CN109642925B

CN109642925B - Electronic device and method for monitoring an analog signal

Info

Publication number: CN109642925B
Application number: CN201780052615.0A
Authority: CN
Inventors: 宋德强; 孔晓华; B·班迪达; 高卓
Original assignee: Qualcomm Inc
Current assignee: Qualcomm Inc
Priority date: 2016-08-30
Filing date: 2017-08-09
Publication date: 2021-08-31
Anticipated expiration: 2037-08-09
Also published as: CN109642925A; US9729163B1; WO2018044519A1; EP3507610A1

Abstract

An Integrated Circuit (IC) chip includes on-chip analog signal monitoring circuitry for monitoring a set of analog signals generated by one or more mixed signal cores within the IC chip, converting the analog signals to digital signals, storing the digital signals in on-chip memory, and providing the digital signals to test equipment upon request. The analog signal monitoring circuit includes an on-chip reference generator for generating precise voltages and/or currents, a switching network for routing selected reference signals to an analog-to-digital converter (ADC) for calibration purposes and for routing selected analog signals from one of the mixed signal cores to the ADC for digitization purposes. The IC chip further includes on-chip memory for storing the digitized analog signals for subsequent access by test equipment for analysis. The IC chip includes a digital-to-Analog Test Point (ATP) for outputting a digitized analog signal.

Description

Electronic device and method for monitoring an analog signal

Cross Reference to Related Applications

This application claims priority and benefit to the non-provisional application No.15/251,861 filed at united states patent and trademark office at 2016, 8, 30, which is hereby incorporated by reference in its entirety for all applicable purposes.

Technical Field

Some aspects of the present disclosure generally relate to diagnosis and error correction of Integrated Circuits (ICs), and in particular, to apparatus and methods for in-situ or on-chip analog signal diagnosis and error correction using calibrated analog-to-digital converters.

Background

An Integrated Circuit (IC) chip or die sometimes includes a collection of analog or mixed (analog and digital) signal cores. For example, the IC chip may include a Universal Serial Bus (USB) physical interface (USB PHY) core, a personal component interconnect express (PCIe) physical interface (PCIe PHY) core, and a universal flash memory (UFS) physical interface (UFS PHY) core. Each of these cores may generate a set of one or more analog signals that need to be monitored for testing, error correction, optimization, circuit robustness, operational verification, and/or other purposes.

Disclosure of Invention

The following presents a simplified summary of one or more embodiments in order to provide a basic understanding of such embodiments. This summary is not an extensive overview of all contemplated embodiments, and is intended to neither identify key or critical elements of all embodiments nor delineate the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.

Aspects of the present disclosure relate to an apparatus including an Integrated Circuit (IC). The IC includes a first core configured to generate a first set of one or more analog signals; a reference generator configured to generate a set of one or more reference signals; an analog-to-digital converter (ADC) configured to generate a digital signal based on a selected analog signal of a first set of one or more analog signals; and a switching network configured to selectively route a selected one of the set of one or more reference signals to the ADC for calibrating the ADC, and to selectively route a selected one of the first set of one or more analog signals to the ADC for generating the digital signal.

Another aspect of the disclosure relates to a method of monitoring an analog signal. The method includes generating an analog signal within a first core of an Integrated Circuit (IC) chip; generating a reference signal within a second core of the IC chip; and generating a digital signal within the IC chip based on the analog signal and the reference signal.

Another aspect of the disclosure relates to an apparatus comprising means for generating an analog signal within a first core of an Integrated Circuit (IC) chip, means for generating a reference signal within a second core of the IC chip, and means for generating a digital signal within the IC chip based on the analog signal and the reference signal.

To the accomplishment of the foregoing and related ends, the one or more embodiments comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more embodiments. These aspects are indicative, however, of but a few of the various ways in which the principles of various embodiments may be employed and the described embodiments are intended to include all such aspects and their equivalents.

Drawings

FIG. 1 shows a diagram depicting an exemplary test system according to one aspect of the present disclosure.

Fig. 2A illustrates a block diagram of an exemplary IC including an on-chip analog signal monitoring signal according to another aspect of the disclosure.

Fig. 2B illustrates a block diagram of another exemplary IC in accordance with another aspect of the disclosure.

Fig. 2C illustrates a block diagram of yet another exemplary IC in accordance with another aspect of the disclosure.

FIG. 3 illustrates a schematic diagram of another exemplary on-chip analog signal monitoring circuit according to another aspect of the present disclosure.

FIG. 4 illustrates a flow chart of an exemplary method of monitoring an analog signal according to another aspect of the present disclosure.

Detailed Description

The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. It will be apparent, however, to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

Many Integrated Circuit (IC) chips (also known as "IC dies") include analog or mixed (digital and analog) signal cores, each configured to generate a set of one or more analog signals. The analog signal may include a Direct Current (DC) signal, as well as a low frequency analog signal. Typically during the prototyping phase, these analog signals need to be monitored to diagnose the corresponding cores, to test the design's functionality, and for design optimization and robustness purposes. An example of the IC is described below.

FIG. 1 shows a diagram depicting an exemplary test system 100 in accordance with an aspect of the present disclosure. Test system 100 includes an IC 110 as a Device Under Test (DUT) having an IC chip 130 located within an IC package 120. In this example, IC chip 130 includes a set of analog or mixed

signal cores

132, 134, and 136. For example, one of the cores may be a Universal Serial Bus (USB) physical interface (USB PHY), another of the cores may be a personal component interconnect express (PCIe) physical interface (PCIe PHY), and another of the cores may be a universal flash memory (UFS) physical interface (UFS PHY).

Each of the analog or mixed

signal cores

132, 134, and 136 is configured to generate a set of one or more analog signals (e.g., DC, low frequency signals, bias conditions, current, and voltage). One or more of the analog signals of each

core

132, 134, and 136 may be selectively output for testing, error correction, optimization, and/or other purposes. For example, the analog or mixed signal core 132 may selectively output a set of one or more analog signals (collectively referred to as V) via a switch SW1_A1) To the solder bumps 142 of the IC chip 130. Similarly, the analog or mixed signal core 134 may selectively output another set of one or more analog signals (collectively referred to as V) via a switch SW2_A2) To the solder bumps 144 of the IC chip 130. And, the analog or mixed signal core 136 may selectively output a set of one or more analog signals to the solder bumps 146 of the IC chip 130 via the switch SW 3.

IC package 120 may include a collection of Ball Grid Array (BGA)

solder balls

122, 124, and 126 coupled to

solder bumps

142, 144, and 146 of analog or mixed

signal cores

132, 134, and 136 via

package interconnects

152, 154, and 156, respectively. Analog signal V via

interconnects

152, 154, and 156, respectively_A1、V_A2And V_A3To BGA

solder balls

122, 124, and 126 for testing, diagnostic, error correction, optimization, and/or other purposes. Thus, BGA

solder balls

122, 124 and 126 serve as Analog Test Points (ATP) for IC 110.

A test instrument 170 may be electrically coupled to each

BGA solder ball

122, 124, 126 via a general purpose input/output (GPIO) interface 160 (e.g., connector and cable) to couple the analog signal V_A1、V_A2And V_A3Is selectively provided to the test instrument. During the prototyping of IC 110, analog signals V from

cores

132, 134, and 136 are analyzed by test instrument 170_A1、V_A2And V_A3To ensure signal alignment and to result in robust performance of the IC 110. In the final commercial product, the analog signal V may be analyzed by the test instrument 170_A1、V_A2And V_A3To troubleshoot the IC 110 in the field.

There are several disadvantages to the IC 110. First, during the manufacture of the IC, it may not be desirable for confidential and/or proprietary reasons for the customer to access the analog signals V via the

BGA balls

122, 124, and 126_A1、V_A2And V_A3A collection of (a). Further, the

interconnections

152, 154, and 156 and the

BGA solder balls

122, 124, and 126 are implemented for test purposes in terms of IC package area to output the analog signal V_A1、V_A2And V_A3There is a cost to the set of. Reduce or even eliminateThe number of package interconnects and BGA solder balls for testing purposes may allow better utilization of IC package area.

Briefly, one aspect of the present disclosure is to create an on-chip scheme to monitor analog signals from one or more analog or mixed signal cores. By creating an on-chip solution, the number of BGA solder balls and package interconnects used for analog signal testing purposes may be reduced or even eliminated, which facilitates a reduction in IC chip and package size, and/or allows area for other purposes.

In another aspect, an on-chip analog signal monitoring scheme converts an analog signal from an analog or mixed signal core to a digital signal for storage in a memory core on an IC chip. In this regard, the on-chip analog signal monitoring scheme facilitates testing cores in the field. For example, a test instrument running diagnostic software may be connected to test interface circuitry within the IC chip to access stored data of the analog signal for testing, monitoring, diagnostic, error correction, optimization, and/or other purposes.

The on-chip analog signal monitoring scheme is described in more detail below with reference to various exemplary embodiments.

Fig. 2A illustrates a diagram of an exemplary IC 200 including an on-chip analog signal monitoring circuit according to another aspect of the disclosure. In particular, IC 200 includes an IC chip 220 located within an IC package 210. IC chip 220 may include one or more analog or mixed-signal cores 232-1 through 232-L, where L is one or more integers. As examples, cores 232-1 through 232-L may be UFS PHY, PCIe PHY, and USB PHY cores.

Each of the cores 232-1 through 232L is configured to generate a set of analog signals that are desired to be monitored for configuration, optimization, robustness, diagnostics, error correction, testing, and/or other purposes. For example, the analog or mixed signal core 232-1 may generate an analog signal V_A11To V_A1MWherein M is one or more integers. Similarly, the analog or mixed signal core 232-L may generate an analog signal V_AL1To V_ALNWherein N is one or more integers.

Analogue or mixed signalsThe cores 232-1 to 232-L include switches for selectively outputting analog signals or voltages to be monitored. For example, the core 232-1 includes a set of switches SW 11-SW 1M for coupling an analog signal or voltage V_A11To V_A1MSelectively outputs one of the analog signals or voltages to the solder bumps 234-1 of the IC chip 220. Similarly, core 232-L includes a set of switches SWL1 through SWLM for coupling analog signals or voltages V_AL1To V_ALNSelectively outputs one of the analog signals or voltages to the solder bumps 234-L of the IC chip 220.

Solder bumps 234-1 through 234-L may be electrically coupled to analog bus 236, at least a portion of which may be implemented as interconnects for IC package 210. Analog bus 236 may be electrically coupled to at least one solder ball 238 of the set of BGA solder balls of IC package 210. The test equipment may be coupled to at least one BGA solder ball 238 for testing and other related purposes as described herein. Thus, at least one BGA solder ball 238 may be used as an analog ATP.

The IC chip 220 further includes an on-chip analog signal monitoring circuit 240. To reduce complexity and save area of the IC chip, the on-chip analog signal monitoring circuit 240 may be implemented in an already existing core, such as a reference generation core. The reference generating core may be a core that generates an accurate reference voltage and/or current.

Accordingly, the on-chip analog signal monitoring circuit 240 includes a reference generator 242 configured to generate a set of one or more reference signals. For example, reference generator 242 may generate reference voltage V_BG(e.g., bandgap voltage), a first reference current (e.g., inversely proportional to the resistor current I)_P) And a second reference current (e.g., constant current I)_E). As shown, reference generator 242 may provide reference signal V via impedance-calibrated electrical paths within IC chip 220_BG,I_PAnd I and_Eto one or more of the analog or mixed signal cores 232-1 through 232-L. The cores 232-1 to 232-L all use a reference signal V_BG,I_PAnd I and_Eto perform it on any one or more reference signalsAnd (4) designing operation.

The on-chip analog signal monitoring circuit 240 also includes a switching network 244 and an analog-to-digital converter (ADC) 246. The switch network 244, in turn, includes switches SW01 through SW 06. Subsets of switches SW01 through SW03 are coupled to outputs of reference generator 242 (for generating V), respectively_BG,I_PAnd I and_E) And switch SW 04. Switch SW05 is coupled between switch SW04 and the input of ADC 246. Switch SW06 is coupled between switch SW04 and solder bumps 235 of IC chip 220. Solder bumps 235 are then coupled to analog bus 236 and BGA solder balls 238.

IC chip 220 further includes a controller 260 and a memory core 250 coupled to test interface circuitry 270. The memory core 250 is configured to store the digitized analog voltage V generated by the ADC246_DFor subsequent external access by the test equipment via the test interface circuit 270, the at least one solder bump 272, and the at least one solder ball 274. The controller 260 may be configured to generate switch control signals SW _ CNTL for controlling the states of the various switches described herein, such as switches SW 01-SW 06, SW 11-SW 1M, SWL 1-SWLN. In this regard, the controller 260 may receive external test configuration signals from the test equipment, e.g., via at least one BGA solder ball 274, at least one solder bump 272, and test interface circuitry 270 for setting a desired test environment for monitoring the analog signals.

In operation, the reference signal V may be used_BG、I_PAnd I_ETo calibrate the ADC 246. For example, if the ADC246 is a voltage mode ADC, a bandgap voltage reference signal V may be used_BGTo calibrate the ADC. Alternatively, the current reference signal I may also be used by including at least one resistor for converting the current reference signal into a voltage_PAnd I_EThe voltage mode ADC is calibrated by any of the current reference signals and the converted voltage is used to calibrate ADC 246. If the ADC246 is a current mode ADC, a current reference signal I may be used_PAnd I_ETo directly calibrate the ADC.

In this regard, the controller 280 mayA test configuration signal is received for calibrating ADC246 using the selected reference. In response, the controller 260 generates the switch control signal SW CNTL to configure the switches of the switch network 244 for calibrating the ADC246 using the selected one of the reference signals. For example, if the reference signal V is to be used_BGCalibrating ADC246, controller 260 generates switch control signal SW CNTL to close switches SW01, SW04, and SW05, and to open switches SW02, SW03, and SW 06. In this configuration, the reference signal V is provided via switches SW01, SW04, and SW05_BGTo ADC 246. The other switches SW02, SW03 and SW06 are opened to prevent the selected reference signal V_BGLeakage and interference.

Similarly, if a reference signal I is to be used_PCalibrating ADC246, controller 260 generates switch control signal SW CNTL to close switches SW02, SW04, and SW05 and open switches SW01, SW03, and SW 06. In this configuration, the reference signal I is provided via switches SW02, SW04, and SW05_PTo ADC 246. The other switches SW01, SW03 and SW06 are opened to prevent the selected reference signal I_PLeakage and interference.

In a similar manner, if a reference signal I is to be used_ECalibrating ADC246, controller 260 generates switch control signal SW CNTL to close switches SW03, SW04, and SW05, and to open switches SW01, SW02, and SW 06. In this configuration, the reference signal I is provided via switches SW03, SW04, and SW05_PTo ADC 246. The other switches SW01, SW02 and SW06 are opened to prevent the selected reference signal I_PLeakage and interference.

The ADC246 may also be calibrated using an external reference signal. An external reference signal may be provided to ADC246 via BGA solder balls 238. In this regard, the controller 260 generates the switch control signal SW CNTL to configure the switches of the switch network 244 for calibrating the ADC246 using the external reference signal. For example, the controller 260 generates the switch control signal SW _ CNTL to close the switches SW05 and SW06 and open the switches SW01 to SW 04. Additionally, in this configuration, the controller 260 may generate switch control signals to open all of the switches SW11 through SW1M through SWL1 through SWLN in the analog or mixed signal cores 232-1 through 232-L so as not to interfere with the outsideA reference signal. Thus, the external reference signal is applied to ADC246 via BGA solder balls 238, analog bus 236, solder bumps 235, and switches SW06 and SW 05. Similarly, switches SW 01-SW 04 are opened for the internal reference signal V_BG,I_PAnd I and_Edoes not interfere with the external reference signal applied to ADC 246.

To digitize a selected analog signal from one of the analog or mixed signal cores 232-1 through 232-L, the controller 260 configures the switches to route selected ones of the analog voltages to the ADC246 for digitization based on test configuration commands received via the test interface circuit 270. In this regard, the controller 260 generates the switch control signal SW _ CNTL to close the switches of the switches SW11 to SWLN corresponding to the analog voltage to be digitized, and opens the remaining switches SW11 to SWLM. Additionally, according to the test configuration, controller 260 generates switch control signal SW _ CNTL to close switches SW05 and SW06 for routing to ADC246 via selected ones of switches SW11 to SWLN, switch SW06, and switch SW 05. Further, according to this configuration, the controller 260 generates the switch control signal SW _ CNTL to turn off at least the switch SW04 and optionally the switches SW01 to SW03, so that the internal reference signal V_BG,I_PAnd I and_Eand does not interfere with the selected analog voltage applied to the ADC 246.

The ADC246 then converts the selected analog signal to a digital signal V_DFor storage in the memory 250. The process may repeat for digitizing other analog signals V as desired according to test configuration commands received by controller 260 via test interface circuit 270_A11To V_ALN. Memory core 250 may then receive a read command to digitize one or more analog voltages V_DOutput to external (e.g., software-based) diagnostic or test equipment via test interface circuitry 270.

Based on the received test configuration commands, the controller 260 may also cause the analog voltage V to be_A11To V_ALNTo the analog ATP 238 for performing direct monitoring of the analog signals by the external test equipment. In this regard, the controller 260 is based onIn response to a test configuration command received through the test interface circuit 270, the switch control signal SW _ CNTL is generated to close the switch corresponding to the selected analog voltage among the switches SW11 through SWLN and to open the remaining switches among the switches SW11 through SWLN. Additionally, according to the test configuration, the controller 260 generates the switch control signal SW CNTL to open the switch SW06 so that the switch network 244 does not affect routing of the selected analog signals to the analog ATP 238.

Thus, the on-chip analog signal monitoring circuit 240 facilitates monitoring and digitization of analog signals from an analog or mixed signal core, and subsequent storage of the digitized signals. For testing and/or diagnostic purposes, a field or development engineer may connect a software-based test device to the test interface circuit 270 via the at least one bump and the at least one BGA solder ball 274, and read all desired digitized analog voltages from the memory core 250. The test equipment may then analyze the data to assist engineers in error correction and/or optimization of the IC 200. Alternatively, or in addition, if error correction and/or optimization of the IC 200 is desired, a field or development engineer may connect test equipment to the analog ATP 238 to directly monitor the analog signals.

Fig. 2B illustrates a block diagram of another exemplary IC 202 in accordance with another aspect of the disclosure. IC 202 is a variation of IC 200 and includes many similar elements as indicated by the same reference numerals. As previously described, analog ATP 238 may not be needed because all of the digitized analog signals may be monitored by external test equipment via test interface circuit 270. Accordingly, the IC 202 may optionally be configured to eliminate the analog ATP 238. This facilitates the fabrication of smaller IC packages 210 or facilitates the use of areas previously intended for the ATP 238 for other purposes.

Fig. 2C illustrates a block diagram of yet another exemplary IC 204 in accordance with another aspect of the disclosure. IC 204 is a variation of IC 202 and includes many similar elements as indicated by the same reference numerals. As previously described, analog bus 236 need not be implemented as a package interconnect, as analog ATP 238 may not be needed. Thus, IC 204 may optionally be configured as an analog bus 236 implemented within IC chip 220. In addition, this may further facilitate smaller IC packages 210 or facilitate previously intentional design of area for analog bus interconnects 236 for other purposes.

FIG. 3 illustrates a schematic diagram of another exemplary on-chip analog signal monitoring circuit 300 in accordance with another aspect of the present disclosure. The monitoring circuit 300 may be an exemplary implementation of the monitoring circuit 240 previously described. The monitoring circuit 300 includes a switch network 310 having pass gates PG 1-PG 7 and an ADC 320. Control signals Sel <1> to Sel <7> set the states (on or off) of transfer gates PG1 to PG7, respectively. The control signals Sel <1> to Sel <7> may be generated by the controller 260 as the switch control signals SW _ CNTL.

In this example, there are three (3) reference signals V available_BG、I_EAnd I_P. Band gap reference signal V_BGIs applied to the input of a pass gate PG 1. Control signal Sel<1>And its complementary signal

Is applied to the gate and complementary gate of pass gate PG 1. Constant current reference signal I_EIs applied to the input of a pass gate PG 2. Control signal Sel<2>And its complementary signal

Is applied to the gate and complementary gate of pass gate PG 2. Furthermore, the inversely proportional resistor current I_PTo the input of a pass gate PG 3. Control signal Sel<3>And its complementary signal

To the gate of pass gate PG3 and to the complementary gate.

Pass gates PG1 and PG2 include outputs coupled to inputs of pass gate PG 4. Control signal Sel<4>And its complementary signal

Is applied to the gate and complementary gate of pass gate PG 4. The pass gates PG3 and PG4 include outputs coupled to inputs of pass gates PG5 and PG6. Control signal Sel<5>And its complementary signal

Is applied to the gate and complementary gate of pass gate PG 5. Control signal Sel<6>And its complementary signal

Is applied to the gate and complementary gate of pass gate PG 6.

Pass gate PG5 includes an output coupled to an input of ADC 320. Pass gate PG6 includes an output coupled to analog signal bus 340 and to an input of pass gate PG 7. Control signal Sel<7>And its complementary signal

Is applied to the gate and complementary gate of pass gate PG 7. Pass gate PG7 includes an output coupled to an input of ADC 320.

Analog signal V to be monitored_ACoupled to an analog signal bus 340 is a source 320 (e.g., an analog or mixed signal core). Further, alternatively, BGA solder balls 350 may be coupled to analog signal bus 340. As described in more detail below, the ADC 320 is configured to digitize an analog voltage V_ATo generate a digitized signal V_D。

In operation, to select an internal reference signal (e.g., V)_BG、I_EOr I_P) Control signal Sel sent to ADC 320 for calibration purposes<5>Is set to logic high to turn on the transmission gate PG5, and controls the signal Sel<6>And Sel<7>Is set to logic low to turn off pass gates PG6 and PG 7. Further, corresponding to the selected reference signal (V)_BG、I_EAnd I_PSelected item of (1) of a control signal (Sel)<1>To Sel<3>The selected signal) is set to logic high to turn on the corresponding pass gate (the selected one of pass gates PG1, PG2, and PG 3). Further, corresponding to the unselected reference signal (V)_BG,I_EAnd I and_Ptwo not selected) of the control signal (Sel)<1>To Sel<3>Two of not selected) are providedA logic low is set to turn off the corresponding pass gate (unselected two of pass gates PG1, PG2, and PG 3). If one of the selected reference signals is V_BGOr I_EThen control signal Sel<4>Is set to logic high to turn on pass gate PG 4. Otherwise, the control signal Sel<4>May be set to a logic low to turn off pass gate PG4 if the selected reference signal is I_P。

Thus, via the selected pass gate (the selected one of pass gates PG1, PG2, and PG 3), pass gate PG4 (if the selected reference signal is V)_BGOr I_E) And pass gate PG5 routes the selected reference signal to ADC 320. Pass gates PG6 and PG7 are turned off to prevent the selected reference signal from leaking out to the analog bus 340 and to prevent any signal or noise effects residing in the analog bus from routing the selected reference signal to the ADC 320.

To convert the analog signal V_ASent to ADC 320 for digitization, control signal Sel<7>Is set to logic high to turn on the pass gate PG7, and the remaining control signal Sel<1>To Sel<6>May be set to logic low to turn off pass gates PG 1-PG 6, respectively. Thus, the analog signal V is transmitted via the transmission gate PG7_ARoute to ADC 320, and turn off other pass gates PG 1-PG 7 to prevent analog signal V when it is routed to ADC 320_ALeakage and interference.

In order to select the reference (V)_BG、I_EAnd I_PTo the BGA ball 350, a control Signal (SEL) corresponding to the selected reference signal<1>To SEL<3>The selected signal) is set to logic high to turn on the corresponding pass gate (the selected one of pass gates PG1, PG2, and PG 3). If one of the selected reference signals is V_BGOr I_EThen control signal Sel<4>Is set to logic high to turn on pass gate PG 4. Otherwise, the control signal Sel<4>May be set to a logic low to turn off pass gate PG4 if the selected reference signal is I_P. Control signal Sel<6>Is set to logic high to turn on pass gate PG 6. Control signal Sel<5>And Sel<6>Can be set to logic low to turn offPass gates PG5 and PG7 are disabled.

Thus, via the selected pass gate (selected one of pass gates PG1, PG2, and PG 3), pass gate PG4 (if the selected reference signal is V)_BGOr I_E) And a pass gate PG6 that sends the selected reference signal to BGA solder balls 350. Pass gates PG5 and PG7 are turned off to prevent leakage and interference of the selected reference signal when it is routed to BGA solder balls 350.

To disconnect monitor circuit 300 from analog bus 340, control signals Sel <6> and Sel <7> are set to logic low to turn off pass gates PG6 and PG 7.

FIG. 4 illustrates a flow chart of an exemplary method 400 of monitoring an analog signal according to another aspect of the present disclosure. The method 400 includes generating an analog signal within a first core of an IC chip (block 402). Examples of means for generating an analog signal include any circuit arrangement within any of the analog or mixed signal cores 234-1 through 234-L of the IC chip 220.

The method 400 further includes generating a reference signal within a second core of the IC chip (block 404). An example of an apparatus for generating a reference signal within a second core of an IC chip includes a reference generator 242 that generates a reference signal V within a reference generation core of IC chip 220_BG,I_PAnd I and_Eany one of the reference signals.

The method 400 also includes generating a digital signal within the IC chip based on the analog signal and the reference signal (block 406). An example of an apparatus for generating a digital signal within an IC chip based on an analog signal and a reference signal includes an analog-to-digital converter (ADC) 246.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An electronic device, comprising:

an Integrated Circuit (IC) chip, comprising:

a first core configured to generate a first set of one or more analog signals;

a reference generator configured to generate a set of one or more reference signals;

an analog-to-digital converter (ADC) configured to generate a digital signal based on a selected analog signal of the first set of one or more analog signals; and

a switching network configured to:

selectively route selected reference signals of the set of one or more reference signals to the ADC for calibrating the ADC; and

selectively route selected ones of the first set of one or more analog signals to the ADC for generating the digital signal.

2. The electronic device of claim 1, wherein the reference generator, the switching network, and the ADC are implemented in a second core of the IC chip.

3. The electronic device of claim 1, wherein at least one reference signal of the set of one or more reference signals is applied to the first core.

4. The electronic device of claim 1, wherein the IC chip further comprises a memory core configured to store the digital signal.

5. The electronic device of claim 4, further comprising a test interface circuit coupled to the ADC and the memory core.

6. The electronic device of claim 5, wherein the test interface circuit is implemented in the IC chip.

7. The electronic device defined in claim 5 further comprising an IC package, wherein the IC chip is encapsulated within the IC package.

8. The electronic device of claim 7, wherein the IC package further comprises at least one Ball Grid Array (BGA) solder ball coupled to the test interface circuit, wherein the at least one BGA solder ball is configured to be coupled to a test device for outputting the digital signal for analysis purposes.

9. The electronic device of claim 1, further comprising a controller configured to generate control signals for controlling the switching network to route selected ones of the one or more reference signals to the ADC and to route selected ones of the one or more analog signals to the ADC.

10. The electronic device of claim 1, wherein the IC chip further comprises a second core configured to generate a second set of one or more analog signals; and the apparatus further includes an analog bus coupled to the first and second cores and to the switching network, wherein the analog bus and the switching network are configured to route selected ones of the first or second sets of one or more analog signals to the ADC.

11. The electronic device of claim 10, wherein the analog bus is implemented within the IC chip.

12. The electronic device defined in claim 11 further comprising an IC package, wherein the IC chip is encapsulated within the IC package.

13. The electronic device of claim 12, wherein the IC package further comprises at least one Ball Grid Array (BGA) solder ball coupled to the analog bus.

14. The electronic device of claim 13, wherein the at least one BGA solder ball is configured to be coupled to a test device for outputting a selected analog signal from the first set of one or more analog signals or the second set of one or more analog signals for analysis purposes.

15. The electronic device of claim 13, wherein the at least one BGA solder ball is configured to be coupled to a source of an external reference signal, wherein the analog bus and the switch network are configured to route the external reference signal to the ADC for calibrating the ADC.

16. The electronic device of claim 12, wherein the analog bus is implemented as an interconnect of the IC package.

17. A method for monitoring an analog signal, comprising:

generating an analog signal within a first core of an Integrated Circuit (IC) chip;

generating a reference signal within a second core of the IC chip; and

a first digital signal is generated within the IC chip based on the analog signal and the reference signal.

18. The method of claim 17, wherein generating the first digital signal occurs within the second core of the IC chip.

19. The method of claim 17, further comprising storing the first digital signal within a memory core of the IC.

20. The method of claim 19, further comprising routing the first digital signal from a memory core of the IC to an external test device.

21. The method of claim 17, further comprising routing the analog signal from the second core of the IC to an external test device.

22. The method of claim 17, further comprising:

generating a second analog signal within a third core of the IC;

generating a second digital signal within the IC chip based on the second analog signal and the reference signal or another reference signal; and

storing the first digital signal and the second digital signal in a memory core within the IC.

23. The method of claim 22, further comprising routing the first and second digital signals from a memory core of the IC to an external test device.

24. An electronic device, comprising:

means for generating an analog signal within a first core of an Integrated Circuit (IC) chip;

means for generating a reference signal within a second core of the IC chip; and

means for generating a first digital signal within the IC chip based on the analog signal and the reference signal.

25. The electronic device of claim 24, wherein the means for generating the first digital signal is implemented within a second core of the IC chip.

26. The electronic device of claim 24, further comprising means for storing the first digital signal within the IC.

27. The electronic device of claim 24, further comprising means for routing the digital signal from the means for storing to an external test equipment.

28. The electronic device of claim 24, further comprising means for routing the analog signal from the second core of the IC to an external test device.

29. The electronic device of claim 24, further comprising:

means for generating a second analog signal within a third core of the IC;

means for generating a second digital signal within the IC chip based on the second analog signal and the reference signal or another reference signal; and

means for storing the first digital signal and the second digital signal in a memory core within the IC.

30. The electronic device of claim 29, further comprising means for routing the first and second digital signals from a memory core of the IC to an external test device.