CN109639366B - Signal pulse width modulation and demodulation method based on two-wire bus communication - Google Patents
Signal pulse width modulation and demodulation method based on two-wire bus communication Download PDFInfo
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Abstract
The invention relates to a signal pulse width modulation and demodulation method based on two-wire bus communication. The method aims at a two-wire bus which has nonpolarity, one-master multi-slave half-duplex communication and power supply, a communication frame structure comprises a subframe, the subframe comprises a start bit, N information bits and an end bit, a downlink communication adopts a differential voltage pulse width modulation and downlink standard pulse width value configurable mode, an uplink communication frame adopts a current pulse width modulation and uplink standard pulse width value fixed mode, a master station broadcasts a standard pulse width communication frame before the downlink normal communication, a slave station receives and detects a downlink standard pulse width value, and modulated digital information is demodulated out based on the uplink standard pulse width value and the downlink standard pulse width value during the uplink normal communication and the downlink normal communication. Through the mode, the anti-interference capability, the communication effectiveness and reliability and the application flexibility of the dual-wire bus can be improved, the processing complexity and the equipment cost are reduced, the communication distance is prolonged, the application scene is expanded, and the reliable communication and power supply of the bus are guaranteed.
Description
Technical Field
The invention relates to the technical field of bus communication, in particular to a signal pulse width modulation and demodulation method based on double-wire bus communication.
Background
Because the working environment of the industrial equipment is relatively severe, and higher requirements are provided for the aspects of long-distance communication, interference resistance, reliability, practicability, convenience (construction and maintenance), cost saving and the like, the industrial equipment communication usually adopts a two-wire system communication mode, and mainly comprises a CAN (controller Area network) bus, an MBUS (Meter BUS) bus and the like.
The CAN bus is widely used in industrial control and automotive fields. The CAN bus adopts a two-wire differential voltage amplitude modulation mode and a serial communication mode; the system supports a multi-host mode, and can transmit and receive data in a point-to-point, one-to-many and broadcast centralized mode; the method has the advantages of strong real-time performance, long transmission distance, strong anti-electromagnetic interference capability, low cost and the like; however, the dual-wire bus has polarity, the master station cannot supply power to the slave station through the bus, and the interference resistance is reduced due to power supply fluctuation interference and attenuation of differential voltage amplitude in a transmission path, so that a plurality of power supply application scenes cannot be applied.
The MBUS bus is widely applied to building and industrial energy consumption data acquisition. The European standard double-wire bus of the MBUS bus adopts a double-wire serial communication mode and has no polarity; the method supports a master multi-slave mode, the downlink transmits data through a differential voltage amplitude modulation mode, and the uplink transmits information through a current amplitude modulation mode; the method has the advantages of strong real-time performance, long transmission distance, strong anti-interference capability, low cost and the like; however, the signal size is pulse amplitude, common mode additive interference, power supply fluctuation interference, remote communication transmission path attenuation and the like can reduce the anti-interference capability and reliability of system communication, the parameter configuration is lack of flexibility, and the method is not suitable for being used in special application scenes with very high safety and reliability (such as remote control digital detonator ignition, digital firework ignition and the like) and cannot well meet the application requirements.
Based on the deficiencies in two-wire bus communication described above, digital Pulse Width Modulation (PWM) may be used. The anti-interference performance, the convenience in control and use, the transmission quality and the reliability are improved, the processing complexity and the equipment cost are reduced, the communication distance is prolonged, the parameter configuration flexibility is increased, the application scene is expanded, the differential voltage PWM can provide bus power supply, and meanwhile, the communication information transmission is realized.
The invention relates to a signal pulse width modulation and demodulation method based on two-wire bus communication, which is also a master-slave half-duplex communication technology, wherein a differential pulse width modulation mode has the characteristics of long communication distance, strong anti-interference capability, flexible power supply, high adaptability and configurability and the like, and can be widely applied to various instrument data acquisition and special application scenes with high requirements on safety and reliability.
Disclosure of Invention
In view of the problems of the existing bus communication technology, the invention aims to provide a signal pulse width modulation and demodulation method based on two-wire bus communication, so as to overcome the problems of the existing technology, improve the anti-interference capability, realize reliable communication, accurate signal modulation and demodulation and increase the application scenes of the two-wire bus communication.
The invention aims to realize the technical scheme that the invention provides a signal pulse width modulation and demodulation method based on two-wire bus communication, which comprises the following steps.
(1) The downlink communication adopts a differential voltage pulse width modulation mode, and the uplink communication (from the station to the master station) adopts a current pulse width modulation mode.
(2) The communication frame comprises one or more sub-frames, each sub-frame comprising a start bit and an end bit, N (positive integer) information bits.
(3) The signal width of the start bit and the end bit is equal to the standard width value, and the signal width after the modulation of the digital signal 0 is equal to the corresponding standard pulse width value TdownOr TupIs M times, the signal width after the modulation of the digital signal 1 is equal to the corresponding standard pulse width value TdownOr TupL times, said L and M being positive numbers, L and M being unequal and not equal to 1.
(4) The downlink standard pulse width value Tdown can be set according to application requirements, and the uplink standard pulse width value TupAnd (4) fixing.
(5) Before downlink normal communication, a master station broadcasts a standard pulse width frame (only comprising a standard-width subframe, and the pulse widths of a start bit, an end bit and N information bits in the subframe are all equal), and a slave station receives and demodulates the standard pulse width frame to obtain the width of the standard pulse width.
(6) When the downlink is in normal communication, the slave station receives the communication frame based on the downlink standard pulse width value TdownAnd demodulating the modulated digital information number.
(7) During uplink normal communication, the main station keeps the differential voltage of the bus unchanged, converts current into voltage through the sampling resistor on the bus, obtains a digital signal after amplifying and comparing the voltage with reference voltage, and then obtains the digital signal according to an uplink standard pulse width value TupAnd demodulating the modulated digital information transmitted by the secondary station.
It can be seen from the above technical solutions that the present invention defines a communication frame structure, a sub-frame structure, and a pulse width of a start bit/an end bit/an information bit for two-wire bus communication, and provides a specific communication frame structure for pulse width modulation and demodulation, that is, a communication rule and a data format that the master and the slave stations must follow.
Aiming at the two-wire bus communication, the invention adopts a differential voltage pulse width modulation mode for downlink communication and a current pulse width modulation mode for uplink communication, thereby effectively improving the anti-interference (common mode interference, power interference, noise interference, path attenuation and the like) capability, improving the control convenience, simplifying the equipment and reducing the cost.
The invention defines the downlink standard pulse width T based on supporting more application scenesdownCan be set according to application requirements, and the standard pulse width T of the uplinkupAnd fixation is beneficial to simplifying signal modulation and demodulation processing, saving equipment cost and reducing processing difficulty.
The invention is based on the clock-free signal transmission of the two-wire bus communication, the slave station asynchronously samples the communication signal sent by the master station, and sends the standard pulse width frame before the downlink normal communication, thereby ensuring that the slave station detects the value of the downlink standard pulse width and providing guarantee for the slave station to receive and accurately demodulate the downlink communication frame.
The invention provides a modulation and demodulation method of a downlink communication frame and a modulation and demodulation method of an uplink communication frame based on two-wire bus communication, which realize one master and multiple slaves of a two-wire bus, have no polarity of the bus, can communicate and remotely supply power to the bus, improve the anti-interference capability and the communication transmission quality, improve the convenience of maintenance and reduce the construction and maintenance cost.
Drawings
FIG. 1 is a flow chart of an embodiment of the present invention.
Fig. 2a is a communication frame structure of a two-wire bus of the present invention.
Fig. 2b is a sub-frame structure of the two-wire bus of the present invention.
FIG. 3 is a flow chart of an embodiment of step 2 in FIG. 1.
FIG. 4 is a flowchart of an embodiment of step 3 in FIG. 1.
FIG. 5 is a flowchart of an embodiment of step 4 in FIG. 1.
FIG. 6 is a flowchart of an embodiment of step 5 in FIG. 1.
Detailed Description
The core idea of the invention.
(1) The downlink communication signals adopt a differential voltage pulse width modulation mode, and the uplink communication signals adopt a current pulse width modulation mode.
(2) The communication frame structure is composed of 1 or a plurality of subframes, each subframe comprises a start bit, N (natural number which is not 0) information bits and an end bit, wherein the widths of the start bit and the end bit are standard pulse width values, the modulated signal pulse width of the modulated digital signal 0 is M times (M is a positive number) of the standard pulse width, the modulated signal pulse width of the modulated digital signal 1 is L times of the standard pulse width value, the L and the M are positive numbers, and the L and the M are not equal and are not equal to 1.
(3) The standard pulse width value of the uplink communication frame can be set according to application requirements, and the standard width of the uplink communication frame is a fixed value appointed by a protocol.
(4) Before normal communication, the master station sends a communication frame with continuous standard pulse width to enable the slave station to detect the standard pulse width value, and then during normal communication, the master station sends an information communication frame to enable the slave station to receive and demodulate the modulated digital information.
(5) The master station keeps the differential voltage of the buses (voltage difference between the buses) unchanged, the slave station feeds back information by sending an uplink communication frame (the uplink standard pulse width is a protocol default value) modulated by the current pulse width, and the master station converts the current into the voltage through a sampling resistor on the buses, correspondingly processes the voltage and demodulates the modulated digital information.
By the method, accurate and reliable communication and bus power supply among the master station and the slave stations based on the double-wire bus are realized, and the anti-interference capability is improved for more application scenes.
The embodiments of the present invention will now be further described with reference to the drawings, and first, with reference to fig. 1, the method of the present invention will be described, specifically including the following steps.
Step 11: two-wire bus communication frames and sub-frames.
(1) The communication frame takes a subframe as a unit, and one communication frame comprises one or more subframes; m is an integer, and 1 indicates that the communication frame has only one sub-frame.
(2) The sub-frames can be classified into command sub-frames, data sub-frames, end sub-frames, standard width sub-frames and the like, and one communication frame can be combined by the sub-frames, such as a lower communication frame comprising the standard width sub-frame, the command sub-frame/the end sub-frame, the command sub-frame/the data sub-frame/the end sub-frame; the uplink communication frame includes a data subframe/an end subframe.
(3) The subframe transmission is continuously carried out, namely, no pause exists in the middle; the number of effective subframes of the communication frame can be determined according to application requirements; the communication frame structure is shown in fig. 2 a.
(4) The sub-frame comprises a start bit, an information bit and an end bit, the number of the effective information bits in the sub-frame can be determined according to the application requirement, N is an integer, when N is 1, the number of the effective information bits is only one information bit, and the information bits can be composed of N-1 effective information bits and a parity check bit; the pulse width of the start position and the end position in the subframe is a standard pulse width value, the signal pulse width of the information position corresponding to the digital signal (0 or 1) after modulation is a fixed multiple of the standard pulse width value, for example, the pulse width of the digital modulation signal 1 after modulation is 1.5 times of the standard pulse width value, and the pulse width of the digital modulation signal 0 after modulation is 0.5 times of the standard pulse width value; the structure of the subframe is shown in fig. 2b, which specifically includes.
(a) The initial position: and the start mark of the sub-frame, the pulse width of the communication signal on the bus after modulation is a standard pulse width value.
(b) Information bit: the valid information mark, the pulse width of the communication signal on the bus after the digital signal (0 or 1) is modulated is a fixed multiple (not equal to 1) of the standard pulse width value, and the modulated digital signal can be valid information or check bit information.
(c) An end bit: and (5) marking the end of sub-frame transmission, wherein the pulse width of the communication signal on the bus after modulation is a standard pulse width value.
(5) The standard pulse width value of the downlink communication frame can be set according to application requirements, and the standard pulse width value of the uplink communication frame is fixed, namely, can not be set.
(6) The transmission of the communication frame modulation signal can be high before low, or low before high, and is determined according to application requirements.
(7) The bus communication signal width represents the time during which the signal value (bus differential voltage or bus current) is constant.
Step 12: and (3) modulating and transmitting the differential voltage pulse width of the main station downlink communication frame.
(1) The two-wire bus communication adopts a one-master multi-slave mode, downlink communication frames indicate that a master station transmits communication frames to slave stations, and the structure of the communication frames is shown in fig. 2 a.
(2) The differential voltage pulse width modulation represents that the edge (rising edge and falling edge) of a digital signal (logic value 0 or 1) used for modulation controls the voltage inversion on the bus, the logic value of the digital signal controls the width of bipolar voltage pulse on the bus, and the voltage inversion and pulse width change on the bus are realized to transmit downlink communication signals. If the pulse width of the transmission voltage signal after the modulation of the digital signal 1 is 1.5 times of the value of the downlink standard pulse width, the pulse width of the transmission voltage signal after the modulation of the digital signal 0 is 0.5 times of the value of the downlink standard pulse width, the rising edge (logic value 0 to 1) and the falling edge (logic value 1 to 0) of the digital signal enable the voltage of the two-wire bus to be inverted, and the pulse width of the bus voltage signal after the modulation of the start bit or the end bit is the value of the downlink standard pulse width.
(3) Before normal communication: the master station sends a downlink standard pulse width communication frame, namely the communication frame only comprises 1 subframe, and the pulse widths of the differential voltage signals modulated by all information bits of the subframe are all downlink standard pulse width values Tdown(ii) a And the slave station receives and demodulates the standard pulse width value of the downlink communication frame, and is used for demodulating a downlink digital modulation signal during normal communication.
(4) And (3) during normal communication: the master station sends a downlink normal communication frame, namely the pulse widths of the voltage signals of the start position and the end position of the subframe in the communication frame are both downlink standard pulse width values TdownThe information bit is a differential voltage signal pulse modulated by a digital signal (logic value 0 or 1); the slave station receives the normal communication frame and based on the downlink standard pulse width value T demodulated before the normal communicationdownAnd performing signal demodulation to obtain accurate instructions and data of normal communication frames.
(5) The normal communication frame after the differential voltage pulse width modulation is performed on the digital signal is shown in fig. 3, which specifically includes.
(a) The abscissa: time t, the time unit is set according to application needs, such as milliseconds or seconds.
(b) Ordinate: differential voltage, i.e. difference in voltage DeltaU of the two-wire busbusThe unit V (volts).
（c）Tdown: the value of the downlink standard pulse width, i.e. the time length during which the differential voltage value is constant, can be set according to the application requirements, and the time unit is set according to the application requirements, such as millisecond or second.
(6) Subframe in downlink communication frame: including 1 Start bit (Start), N information bits, 1 Stop bit (Stop).
(a) Start position (Start): the pulse width is a downlink standard pulse width Tdown。
(b) End bit (Stop): the pulse width is a downlink standard pulse width Tdown。
(c) Information bit 0: the pulse width is a downlink standard pulse width TdownM may be a positive number but not equal to 1.
(d) Information bit 1: the pulse width is a downlink standard pulse width TdownL may be a positive number, and may not equal 1, nor M.
(e) Differential voltage: each digital signal for modulation completes the voltage reversal between buses after modulation.
Step 13: and the slave station receives the downlink communication frame and demodulates the modulated digital signal.
The slave station in the two-wire bus communication receives the downlink communication frame sent by the master station, firstly detects the downlink standard pulse width communication frame and obtains the downlink standard pulse width value TdownThen based on the pulse width value modulated by the digital signal (logic 0 and 1), the said down standard pulse width value TdownAnd processing is carried out, the start bit and the end bit of the subframe are judged, and digital logic values (0 and 1) in the subframe are demodulated.
Step 14: and current pulse width modulation and transmission of the communication frame at the slave station.
(1) An uplink communication frame indicates that the slave station transmits a communication frame to the master station, and the structure of the uplink communication frame is shown in fig. 2 a.
(2) When the slave station transmits the upstream communication frame, the bus voltage is kept unchanged (the bus voltage is not inverted).
(3) Current pulse width modulation representing digital signals (logic)Edit value 0 or 1) to control the constant current source to draw current from the bus, and data is transmitted by the change of the current value pulse width on the bus; if the pulse width of the bus current value after the modulation of the digital signal 1 is 1.5 times of the value of the uplink standard pulse width, the pulse width of the bus current value after the modulation of the digital signal 0 is 0.5 times of the value of the uplink standard pulse width, and the pulse width of the bus current value after the modulation of the start bit or the end bit is 0.5 times of the value of the standard pulse width Tup。
(4) The pulse width of the uplink communication frame after the current pulse width modulation is performed on the digital signal is shown in fig. 5, which specifically includes.
(a) The abscissa: time t, the time unit is set according to application needs, such as milliseconds or seconds.
(b) Ordinate: the bus current, including the quiescent current and the increased current Δ I in mA (milliampere) when fed back from a slave station.
(c) Delta I: the differential voltage of the two-wire bus is not changed (the voltage between the buses is not inverted), and a slave station controls the current drawn from the buses by a constant current source, and the unit of the current is mA (milliampere).
（d）Tup: the value of the uplink standard pulse width, i.e. the duration of the current value, is constant, and the time unit is determined according to the application requirement, such as millisecond or second.
(5) Subframe in uplink communication frame: including 1 Start bit (Start), N information bits, 1 Stop bit (Stop).
(a) Start position (Start): the pulse width is an uplink standard pulse width Tup。
(b) End bit (Stop): the pulse width is an uplink standard pulse width Tup。
(c) Information bit 0: the pulse width is an uplink standard pulse width TupM may be a positive number, but not equal to 1.
(d) Information bit 1: the pulse width is an uplink standard pulse width TupL may be a positive number, but is not equal to 1 and M above.
(e) Current pulse: each digital signal for modulation is changed in current value by Δ I after completion of modulation.
Step 15: and the master station receives the uplink communication frame and demodulates the modulated digital signal.
A master station in the double-wire bus communication converts bus current (static current plus current drawn by a constant current source) into voltage through a bus upper sampling resistor, then obtains a digital signal after voltage amplification and comparison with reference voltage, performs related processing on an uplink standard pulse width value Tup, judges a start bit and an end bit of a subframe, and demodulates a modulation digital signal (logic 0 and 1) in the subframe.
It can be seen from the processing procedures in steps 11 to 15 that the present invention implements signal modulation and demodulation based on two-wire bus communication, that is, the master station transmits a differential voltage pulse width modulated communication signal to the slave station, the slave station receives and demodulates downlink modulation digital information, the slave station transmits a communication signal to the master station in a current pulse width modulation mode when the bus voltage is kept unchanged, and the master station converts the current into voltage through the bus sampling resistor and demodulates uplink modulation digital information after performing relevant processing.
The processing procedure in step 13 of fig. 1, referred to in fig. 4, is essentially: the master station sends a communication frame with standard pulse width and only containing one sub-frame before normal communication, so that the pulse widths of continuous information bits of the communication signal are all standard pulse width TdownAll slave stations on the two-wire bus receive the communication frame (also called broadcast frame) with the standard pulse width and demodulate the standard pulse width value Tdown(ii) a During normal communication, all slave stations on the bus receive normal communication frames (containing 1 or more sub-frames) and based on the detected downlink standard pulse width value TdownDemodulating the modulated digital information; during normal communication, the standard pulse width detection circuit works simultaneously, but does not output a valid standard pulse width value, as shown in fig. 4, which includes the following steps.
Step 41: the initialization counter or status register has a value of 0, including signal width counter, signal number counter, signal edge effective register, standard width detection status register, and down standard pulse width value TdownBy default, then step 42 is performed.
Step 42: the slave station receives a differential voltage pulse width modulation signal of a certain subframe in a downlink communication frame sent by the master station, the differential voltage pulse width modulation signal is converted into a digital signal after corresponding processing, if the digital signal is supplied to the slave station through full-wave rectification, the digital signal is obtained through processing of a differential hysteresis voltage comparator, a downlink standard pulse width communication frame is sent before the master station normally communicates, and then the downlink normal communication frame is sent.
Step 43: a determination is made whether the signal edge (rising or falling) is valid and if valid steps 45 and 46 are performed and if not valid step 44 is performed.
Step 44: the semaphore width counter is not 0, i.e. a signal edge has occurred before, the semaphore width counter is incremented by 1 in the current clock cycle (the clock cycle used inside the slave) and the next clock cycle continues with step 43.
Step 45: the semaphore counter is set to 1, i.e. the semaphore counter is set to 1 when the signal edge is active and the sampling clock cycle is active, and the next semaphore counter is ready to count, and then the next clock cycle continues to step 43.
Step 46: if the semaphore counter is not 0, the value of the current semaphore counter is registered, and the steps 47 and 48 are continued.
Step 47: judging whether the standard width detection state register is 1, wherein 1 means the downlink standard width TdownHaving detected that the received downlink communication frame and demodulation processing for normal communication can be performed, step 49 is performed, and if 0, the standard pulse width detection must be performed first, and step 48 is performed.
And 48: no matter whether the downlink standard pulse width detection state register is 1 or not, the standard pulse width detection circuit performs standard detection processing, mainly including that the widths of a start bit, an end bit and all N information bits in a subframe are the same pulse width value, the downlink standard pulse width value is equal to the arithmetic mean value of the pulse widths of all signals in one subframe, namely equal to (the sum of N +2 pulse widths)/(N +2), and the subframe structure is shown in fig. 2 b; after the downlink standard pulse width detection is completed according to the description requirement, the standard pulse width detection state register is set to be 1, and a downlink standard pulse width value T is outputdownCovering the previously detected downlink standard pulse width value; the downlink communication frame continues to be received and step 43 is executed.
Step 49: judging whether the width of the received digital signal is equal to the value T of the downlink standard pulse widthdownIf equal, step 4B is performed, otherwise step 4A is performed.
And step 4B: a start bit or an end bit status register (hereinafter, status register is abbreviated as status) is set to 1, that is, the end bit and the status bit appear in a subframe in pair, if the status of the current start bit is 0, the status of the start bit is set to 1, and the status of the end bit is set to 0; if the current starting bit state is 1, setting the ending bit state to be 1, setting the starting bit state to be 0, and automatically changing the ending bit state of the next period to be 0; step 4C is then performed.
And step 4C: if the start bit status is valid, step 4D is performed, otherwise step 43 is performed.
And step 4D: and judging whether the end bit state is valid, if so, executing the step 4F, otherwise, executing the step 4E.
And 4E: and adding 1 to a signal number (signal pulse number including positive pulses and negative pulses) counter, registering the digital logic value demodulated by the current signal, and continuing to execute the step 4G.
And step 4F: and judging whether the number of the effective signals is equal to N, wherein the number of the effective signals represents N information bits between the start bit and the end bit, if so, executing the step 4H, otherwise, executing the step 4I.
Step 4I: receiving and demodulating the subframe of the current downlink communication frame in a failure mode, namely, the subframe fails due to 2 conditions, in the condition 1, the end bit is not received, the number of effective signals exceeds N, namely, more information bits of the subframe are received before the end bit is received; case 2: receiving the end bit, wherein the number of the effective signals is not equal to N, namely, the information bits of the subframe are received less after the end bit is received; and 4J, if the error occurs in the received subframe, executing the step 4J.
The process of step 15 in fig. 1, see fig. 6, is substantially as follows.
Step 61: initializing the counter and register, specifically including setting the signal width counter to 0, setting the signal number counter to 0, setting the signal edge valid state to 0, and setting the uplink standard pulse width value TupFor the protocol-defined value, the master station maintains the bus differential voltage (i.e., the inter-bus voltage difference) and then performs step 62.
Step 62: the master station switches off the bus sampling resistor to convert the bus current into voltage, performs corresponding processing to obtain a digital signal, and then executes step 63.
And step 63: a determination is made as to whether the signal edge (either rising or falling) is active during the master sampling clock cycle and if so steps 65 and 66 are performed and if not step 64 is performed.
Step 64: the semaphore width counter is not 0, i.e. a signal edge has occurred before, the semaphore width counter is incremented by 1 in the current clock cycle (the clock cycle used inside the master station), and then the next clock cycle continues with step 63.
Step 65: the semaphore counter is set to 1, i.e. the semaphore counter is set to 1 when the signal edge is active and the sampling clock cycle is active, in preparation for the next semaphore count, and then the next clock cycle continues to step 63.
And step 66: if the semaphore counter is not 0, the value of the current semaphore counter is registered, and the process continues to step 67 and step 68.
Step 67: judging whether the received signal width value is equal to the uplink standard pulse width value Tup(the fixed value agreed by the primary and secondary stations, the primary station need not detect the standard pulse width value of the upstream communication frame), if equal, step 68 is performed, otherwise step 69 is performed.
Step 68: a start bit or an end bit status register (hereinafter, status register is abbreviated as status) is set to 1, that is, the end bit and the status bit appear in a subframe in pair, if the status of the current start bit is 0, the status of the start bit is set to 1, and the status of the end bit is set to 0; if the current starting bit state is 1, setting the ending bit state to be 1, setting the starting bit state to be 0, and automatically changing the ending bit state of the next period to be 0; step 6A is then performed.
Step 69: the digital information is demodulated by judging the signal width, if the signal width is equal to TupM times (M may be a positive integer or a decimal), a digital logic value of 0 is demodulated; otherwise, judging if the signal width is equal to TupIs multiplied by L (L may be a positive integer or a decimal), the digital logic value is demodulated to be 1; otherwise the signal is not valid and execution continues at step 6A.
And step 6B: and judging whether the end bit state is valid, if so, executing the step 6D, otherwise, executing the step 6C.
And 6C: and adding 1 to a signal number (signal pulse number including positive pulses and negative pulses) counter, registering the digital logic value demodulated by the current signal, and continuing to execute the step 6E.
And 6E: and judging whether the number of the effective signals is equal to N +1 or not, wherein the number of the normal effective signals is N information bits between the start bit and the end bit, if the number of the effective signals is equal to N +1, executing a step 6G, and if not, executing a step 63.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Those skilled in the art will appreciate that the invention may be practiced without these specific details.
Various modifications and changes may be made by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (2)
1. A signal pulse width modulation and demodulation method based on two-wire bus communication, which has the following common points with the prior MBUS and CMBUS: the communication from the Master of the downlink Master station to the Slave station adopts a voltage modulation mode, the uplink communication from the Slave station to the Master station adopts a current modulation mode, the bus has no polarity, the bus can supply power, the half-duplex communication is realized, a Master-Slave network and a multi-Slave network are realized, and no clock line is used; the different features include: the downlink communication is a differential voltage pulse width modulation mode, the uplink communication is a current pulse width modulation mode, the downlink standard pulse width is configured according to application requirements, the uplink standard pulse width is fixed, a communication frame structure comprises one or more subframes, the subframe transmission is continuously carried out, namely, no pause exists in the middle, the number of effective subframes of the communication frame is determined according to the application requirements, each subframe structure comprises a start bit, N information bits and an end bit, wherein N is a positive integer, the number of the effective information bits in the subframe can be determined according to the application requirements, the width of the start bit and the end bit in the subframe is the standard pulse width, the pulse width of the information bits is a fixed multiple of the standard pulse width, the master station broadcasts a standard pulse width communication frame only comprising one subframe before the downlink normal communication, the pulse widths of the continuous information bits of the communication signals are all the standard pulse width, and the slave station detects the downlink standard pulse width communication frame and obtains the downlink standard pulse width value before the downlink normal communication, the method comprises the steps that a slave station receives a downlink communication frame during downlink normal communication, the downlink communication frame comprises one or more subframes, the slave station processes the downlink communication frame to form a digital signal, the digital signal is processed through a pulse width value modulated by the digital signal and a downlink standard pulse width value, the start position and the end position of the subframe are judged, a digital logic value in the subframe is demodulated, and a standard pulse width detection circuit works simultaneously during normal communication; when the uplink normal communication is carried out, the bus voltage is unchanged, the master station receives an uplink communication frame, the master station converts current into voltage through a sampling resistor on the bus, obtains a digital signal after amplifying and comparing the voltage with reference voltage, and then demodulates modulated digital information transmitted by the slave station according to an uplink standard pulse width value; the transmission of the communication frame modulation signal is determined according to the application requirement, wherein the transmission is carried out in a high order and then in a low order or in a low order and then in a high order; the bus communication signal width represents the time of a signal value which is constant, the signal value represents the bus differential voltage or the bus current, the downlink standard pulse width value is the time length of the differential voltage value which is constant, and the uplink standard pulse width value is the time length of the current value which is constant.
2. The method of claim 1, wherein the method comprises:
(1) the double-wire bus is a non-polar bus with one master and multiple slaves, half-duplex serial communication and power supply;
(2) the downlink communication from the master station to the slave station adopts a differential voltage pulse width modulation mode, and the uplink communication from the slave station to the master station adopts a current pulse width modulation mode;
(3) the two-wire bus communication frame structure comprises one or more sub-frames, wherein each sub-frame comprises a start bit, N information bits and an end bit, wherein the N information bits are composed of N-1 information bits and a parity bit, and N is a positive integer;
(4) the widths of a start bit and an end bit in a subframe are standard pulse width values, the pulse width of a signal modulated by digital logic '0' is equal to M times of the standard pulse width value, the pulse width of a signal modulated by digital logic '1' is equal to L times of the standard pulse width, L and M are positive numbers, L and M are not equal to 1, and the master station and the slave station are set and agreed in a communication protocol according to application needs;
(5) downlink communication standard pulse width value TdownSetting up the standard pulse width value T of the uplink communication according to application requirementsupFixing;
(6) the method comprises the following steps that a master station broadcasts a downlink standard pulse width communication frame before downlink normal communication, the downlink standard pulse width communication frame only comprises a subframe, and the widths of a start bit, N information bits and an end bit are all equal to a standard pulse width value TdownAll slave stations on the bus receive and detect the value of the downstream standard pulse width TdownCalculating TdownEqual to the arithmetic mean of the pulse widths of the start bit, the end bit and the N information bits;
(7) the slave station detects the communication frame from the master station during the downlink normal communication and bases on the detected downlink standard pulse width value TdownAccurately demodulating digital information for modulation;
(8) the master station keeps the bus differential voltage unchanged during uplink normal communication, namely the voltage difference between the two-wire buses is unchanged, and the master station passes through the sampling resistor on the busesConverting the modulated current of the slave station into voltage, performing correlation processing to obtain a digital signal, and then basing the digital signal on an uplink standard pulse width value TupAnd accurately demodulating the digital information sent by the slave station.
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| CN112737905B (en) * | 2020-12-22 | 2022-05-24 | 青岛鼎信通讯消防安全有限公司 | Method and system for transmitting and receiving parallel two-bus communication |
| CN114459303B (en) * | 2022-01-29 | 2023-03-31 | 南京金阵微电子技术有限公司 | Communication method, medium and electronic detonator communication system |
| CN115833998A (en) * | 2023-02-21 | 2023-03-21 | 江西飞尚科技有限公司 | Two-bus communication coding method and system |
| CN118018356B (en) * | 2024-04-08 | 2024-06-07 | 武汉派呦科技有限公司 | Power supply communication system based on two-bus time-sharing multiplexing |
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