CN109600062A - A kind of control method and full bridge rectifier of full-bridge rectification - Google Patents
A kind of control method and full bridge rectifier of full-bridge rectification Download PDFInfo
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- CN109600062A CN109600062A CN201811595789.4A CN201811595789A CN109600062A CN 109600062 A CN109600062 A CN 109600062A CN 201811595789 A CN201811595789 A CN 201811595789A CN 109600062 A CN109600062 A CN 109600062A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
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Abstract
This application provides a kind of control method of full-bridge rectification and full bridge rectifiers, this method comprises: in the current period of input current, detect the first voltage of the half-bridge metal-oxide half field effect transistor MOSFET drain electrode of full bridge rectifier, it determines that first voltage is greater than pre-set shutdown voltage threshold, turns off half-bridge MOSFET；After turning off half-bridge MOSFET, the second voltage of detection half-bridge MOSFET drain electrode；If detecting, second voltage is less than or equal to pre-set cut-in voltage and compares threshold value, by the pre-set timeslice of turn on time delay of the driving control signal of control of next period half-bridge MOSFET grid, compare threshold value less than or equal to pre-set cut-in voltage if second voltage is not detected, the turn-on time of the driving control signal of the grid of control of next period half-bridge MOSFET is reduced into pre-set timeslice.The functional reliability of full bridge rectifier can be promoted.
Description
Technical field
This application involves commutation technique fields, in particular to the control method and full-bridge rectification of a kind of full-bridge rectification
Circuit.
Background technique
Full bridge rectifier is a kind of common rectification circuit in power management, for being converted to the alternating voltage of input
DC voltage.Fig. 1 is the full bridge rectifier structural schematic diagram of the prior art.As shown in Figure 1, as the input current (I of exchangeAC)
For timing, first diode (D1), third diode (D3) conducting charge for output capacitance (C0) and export DC voltage
(Vout)；As the alternating current (I of inputAC) when being negative, the second diode (D2), the conducting of the 4th diode (D4), for output electricity
Hold (C0) to charge and export DC voltage (Vout).
In practical application, due to diode have certain conducting voltage threshold value, in high current in application, due to
Metal-oxide half field effect transistor (MOSFET, Metal-Oxide-Semiconductor Field-Effect Transistor) tool
There is the conduction impedance of very little, efficiency can be greatlyd improve.Therefore, can use 4 MOSFET replace respectively 4 diodes with
Realize full-bridge rectification, Fig. 2 is another structural schematic diagram of full bridge rectifier of the prior art.As shown in Fig. 2, compared to diode
The conducting of the automatic conducting realized under differential pressure, MOSFET needs to realize by the control voltage of grid, therefore, in order to make 4
The conducting behavior of a MOSFET (being denoted as M1~M4 respectively) and diode-like seemingly, need to be detected the source and drain of MOSFET with comparator
The voltage or current of pole controls the grid voltage of MOSFET, to control the turn-on and turn-off of MOSFET.Wherein, when
When MOSFET generates the electric current from source electrode to drain electrode, the grid voltage that comparator controls MOSFET is height, makes drive control circuit
To the driving control signal of MOSFET output high level, to open MOSFET；And when MOSFET generation is slave source electrode to drain electrode
Electric current reduce and when close to 0, comparator control MOSFET grid voltage be it is low, keep drive control circuit defeated to MOSFET
Low level driving control signal out, to turn off MOSFET.
In full bridge rectifier, due to the symmetry of input current, in Fig. 2, M4 is also necessarily connected when M2 is connected, and M3 is led
M1 is also necessarily connected when logical, and therefore, the comparator of the comparator and control M3 that control M1 can be multiplexed, control M2 comparator and
The comparator of control M4 can also be multiplexed.Certainly, in practical application, M1 and being switched on and off for M3 also can use two differences
Comparator controlled.As shown in figure 3, Fig. 3 is the another structural schematic diagram of full bridge rectifier of the prior art.
The sequential relationship schematic diagram of driving control signal and input voltage and input current that Fig. 4 is MOSFET.Wherein, it drives
Dynamic control signal refers to that the voltage signal of control MOSFET grid, input voltage are the corresponding voltage of input current.
As shown in Figure 3 and Figure 4.The turn-on and turn-off of each MOSFET are controlled in full bridge rectifier to realize full-bridge rectification
Process is as follows:
Under initial situation, the driving control signal (Drv_LD/Drv_RD) of 4 MOSFET be it is low, therefore, 4 MOSFET
It is in off state.Wherein, Drv_RD is the drive voltage signal for controlling M1 and M3 grid, and Drv_LD is control M2 and M4 grid
The drive voltage signal of pole.
As input current (IAC) it is timing, full bridge rectifier is flowed into from ACP, flows out full bridge rectifier, input from ACN
Electric current (IAC) by the substrate diode of M1 and M3, therefore, the drain voltage of M1 and M3 are equal to negative diode drop (- VBE)。
By taking M3 as an example, the first unlatching comparator (Cmp1_ON) threshold compared with preset cut-in voltage by the drain voltage of M3
Value (VTHON) is compared, if detecting, the drain voltage of M3 reaches negative diode drop, that is, detects the drain voltage of M3
When less than or equal to negative diode drop, the Drv_RD=1 that output high level exports drive control circuit to M3, for high electricity
Flat, M3 is turned on, and due to conduction impedance (Rdson) very little of M3, the drain voltage of M3 can be greater than-VBE after M3 is opened.
As input current (IAC) when gradually decreasing to close to 0, the leakage of the first shutdown comparator (Cmp1_OFF) detection M3
Pole tension, the drain voltage for the M3 that will test threshold value (VTHOFF) compared with preset shutdown voltage are compared, wherein are closed
Power-off pressure ratio is greater than cut-in voltage compared with threshold value and compares threshold value, when the drain voltage for detecting M3 is greater than or equal to preset shutdown electricity
When pressure ratio is compared with threshold value, to export the Drv_RD=0 that low level exports drive control circuit to M3, M3 is turned off.
As input current (IAC) when being negative, electric current flows into full bridge rectifier from ACN, flows out full bridge rectifier from ACP.
Second, which opens comparator (Cmp2_ON) and second, turns off the working principle of comparator (Cmp2_OFF) and is positive when input current
When, the first unlatching comparator (Cmp1_ON) is identical with the first shutdown working principle of comparator (Cmp1_OFF).
In the full bridge rectifier, due to the conduction impedance very little of MOSFET, conduction voltage drop is low, so that shutdown voltage
Compare threshold value (VTHOFF) to be generally arranged between -1mV~-10mV, it is therefore desirable to comparator resolution ratio it is higher, for example,
The resolution ratio for needing to reach 0.1mV, especially in high frequency, for example, reaching the higher-frequencies such as 100KHz~1MHz in input current frequency
When, the high resolution of comparator is not required nothing more than, it is also necessary to the fast response time of comparator, but since full bridge rectifier would generally
Biggish electric current, therefore noise vs' being affected compared with device resolution ratio are flowed through, can comparator be judged by accident, to influence
The functional reliability of full bridge rectifier.
Summary of the invention
In view of this, a kind of control method and full bridge rectifier for being designed to provide full-bridge rectification of the application, is used
In solving noise vs' being affected so that the functional reliability of full bridge rectifier is lower compared with device resolution ratio in the prior art
The problem of.
In a first aspect, the embodiment of the present application provides a kind of control method of full-bridge rectification, this method comprises:
In the current period of input current, the half-bridge metal-oxide half field effect transistor MOSFET leakage of full bridge rectifier is detected
The first voltage of pole determines that the first voltage is greater than pre-set shutdown voltage threshold, turns off half-bridge MOSFET；
After turning off the half-bridge MOSFET, the second voltage of the half-bridge MOSFET drain electrode is detected；
If detecting, the second voltage is less than or equal to pre-set cut-in voltage and compares threshold value, and next period is controlled
The pre-set timeslice of turn on time delay for making the driving control signal of the half-bridge MOSFET grid, if institute is not detected
It states second voltage and compares threshold value less than or equal to pre-set cut-in voltage, next period is controlled the half-bridge MOSFET's
The turn-on time of the driving control signal of grid reduces pre-set timeslice.
Optionally, from control half-bridge MOSFET drain current period low level to overturning to high level rising edge it
Between period in, detect the second voltage of half-bridge MOSFET drain electrode；By the driving control for controlling half-bridge MOSFET grid
The failing edge of signal processed carries out the delay or reduction of the timeslice.
Second aspect, the embodiment of the present application provide a kind of full bridge rectifier, comprising: the first metal-oxide half field effect transistor
MOSFET, the 2nd MOSFET, the 3rd MOSFET, the 4th MOSFET, first comparator, the second comparator, the first driving voltage control
Device, the second drive voltage controller, the first delayer and the second delayer processed, wherein
The anode of the source electrode access input voltage of first MOSFET, drain electrode are connected with the anode of output voltage, grid and the
The output end of one delayer is connected；
The source electrode of 2nd MOSFET is connected with the cathode of output voltage, the anode of drain electrode access input voltage, grid and the
The output end of two delayers is connected；
The source electrode of 3rd MOSFET is connected with the cathode of output voltage, the cathode of drain electrode access input voltage, grid and the
The output end of one delayer is connected；
The source electrode of 4th MOSFET is connected with the cathode of input voltage, the anode of drain electrode access output voltage, grid and the
The output end of two delayers is connected；
The non-inverting input terminal of first comparator is connected with the drain electrode of the 3rd MOSFET, inverting input terminal access shutdown voltage threshold
Value or cut-in voltage compare threshold value, and output end is connected with the input terminal of the first drive voltage controller；
The first input end of first delayer is connected with the output end of the first drive voltage controller, the second input terminal and
The output end of one comparator is connected；
The non-inverting input terminal of second comparator is connected with the drain electrode of the 2nd MOSFET, inverting input terminal access shutdown voltage threshold
Value or cut-in voltage compare threshold value, and output end is connected with the input terminal of the second drive voltage controller；
The first input end of second delayer is connected with the output end of the second drive voltage controller, the second input terminal and
The output end of two comparators is connected.
Optionally, first delayer includes: delay judging circuit and configurable delay circuit, wherein
Delay judging circuit, the driving control signal of first input end access the first drive voltage controller output, second
Input terminal is connected with the output end for opening first comparator, and output end is connected with the input terminal of configurable delay circuit；
Configurable delay circuit, first input end access the driving control signal of the first drive voltage controller output, the
Two input terminals are connected with the output end of delay judging circuit, and output end is connected with the grid of the 3rd MOSFET.
Optionally, the delay judging circuit includes: sampling module, accumulator and register, wherein
Sampling module, for the second voltage of the 3rd MOSFET drain electrode being detected, if detecting after turning off the 3rd MOSFET
The second voltage is less than or equal to pre-set cut-in voltage and compares threshold value, exports to accumulator and extends timeslice instruction,
Compare threshold value less than or equal to pre-set cut-in voltage if the second voltage is not detected, when exporting reduction to accumulator
Between piece instruct；
Accumulator, the conducting for the output according to sampling module, to including in the driving control signal in current period
Time carries out extending timeslice or reduces the operation of timeslice；
Register obtains the driving control signal in next period for refreshing the calculated result of accumulator.
Optionally, the sampling module includes: that the first phase inverter, the first d type flip flop, the second d type flip flop and delay are single
Member, wherein
The input terminal of first phase inverter accesses driving control signal, output end respectively with the end D of the first d type flip flop and prolong
The input terminal of slow unit is connected；
The CP of first d type flip flop terminates the event instruction that threshold value is compared compared with cut-in voltage into second voltage
Signal, R are terminated into driving voltage, and the end Q is connected with the end D of the second d type flip flop；
The output end of delay cell is connected with the end CP of the second d type flip flop；
The end Q of second d type flip flop is connected with the end P of accumulator.
Optionally, the register includes: third d type flip flop, four d flip-flop, the 5th d type flip flop, the 6th D triggering
Device, the 7th d type flip flop, the 8th d type flip flop, the 9th d type flip flop and the tenth d type flip flop, wherein
Third d type flip flop, four d flip-flop, the 5th d type flip flop, the 6th d type flip flop, the 7th d type flip flop, the 8th D triggering
The end CP of device, the 9th d type flip flop and the tenth d type flip flop is respectively connected to driving control signal, and the end D is connected with accumulator respectively.
Optionally, the configurable delay circuit includes: the second phase inverter, third phase inverter, the 4th phase inverter, first
Metal-oxide-semiconductor, the second metal-oxide-semiconductor, third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor,
9th metal-oxide-semiconductor, first capacitor, the second capacitor, third capacitor, the 4th capacitor, the 5th capacitor, the 6th capacitor, the 7th capacitor and
8th capacitor, wherein
The input terminal of second phase inverter accesses driving control signal, and output end is connected with the input terminal of third phase inverter；
The output end of third phase inverter is connected with the grid of the first metal-oxide-semiconductor；
The drain electrode of first metal-oxide-semiconductor respectively with the second metal-oxide-semiconductor, third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th MOS
The drain electrode of pipe, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor is connected, source electrode respectively with first capacitor, the second capacitor, the
Three capacitors, the 4th capacitor, the 5th capacitor, the 6th capacitor, the 7th capacitor and the 8th capacitor one end be connected；
Second metal-oxide-semiconductor, third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor
And the 9th the grid of metal-oxide-semiconductor be respectively connected to the first signal, second signal, third signal, fourth signal, the 5th signal, the 6th
Signal, the 7th signal, the 8th signal；
Second metal-oxide-semiconductor, third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor
And the 9th metal-oxide-semiconductor source electrode successively with first capacitor, the second capacitor, third capacitor, the 4th capacitor, the 5th capacitor, the 6th electricity
The other end of appearance, the 7th capacitor and the 8th capacitor is connected；
First capacitor, the second capacitor, third capacitor, the 4th capacitor, the 5th capacitor, the 6th capacitor, the 7th capacitor and
The capacitance of eight capacitors is incremented by multiple；
The input terminal of 4th phase inverter is connected with the drain electrode of the 9th metal-oxide-semiconductor and preset current source, output end and third
The grid of MOSFET is connected.
Optionally, the first comparator, in the current period of input current, the 3rd MOSFET of detection to drain
First voltage determines that the first voltage is greater than pre-set shutdown voltage threshold, exports to the first drive voltage controller
First instruction；
First drive voltage controller is generated for receiving the first instruction for controlling the first MOSFET and third
The driving control signal of MOSFET, output to the first delayer；
First delayer, for detecting the second voltage of the 3rd MOSFET drain electrode after turning off the 3rd MOSFET, if detection
It is less than or equal to pre-set cut-in voltage to the second voltage and compares threshold value, to the output of the first drive voltage controller
The pre-set timeslice of the turn on time delay for including in driving control signal, if be not detected the second voltage be less than or
Compare threshold value equal to pre-set cut-in voltage, includes in the driving control signal exported to the first drive voltage controller
Turn-on time reduces pre-set timeslice.
Optionally, the first comparator includes: shutdown first comparator and unlatching first comparator, wherein
First comparator is turned off, non-inverting input terminal is connected with the drain electrode of the 3rd MOSFET, inverting input terminal access shutdown electricity
Threshold value is pressed, output end is connected with the input terminal of the first drive voltage controller；
First comparator is opened, non-inverting input terminal access cut-in voltage compares threshold value, inverting input terminal and the 3rd MOSFET
Drain electrode be connected, output end is connected with the input terminal of the input terminal of the first drive voltage controller and the first delayer respectively.
The control method and full bridge rectifier of a kind of full-bridge rectification provided by the embodiments of the present application, in working as input current
In the preceding period, detect full bridge rectifier half-bridge metal-oxide half field effect transistor MOSFET drain electrode first voltage, determine described in
First voltage is greater than pre-set shutdown voltage threshold, turns off half-bridge MOSFET；After turning off the half-bridge MOSFET, detection
The second voltage of the half-bridge MOSFET drain electrode；If detecting, the second voltage is less than or equal to pre-set cut-in voltage
Compare threshold value, the turn on time delay that next period controls the driving control signal of the half-bridge MOSFET grid is preset
Timeslice, compare threshold value less than or equal to pre-set cut-in voltage if the second voltage is not detected, by next week
The turn-on time that phase controls the driving control signal of the grid of the half-bridge MOSFET reduces pre-set timeslice.In this way,
It is less than shutdown voltage by setting shutdown voltage threshold and compares threshold value, the resolution to comparator in full bridge rectifier can be made
Rate requires to reduce, and reduces influence of the noise jamming to comparator, meanwhile, by the second voltage of detection half-bridge MOSFET drain electrode with
Cut-in voltage compares threshold value, carries out Adaptive Control to the turn-on time of driving control signal, can ensure full bridge rectifier
Normal operation, to effectively improve the functional reliability of full bridge rectifier.
To enable the above objects, features, and advantages of the application to be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate
Appended attached drawing, is described in detail below.
Detailed description of the invention
Technical solution in ord to more clearly illustrate embodiments of the present application, below will be to needed in the embodiment attached
Figure is briefly described, it should be understood that the following drawings illustrates only some embodiments of the application, therefore is not construed as pair
The restriction of range for those of ordinary skill in the art without creative efforts, can also be according to this
A little attached drawings obtain other relevant attached drawings.
Fig. 1 is the full bridge rectifier structural schematic diagram of the prior art；
Fig. 2 is another structural schematic diagram of full bridge rectifier of the prior art；
Fig. 3 is the another structural schematic diagram of full bridge rectifier of the prior art；
The sequential relationship schematic diagram of driving control signal and input voltage and input current that Fig. 4 is MOSFET；
Fig. 5 is the control method flow diagram of full-bridge rectification provided by the embodiments of the present application；
The driving control signal and input voltage and input current that Fig. 6 is control MOSFET provided by the embodiments of the present application
Sequential relationship schematic diagram；
Fig. 7 is full bridge rectifier structural schematic diagram provided by the embodiments of the present application；
Fig. 8 is the first retarder arrangement schematic diagram provided by the embodiments of the present application；
Fig. 9 is delay judging circuit structural schematic diagram provided by the embodiments of the present application；
Figure 10 is configurable delay electrical block diagram provided by the embodiments of the present application.
Specific embodiment
To keep the purposes, technical schemes and advantages of the embodiment of the present application clearer, below in conjunction with the embodiment of the present application
Middle attached drawing, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described embodiment is only
It is some embodiments of the present application, instead of all the embodiments.The application being usually described and illustrated herein in the accompanying drawings is real
The component for applying example can be arranged and be designed with a variety of different configurations.Therefore, below to the application's provided in the accompanying drawings
The detailed description of embodiment is not intended to limit claimed scope of the present application, but is merely representative of the selected reality of the application
Apply example.Based on embodiments herein, those skilled in the art institute obtained without making creative work
There are other embodiments, shall fall in the protection scope of this application.
Fig. 5 is the control method flow diagram of full-bridge rectification provided by the embodiments of the present application.As shown in figure 5, being applied to
Full bridge rectifier, this method comprises:
Step 501, in the current period of input current, the first of the half-bridge MOSFET drain electrode of full bridge rectifier is detected
Voltage determines that the first voltage is greater than pre-set shutdown voltage threshold, turns off the half-bridge MOSFET；
In the embodiment of the present application, the current period of input current includes a positive half period and a negative half-cycle, input electricity
The period of stream is consistent with the period that control half-bridge MOSFET is switched off and on.As an alternative embodiment, full bridge rectifier
Including upper half-bridge MOSFET and lower half-bridge MOSFET.Wherein it is possible to be the upper half-bridge MOSFET conducting in positive half period, lower half
Bridge MOSFET shutdown, and in negative half-cycle, upper half-bridge MOSFET shutdown, lower half-bridge MOSFET conducting, alternatively, in positive half period
It is interior, lower half-bridge MOSFET conducting, upper half-bridge MOSFET shutdown, and in negative half-cycle, lower half-bridge MOSFET shutdown, upper half-bridge
MOSFET conducting.
In the embodiment of the present application, as an alternative embodiment, upper half-bridge MOSFET includes two MOSFET, for example, in Fig. 2
M1 and M3, lower half-bridge MOSFET also includes two MOSFET, for example, M2 and M4 in Fig. 2.
In the embodiment of the present application, as an alternative embodiment, due to the control of two MOSFET in upper half-bridge MOSFET
Mode is identical, and the control mode of two MOSFET in lower half-bridge MOSFET is also identical, thus, half-bridge MOSFET can be upper half
Any MOSFET in bridge MOSFET or lower half-bridge MOSFET.
In the embodiment of the present application, the shutdown voltage that shutdown voltage threshold is less than in Fig. 2 compares threshold value, due to turning off voltage ratio
It is negative value compared with threshold value, thus, shutdown voltage is less than by setting shutdown voltage threshold and compares threshold value, can be made to full-bridge rectification
The resolution requirement of comparator reduces in circuit, such as, it is only necessary to reach the resolution ratio of 0.3mV, so as to effectively subtract
Few noise vs reduce the probability that comparator is judged by accident, can ensure the work of full bridge rectifier compared with the influence of device resolution ratio
Make reliability.
In the embodiment of the present application, setting shutdown voltage threshold is less than shutdown voltage and compares threshold value, relative to existing full-bridge
Rectification circuit is equivalent to and shifts to an earlier date or postpone shutdown half-bridge MOSFET, thus, if desired keep each of existing full bridge rectifier
The switching time of MOSFET needs the driving control signal (turn-on and turn-off time) to control MOSFET to carry out adaptive
It should adjust.
Step 502, after turning off the half-bridge MOSFET, the second voltage of the half-bridge MOSFET drain electrode is detected；
In the embodiment of the present application, as an alternative embodiment, after turning off half-bridge MOSFET, detection half-bridge MOSFET drain electrode
Second voltage period be from control half-bridge MOSFET drain current period low level to overturning to high level rise
Period between.
Step 503, if detect the second voltage be less than or equal to pre-set cut-in voltage compare threshold value, will under
One period controlled the pre-set timeslice of turn on time delay of the driving control signal of the half-bridge MOSFET grid, if not
It detects that the second voltage is less than or equal to pre-set cut-in voltage and compares threshold value, next period is controlled into the half-bridge
The turn-on time of the driving control signal of the grid of MOSFET reduces pre-set timeslice.
In the embodiment of the present application, the driving control signal of half-bridge MOSFET grid is controlled, for example, for M1 and M3, the drive
Dynamic control signal is Drv_RD；For M2 and M4, which is Drv_LD.As an alternative embodiment, electricity is opened
The threshold value compared with the cut-in voltage in Fig. 2 is identical compared with threshold value for pressure ratio.
In the embodiment of the present application, the second voltage for the half-bridge MOSFET drain electrode that will test is compared with preset cut-in voltage
Threshold value is compared, and when detecting that second voltage compares threshold value no more than cut-in voltage, demonstrating the need for output high level makes this
Half-bridge MOSFET conducting.As an alternative embodiment, voltage threshold is turned off greater than cut-in voltage and compares threshold value.
In the embodiment of the present application, the delay of timeslice can be carried out to turn-on time by delay circuit, that is, when increasing conducting
Between；Alternatively, carrying out the reduction of timeslice to turn-on time.As an alternative embodiment, timeslice be a least significant bit (LSB,
Least Significant Bit) corresponding time.
In the embodiment of the present application, as an alternative embodiment, by the driving control signal for controlling half-bridge MOSFET grid
Failing edge carry out timeslice delay or reduction, i.e., the failing edge of Drv_LD and Drv_RD are delayed respectively.
In the embodiment of the present application, by taking M2, M3 in Fig. 2 as an example, after turning off M2 or M3, if the drain voltage of M2 or M3 is again
It is secondary to fall to VTHON, illustrate input current IACThere are no zero passages, cause the substrate diode of M2 or M3 to be connected, then when will postpone
Between increase by a LSB；If the drain voltage of M2 or M3 does not drop to VTHON, illustrate input current IACPolarity turned over
Turn, then the delay time is reduced into a LSB.Finally, which will reach a dynamic equilibrium point, thus dry in noise
In the case of disturbing, it can ensure the resolution ratio of comparator, comparator is avoided to judge by accident, and pass through detection half-bridge MOSFET drain electrode
Second voltage compared with cut-in voltage threshold value, Adaptive Control is carried out to the turn-on time of driving control signal, can be ensured
The normal operation of full bridge rectifier, the two combine, and effectively improve the functional reliability of full bridge rectifier.
The driving control signal and input voltage and input current that Fig. 6 is control MOSFET provided by the embodiments of the present application
Sequential relationship schematic diagram.In the embodiment of the present application, for example, by taking M2 in Fig. 2 as an example, in n-th of period of input current,
The first voltage for detecting M2 drain electrode determines that first voltage is greater than shutdown voltage threshold, and output signal OFF2 turns off M2；In shutdown M2
Afterwards, the voltage of M2 drain electrode is detected again, it is defeated if detecting that the second voltage of M2 drain electrode is less than or equal to VTHON
Signal ON2 out, on the basis of controlling driving control signal (Drv_LD) current period turn-on time of M2 grid, when by being connected
Between increase a LSB (correspondingly, turn-off time reduce a LSB), obtain next period, i.e. (n+1)th period control M2 grid
Driving control signal (Drv_LD_td)；If detecting that the second voltage of M2 drain electrode is greater than VTHON, in control M2 grid
On the basis of driving control signal current period turn-on time, turn-on time is reduced into a LSB, obtains next period control M2 grid
The driving control signal of pole.
In (n+1)th period of input current, according to next period control M2 grid driving control signal to M2 into
Row control, according to processing mode same as described above, determines the driving control of the n-th+2 period control M2 grids after turning off M2
Signal processed.
Fig. 7 is full bridge rectifier structural schematic diagram provided by the embodiments of the present application.As shown in fig. 7, the full-bridge rectification is electric
Road includes: the first MOSFET70 (M1), the 2nd MOSFET71 (M2), the 3rd MOSFET72 (M3), the 4th MOSFET73 (M4),
One comparator 74, the second comparator 75, the first drive voltage controller 76, the second drive voltage controller 77, the first delayer
78 and second delayer 79, wherein
First MOSFET70 source electrode access input voltage anode, drain electrode be connected with the anode of output voltage, grid and
The output end of first delayer 78 is connected；
The source electrode of 2nd MOSFET71 is connected with the cathode of output voltage, drain electrode access input voltage anode, grid with
The output end of second delayer 79 is connected；
The source electrode of 3rd MOSFET72 is connected with the cathode of output voltage, drain electrode access input voltage cathode, grid with
The output end of first delayer 78 is connected；
The source electrode of 4th MOSFET73 is connected with the cathode of input voltage, drain electrode access output voltage anode, grid with
The output end of second delayer 79 is connected；
The non-inverting input terminal of first comparator 74 is connected with the drain electrode of the 3rd MOSFET72, inverting input terminal access shutdown electricity
Pressure threshold value or cut-in voltage compare threshold value, and output end is connected with the input terminal of the first drive voltage controller 76；
The first input end of first delayer 78 is connected with the output end of the first drive voltage controller 76, the second input terminal
It is connected with the output end of first comparator 74；
The non-inverting input terminal of second comparator 75 is connected with the drain electrode of the 2nd MOSFET71, inverting input terminal access shutdown electricity
Pressure threshold value or cut-in voltage compare threshold value, and output end is connected with the input terminal of the second drive voltage controller 77；
The first input end of second delayer 79 is connected with the output end of the second drive voltage controller 77, the second input terminal
It is connected with the output end of the second comparator 75.
In the embodiment of the present application, first comparator, in the current period of input current, the 3rd MOSFET of detection to leak
The first voltage of pole determines that the first voltage is greater than pre-set shutdown voltage threshold, to the first drive voltage controller
The first instruction of output；
First drive voltage controller is generated for receiving the first instruction for controlling the first MOSFET and third
The driving control signal (Drv_RD) of MOSFET, output to the first delayer；
First delayer, for detecting the second voltage of the 3rd MOSFET drain electrode after turning off the 3rd MOSFET, if detection
It is less than or equal to pre-set cut-in voltage to the second voltage and compares threshold value, to the output of the first drive voltage controller
The pre-set timeslice of the turn on time delay for including in driving control signal obtains the drive control of the 3rd MOSFET of control
Signal (Drv_RD_td) compares threshold value less than or equal to pre-set cut-in voltage if the second voltage is not detected, right
The turn-on time for including in the driving control signal of first drive voltage controller output reduces pre-set timeslice, obtains
Control the driving control signal (Drv_RD_td) of the 3rd MOSFET.
In the embodiment of the present application, as another alternative embodiment, the 3rd MOSFET can also turned off by first comparator
Afterwards, the second voltage of the 3rd MOSFET of detection drain electrode, if detecting, the second voltage is less than or equal to pre-set unlatching
Voltage compares threshold value, exports to the first delayer and extends timeslice instruction, is less than or equal to if the second voltage is not detected
Pre-set cut-in voltage compares threshold value, exports to the first delayer and reduces timeslice instruction；First delayer is according to reception
Extension timeslice instruction or reduce timeslice instruction carry out respective handling.
In the embodiment of the present application, the second comparator, in the current period of input current, the 2nd MOSFET of detection to leak
The first voltage of pole determines that the first voltage is greater than pre-set shutdown voltage threshold, to the second drive voltage controller
The first instruction of output；
Second drive voltage controller is generated for receiving the first instruction for controlling the 2nd MOSFET and the 4th
The driving control signal of MOSFET, output to the second delayer；
Second delayer, for detecting the second voltage of the 2nd MOSFET drain electrode after turning off the 2nd MOSFET, if detection
It is less than or equal to pre-set cut-in voltage to the second voltage and compares threshold value, to the output of the second drive voltage controller
The pre-set timeslice of the turn on time delay for including in driving control signal, if be not detected the second voltage be less than or
Compare threshold value equal to pre-set cut-in voltage, includes in the driving control signal exported to the second drive voltage controller
Turn-on time reduces pre-set timeslice.
In the embodiment of the present application, by increasing by one self-adjustable first on the basis of original full bridge rectifier
Delayer and the second delayer enable the comparator for controlling MOSFET to reach high-precision, quick response and high RST simultaneously and make an uproar
Sound inhibits ratio.
In the embodiment of the present application, as an alternative embodiment, the quantity of first comparator and the second comparator is respectively
2.Specifically,
First comparator 74 includes: to open first comparator 741 and shutdown first comparator 742, wherein
First comparator 742 is turned off, non-inverting input terminal is connected with the drain electrode of the 3rd MOSFET, inverting input terminal access shutdown
Voltage threshold, output end are connected with the input terminal of the first drive voltage controller；
First comparator 741 is opened, non-inverting input terminal access cut-in voltage compares threshold value, inverting input terminal and third
The drain electrode of MOSFET is connected, the output end input terminal with the input terminal of the first drive voltage controller and the first delayer respectively
It is connected.
Second comparator 75 includes: to open the second comparator 752 of the second comparator 751 and shutdown, wherein
The second comparator 752 is turned off, non-inverting input terminal is connected with the drain electrode of the 2nd MOSFET, inverting input terminal access shutdown
Voltage threshold, output end are connected with the input terminal of the second drive voltage controller；
The second comparator 751 is opened, non-inverting input terminal access cut-in voltage compares threshold value, inverting input terminal and second
The drain electrode of MOSFET is connected, the output end input terminal with the input terminal of the second drive voltage controller and the second delayer respectively
It is connected.
Fig. 8 is the first retarder arrangement schematic diagram provided by the embodiments of the present application.As shown in figure 8, in the embodiment of the present application,
As an alternative embodiment, the first delayer includes: delay judging circuit 81 and configurable delay circuit 82, wherein
Delay judging circuit 81, first input end access the driving control signal of the first drive voltage controller output, the
Two input terminals are connected with the output end for opening first comparator, and output end is connected with the input terminal of configurable delay circuit 82；
Configurable delay circuit 82, first input end access the driving control signal of the first drive voltage controller output,
Second input terminal is connected with the output end of delay judging circuit 81, and output end is connected with the grid of the 3rd MOSFET.
Fig. 9 is delay judging circuit structural schematic diagram provided by the embodiments of the present application.As shown in figure 9, the embodiment of the present application
In, as an alternative embodiment, delay judging circuit includes: sampling module, accumulator and register, wherein
Sampling module, for the second voltage of the 3rd MOSFET drain electrode being detected, if detecting after turning off the 3rd MOSFET
The second voltage is less than or equal to pre-set cut-in voltage and compares threshold value, exports to accumulator and extends timeslice instruction,
Compare threshold value less than or equal to pre-set cut-in voltage if the second voltage is not detected, when exporting reduction to accumulator
Between piece instruct；
In the embodiment of the present application, sampling module detects whether the event of ON1=1, i.e., after Drv_LD_td=0
Second voltage is less than or equal to the event generation that pre-set cut-in voltage compares threshold value；If so, then exporting Polary=
1, instruction increases by a LSB；If it is not, output Polary=0, instruction reduce by a LSB.
In the embodiment of the present application, as an alternative embodiment, sampling module can also be according to the driving control signal of M2, M4
As control sequential signal.
Accumulator, the conducting for the output according to sampling module, to including in the driving control signal in current period
Time carries out extending timeslice or reduces the operation of timeslice；
In the embodiment of the present application, accumulator carries out one to the driving control signal in current period, i.e. driving control signal
The secondary operation for adding one or subtracting one.
In the embodiment of the present application, as an alternative embodiment, accumulator can be according to concrete application situation, for example, full-bridge
The factors such as speed, precision, the efficiency of rectification circuit increased or decrease the digit regulated and controled.It is carried out according to driving control signal
Plus one or the operation that subtracts one, for example, driving control signal may include 8 drive control subsignals for 8 bit accumulators, note
Are as follows: BRGCal<0:7>.
Register obtains the driving control signal in next period for refreshing the calculated result of accumulator.
In the embodiment of the present application, as an alternative embodiment, refresh accumulator in the rising edge of next period DRV_LD_td
Calculated result, as next cycle td control signal foundation.
In the embodiment of the present application, the control circuits such as the reading to BRGCal<0:7>, write-in, pause can also be increased.
In the embodiment of the present application, as an alternative embodiment, register includes but is not limited to: d type flip flop, rest-set flip-flop,
JK flip-flop etc..
In the embodiment of the present application, as an alternative embodiment, sampling module includes: the first phase inverter 911, the first D triggering
Device 912, the second d type flip flop 913 and delay cell 914, wherein
The input terminal of first phase inverter 911 accesses driving control signal, the output end end D with the first d type flip flop 912 respectively
And the input terminal of delay cell is connected；
The CP of first d type flip flop 912 terminates the event that threshold value is compared compared with cut-in voltage into second voltage
Indication signal, R are terminated into driving voltage, and the end Q is connected with the end D of the second d type flip flop 913；
The output end of delay cell 914 is connected with the end CP of the second d type flip flop 913；
The end Q of second d type flip flop 913 is connected with the end P of accumulator.
In the embodiment of the present application, if second voltage is less than or equal to the event hair that pre-set cut-in voltage compares threshold value
Raw, the event indication signal that second voltage threshold value compared with cut-in voltage is compared is high level.The end P of accumulator is
Polary pin, the input terminal as accumulator.As an alternative embodiment, another input terminal of accumulator and register
Output end is connected.
In the embodiment of the present application, as an alternative embodiment, register includes: third d type flip flop 930, four d flip-flop
931,932 (not shown) of the 5th d type flip flop, 933 (not shown) of the 6th d type flip flop, the 7th d type flip flop 934 are (in figure
Be not shown), 935 (not shown) of the 8th d type flip flop, 936 (not shown) of the 9th d type flip flop and the tenth d type flip flop
937, wherein
Third d type flip flop, four d flip-flop, the 5th d type flip flop, the 6th d type flip flop, the 7th d type flip flop, the 8th D triggering
The end CP of device, the 9th d type flip flop and the tenth d type flip flop is respectively connected to driving control signal, and the end D is connected with accumulator respectively.
In the embodiment of the present application, the D of third d type flip flop terminates the first signal (BRGCal<0>) into accumulator output, the
The D of four d flip-flop terminates the second signal (BRGCal<1>) into accumulator output, and the D of the 5th d type flip flop is terminated into accumulator
The third signal (BRGCal<2>) of output, the D of the 6th d type flip flop terminate fourth signal (BRGCal<3 into accumulator output
>), the D of the 7th d type flip flop terminates the 5th signal (BRGCal<4>) into accumulator output, and the D of the 8th d type flip flop is terminated into tired
The 6th signal (BRGCal<5>) for adding device to export, the D of the 9th d type flip flop terminate the 7th signal (BRGCal into accumulator output
<6>), the D of the tenth d type flip flop terminates the 8th signal (BRGCal<7>) into accumulator output, and driving control signal includes first
Signal is to the 8th signal.
Figure 10 is configurable delay electrical block diagram provided by the embodiments of the present application.As shown in Figure 10, the application is real
It applies in example, as an alternative embodiment, configurable delay circuit includes: the second phase inverter 1011, third phase inverter the 1012, the 4th
Phase inverter 1013, the first metal-oxide-semiconductor 1014, the second metal-oxide-semiconductor 1015, third metal-oxide-semiconductor 1016, the 4th metal-oxide-semiconductor 1017, the 5th metal-oxide-semiconductor
1018, the 6th metal-oxide-semiconductor 1019, the 7th metal-oxide-semiconductor 1020, the 8th metal-oxide-semiconductor 1021, the 9th metal-oxide-semiconductor 1022, first capacitor 1023,
Two capacitors 1024, third capacitor 1025, the 4th capacitor 1026, the 5th capacitor 1027, the 6th capacitor 1028, the 7th capacitor 1029 with
And the 8th capacitor 1030, wherein
The input terminal of second phase inverter accesses driving control signal, and output end is connected with the input terminal of third phase inverter；
The output end of third phase inverter is connected with the grid of the first metal-oxide-semiconductor；
The drain electrode of first metal-oxide-semiconductor respectively with the second metal-oxide-semiconductor, third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th MOS
The drain electrode of pipe, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor is connected, source electrode respectively with first capacitor, the second capacitor, the
Three capacitors, the 4th capacitor, the 5th capacitor, the 6th capacitor, the 7th capacitor and the 8th capacitor one end be connected；
Second metal-oxide-semiconductor, third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor
And the 9th the grid of metal-oxide-semiconductor be respectively connected to the first signal, second signal, third signal, fourth signal, the 5th signal, the 6th
Signal, the 7th signal, the 8th signal；
Second metal-oxide-semiconductor, third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor
And the 9th metal-oxide-semiconductor source electrode successively with first capacitor, the second capacitor, third capacitor, the 4th capacitor, the 5th capacitor, the 6th electricity
The other end of appearance, the 7th capacitor and the 8th capacitor is connected；
First capacitor, the second capacitor, third capacitor, the 4th capacitor, the 5th capacitor, the 6th capacitor, the 7th capacitor and
The capacitance of eight capacitors is incremented by multiple；
The input terminal of 4th phase inverter is connected with the drain electrode of the 9th metal-oxide-semiconductor and preset current source 1031, output end with
The grid of 3rd MOSFET is connected.
In the embodiment of the present application, configurable delay circuit is only to driving voltage, for example, the failing edge generation of DRV_LD is prolonged
Late, rising edge does not generate delay, and capacitor array (the second capacitor to the 9th capacitor) forms size not according to the value of BRGCal<0:7>
Same capacitance generates configurable failing edge delay time with current source.As an alternative embodiment, first capacitor, second
Capacitor, third capacitor, the 4th capacitor, the 5th capacitor, the 6th capacitor, the 7th capacitor and the 8th capacitor capacitance passed in multiple
Increasing refers to that the capacitance of latter capacitor is twice of the capacitance of previous capacitor.
In the embodiment of the present application, as an alternative embodiment, it is configurable capacitor that configurable delay circuit, which is not limited to electric current,
The structure of array charging, being also possible to resistance is that configurable capacitor array charges, configurable current array is that capacitor charging etc. is each
Kind permutation and combination.
In the embodiment of the present application, as an alternative embodiment, the coding mode of capacitor array is not limited to 8421 codings, can also
To be thermometer code etc..
In the embodiment of the present application, as an alternative embodiment, the second phase inverter to the 4th phase inverter can also be by comparator
Replace.
In embodiment provided herein, it should be understood that disclosed device and method, it can be by others side
Formula is realized.The apparatus embodiments described above are merely exemplary, for example, the division of the unit, only one kind are patrolled
Function division is collected, there may be another division manner in actual implementation, in another example, multiple units or components can combine or can
To be integrated into another system, or some features can be ignored or not executed.Another point, shown or discussed is mutual
Coupling, direct-coupling or communication connection can be INDIRECT COUPLING or communication link by some communication interfaces, device or unit
It connects, can be electrical property, mechanical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme
's.
In addition, each functional unit in embodiment provided by the present application can integrate in one processing unit, it can also
To be that each unit physically exists alone, can also be integrated in one unit with two or more units.
It, can be with if the function is realized in the form of SFU software functional unit and when sold or used as an independent product
It is stored in a computer readable storage medium.Based on this understanding, the technical solution of the application is substantially in other words
The part of the part that contributes to existing technology or the technical solution can be embodied in the form of software products, the meter
Calculation machine software product is stored in a storage medium, including some instructions are used so that a computer equipment (can be a
People's computer, server or network equipment etc.) execute each embodiment the method for the application all or part of the steps.
And storage medium above-mentioned includes: that USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), arbitrary access are deposited
The various media that can store program code such as reservoir (RAM, Random Access Memory), magnetic or disk.
It should also be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, does not then need that it is further defined and explained in subsequent attached drawing, in addition, term " the
One ", " second ", " third " etc. are only used for distinguishing description, are not understood to indicate or imply relative importance.
Finally, it should be noted that embodiment described above, the only specific embodiment of the application, to illustrate the application
Technical solution, rather than its limitations, the protection scope of the application is not limited thereto, although with reference to the foregoing embodiments to this Shen
It please be described in detail, those skilled in the art should understand that: anyone skilled in the art
Within the technical scope of the present application, it can still modify to technical solution documented by previous embodiment or can be light
It is readily conceivable that variation or equivalent replacement of some of the technical features；And these modifications, variation or replacement, do not make
The essence of corresponding technical solution is detached from the spirit and scope of the embodiment of the present application technical solution.The protection in the application should all be covered
Within the scope of.Therefore, the protection scope of the application shall be subject to the protection scope of the claim.
Claims (10)
1. a kind of control method of full-bridge rectification, which is characterized in that this method comprises:
In the current period of input current, the half-bridge metal-oxide half field effect transistor MOSFET drain electrode of full bridge rectifier is detected
First voltage determines that the first voltage is greater than pre-set shutdown voltage threshold, turns off half-bridge MOSFET；
After turning off the half-bridge MOSFET, the second voltage of the half-bridge MOSFET drain electrode is detected；
If detecting, the second voltage is less than or equal to pre-set cut-in voltage and compares threshold value, and next period is controlled institute
The pre-set timeslice of turn on time delay of the driving control signal of half-bridge MOSFET grid is stated, if being not detected described
Two voltages are less than or equal to pre-set cut-in voltage and compare threshold value, and next period is controlled to the grid of the half-bridge MOSFET
The turn-on time of driving control signal reduce pre-set timeslice.
2. the method as described in claim 1, which is characterized in that in the low electricity of the current period to drain from control half-bridge MOSFET
In putting down to overturning to the period between high level rising edge, the second voltage of the half-bridge MOSFET drain electrode is detected；Pass through control
The failing edge of the driving control signal of half-bridge MOSFET grid processed carries out the delay or reduction of the timeslice.
3. a kind of full bridge rectifier, which is characterized in that the full bridge rectifier includes: the first metal-oxide half field effect transistor
MOSFET, the 2nd MOSFET, the 3rd MOSFET, the 4th MOSFET, first comparator, the second comparator, the first driving voltage control
Device, the second drive voltage controller, the first delayer and the second delayer processed, wherein
The anode of the source electrode access input voltage of first MOSFET, drain electrode are connected with the anode of output voltage, and grid prolongs with first
The output end of slow device is connected；
The source electrode of 2nd MOSFET is connected with the cathode of output voltage, and the anode of drain electrode access input voltage, grid prolongs with second
The output end of slow device is connected；
The source electrode of 3rd MOSFET is connected with the cathode of output voltage, and the cathode of drain electrode access input voltage, grid prolongs with first
The output end of slow device is connected；
The source electrode of 4th MOSFET is connected with the cathode of input voltage, and the anode of drain electrode access output voltage, grid prolongs with second
The output end of slow device is connected；
The non-inverting input terminal of first comparator is connected with the drain electrode of the 3rd MOSFET, inverting input terminal access shutdown voltage threshold or
Cut-in voltage compares threshold value, and output end is connected with the input terminal of the first drive voltage controller；
The first input end of first delayer is connected with the output end of the first drive voltage controller, the second input terminal and the first ratio
Output end compared with device is connected；
The non-inverting input terminal of second comparator is connected with the drain electrode of the 2nd MOSFET, inverting input terminal access shutdown voltage threshold or
Cut-in voltage compares threshold value, and output end is connected with the input terminal of the second drive voltage controller；
The first input end of second delayer is connected with the output end of the second drive voltage controller, the second input terminal and the second ratio
Output end compared with device is connected.
4. full bridge rectifier as claimed in claim 3, which is characterized in that first delayer includes: delay judgement electricity
Road and configurable delay circuit, wherein
Delay judging circuit, first input end access the driving control signal of the first drive voltage controller output, the second input
It holds and is connected with the output end for opening first comparator, output end is connected with the input terminal of configurable delay circuit；
Configurable delay circuit, first input end access the driving control signal of the first drive voltage controller output, and second is defeated
Enter end to be connected with the output end of delay judging circuit, output end is connected with the grid of the 3rd MOSFET.
5. full bridge rectifier as claimed in claim 4, which is characterized in that the delay judging circuit include: sampling module,
Accumulator and register, wherein
Sampling module, for detecting the second voltage of the 3rd MOSFET drain electrode after turning off the 3rd MOSFET, if detecting described
Second voltage is less than or equal to pre-set cut-in voltage and compares threshold value, exports to accumulator and extends timeslice instruction, if not
It detects that the second voltage is less than or equal to pre-set cut-in voltage and compares threshold value, is exported to accumulator and reduce timeslice
Instruction；
Accumulator, for the output according to sampling module, to the turn-on time for including in the driving control signal in current period
It carries out extending timeslice or reduces the operation of timeslice；
Register obtains the driving control signal in next period for refreshing the calculated result of accumulator.
6. full bridge rectifier as claimed in claim 5, which is characterized in that the sampling module includes: the first phase inverter,
One d type flip flop, the second d type flip flop and delay cell, wherein
The input terminal of first phase inverter accesses driving control signal, and output end is single with the end D of the first d type flip flop and delay respectively
The input terminal of member is connected；
The CP of first d type flip flop terminates the event instruction letter that threshold value is compared compared with cut-in voltage into second voltage
Number, R is terminated into driving voltage, and the end Q is connected with the end D of the second d type flip flop；
The output end of delay cell is connected with the end CP of the second d type flip flop；
The end Q of second d type flip flop is connected with the end P of accumulator.
7. full bridge rectifier as claimed in claim 5, which is characterized in that the register includes: third d type flip flop,
Four d flip-flop, the 5th d type flip flop, the 6th d type flip flop, the 7th d type flip flop, the 8th d type flip flop, the 9th d type flip flop and the tenth
D type flip flop, wherein
Third d type flip flop, four d flip-flop, the 5th d type flip flop, the 6th d type flip flop, the 7th d type flip flop, the 8th d type flip flop,
The end CP of 9th d type flip flop and the tenth d type flip flop is respectively connected to driving control signal, and the end D is connected with accumulator respectively.
8. full bridge rectifier as claimed in claim 4, which is characterized in that the configurable delay circuit includes: second anti-
Phase device, third phase inverter, the 4th phase inverter, the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor,
6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor, the 9th metal-oxide-semiconductor, first capacitor, the second capacitor, third capacitor, the 4th capacitor,
5th capacitor, the 6th capacitor, the 7th capacitor and the 8th capacitor, wherein
The input terminal of second phase inverter accesses driving control signal, and output end is connected with the input terminal of third phase inverter；
The output end of third phase inverter is connected with the grid of the first metal-oxide-semiconductor；
The drain electrode of first metal-oxide-semiconductor respectively with the second metal-oxide-semiconductor, third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor,
The drain electrode of seven metal-oxide-semiconductors, the 8th metal-oxide-semiconductor and the 9th metal-oxide-semiconductor is connected, and source electrode is electric with first capacitor, the second capacitor, third respectively
One end of appearance, the 4th capacitor, the 5th capacitor, the 6th capacitor, the 7th capacitor and the 8th capacitor is connected；
Second metal-oxide-semiconductor, third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor and
The grid of 9th metal-oxide-semiconductor be respectively connected to the first signal, second signal, third signal, fourth signal, the 5th signal, the 6th signal,
7th signal, the 8th signal；
Second metal-oxide-semiconductor, third metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor and
The source electrode of 9th metal-oxide-semiconductor successively with first capacitor, the second capacitor, third capacitor, the 4th capacitor, the 5th capacitor, the 6th capacitor,
The other end of seven capacitors and the 8th capacitor is connected；
First capacitor, the second capacitor, third capacitor, the 4th capacitor, the 5th capacitor, the 6th capacitor, the 7th capacitor and the 8th electricity
The capacitance of appearance is incremented by multiple；
The input terminal of 4th phase inverter is connected with the drain electrode of the 9th metal-oxide-semiconductor and preset current source, output end and third
The grid of MOSFET is connected.
9. full bridge rectifier as claimed in claim 3, which is characterized in that the first comparator, in input current
Current period in, detection the 3rd MOSFET drain electrode first voltage, determine the first voltage be greater than pre-set shutdown
Voltage threshold, to the first instruction of the first drive voltage controller output；
First drive voltage controller is generated for receiving the first instruction for controlling the first MOSFET's and the 3rd MOSFET
Driving control signal, output to the first delayer；
First delayer, for the second voltage of the 3rd MOSFET drain electrode being detected, if detecting institute after turning off the 3rd MOSFET
It states second voltage and compares threshold value less than or equal to pre-set cut-in voltage, the driving to the output of the first drive voltage controller
The pre-set timeslice of turn on time delay for including in control signal, is less than or equal to if the second voltage is not detected
Pre-set cut-in voltage compares threshold value, the conducting to including in the driving control signal of the first drive voltage controller output
Time reduces pre-set timeslice.
10. full bridge rectifier as claimed in claim 9, which is characterized in that the first comparator includes: the first ratio of shutdown
Compared with device and open first comparator, wherein
First comparator is turned off, non-inverting input terminal is connected with the drain electrode of the 3rd MOSFET, inverting input terminal access shutdown voltage threshold
Value, output end are connected with the input terminal of the first drive voltage controller；
First comparator is opened, non-inverting input terminal access cut-in voltage compares threshold value, the leakage of inverting input terminal and the 3rd MOSFET
Extremely it is connected, output end is connected with the input terminal of the input terminal of the first drive voltage controller and the first delayer respectively.
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| CN201811595789.4A CN109600062B (en) | 2018-12-25 | 2018-12-25 | Control method of full-bridge rectification and full-bridge rectification circuit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110492768A (en) * | 2019-08-13 | 2019-11-22 | 苏州格远电气有限公司 | Rectifier circuit |
| CN111277169A (en) * | 2020-01-20 | 2020-06-12 | 华大半导体有限公司 | Interface circuit for collecting piezoelectric energy and control unit and method thereof |
| CN111371443A (en) * | 2020-05-28 | 2020-07-03 | 上海南麟电子股份有限公司 | Active rectifier bridge circuit and on-chip integrated system |
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| CN110492768A (en) * | 2019-08-13 | 2019-11-22 | 苏州格远电气有限公司 | Rectifier circuit |
| CN111277169A (en) * | 2020-01-20 | 2020-06-12 | 华大半导体有限公司 | Interface circuit for collecting piezoelectric energy and control unit and method thereof |
| CN111277169B (en) * | 2020-01-20 | 2024-04-19 | 华大半导体有限公司 | Interface circuit for piezoelectric energy collection, control unit and method thereof |
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| US11251718B2 (en) | 2020-05-28 | 2022-02-15 | Shanghai Natlinear Electronics Co., Ltd. | Active rectifier bridge circuit and on-chip integrated system |
| CN114123735A (en) * | 2020-08-31 | 2022-03-01 | 华为数字能源技术有限公司 | Series-parallel converter protection system, controller and converter |
| CN114123735B (en) * | 2020-08-31 | 2024-05-03 | 华为数字能源技术有限公司 | Series-parallel converter protection system, controller and converter |
| CN116388588A (en) * | 2023-05-29 | 2023-07-04 | 成都市易冲半导体有限公司 | Rectifying control circuit, electric energy receiving device and electronic equipment |
| CN116388588B (en) * | 2023-05-29 | 2023-08-18 | 成都市易冲半导体有限公司 | Rectifying control circuit, electric energy receiving device and electronic equipment |
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