CN109599434A - Semiconductor devices - Google Patents
Semiconductor devices Download PDFInfo
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- CN109599434A CN109599434A CN201811597948.4A CN201811597948A CN109599434A CN 109599434 A CN109599434 A CN 109599434A CN 201811597948 A CN201811597948 A CN 201811597948A CN 109599434 A CN109599434 A CN 109599434A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 230000005669 field effect Effects 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 238000009825 accumulation Methods 0.000 abstract description 23
- 239000000463 material Substances 0.000 description 14
- 238000000034 method Methods 0.000 description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000005611 electricity Effects 0.000 description 5
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 230000005533 two-dimensional electron gas Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Electrodes Of Semiconductors (AREA)
Abstract
The present invention provides a kind of semiconductor devices, including first electrode layer, substrate layer, N-type drift region, source configuration and the second electrode lay being cascading；Source configuration includes mutually independent N+ doped region, and around the base area P of each N+ doped region setting, the adjacent base area P is spaced each other；The second electrode lay includes source electrode and gate electrode, source electrode is corresponding and connects N+ doped region and the setting of the base area P, gate electrode corresponds to the setting of the N-type drift region between N+ doped region, the base area P and the adjacent base area P, and is connected between gate electrode and N-type drift region and source configuration by gate oxide；Al is provided between gate oxide and N-type drift regionxGa1‑xN layers, AlxGa1‑xN layers of correspondence simultaneously connect N-type drift region, 0 x≤1 <.Semiconductor devices provided by the invention has improved accumulation layer resistance and higher working efficiency.
Description
Technical field
The present invention relates to a kind of semiconductor devices.
Background technique
Metal Oxide Semiconductor Field Effect Transistor (Metal Oxide Semiconductor Field Effect
Transistor, MOSFET) it is fast, low in energy consumption because having the advantages that switching speed, and it is widely used in every field.But
MOSFET haves the shortcomings that current density is small, conducting resistance is big.
Summary of the invention
In view of the problems in the background art, the embodiment of the invention provides a kind of semiconductor devices, to improve electric current
Density reduces conducting resistance.
In order to solve the above-mentioned technical problem, the embodiment of the present invention provides a kind of semiconductor devices, semiconductor devices include according to
The secondary first electrode layer being stacked, substrate layer, N-type drift region, source configuration and the second electrode lay；Source configuration includes phase
Mutual independent N+ doped region, and around the base area P of each N+ doped region setting, the adjacent base area P is spaced each other；Second electrode
Layer includes source electrode and gate electrode, and source electrode is corresponding and connects N+ doped region and the setting of the base area P, gate electrode correspond to N+ doped region, P
N-type drift region setting between base area and the adjacent base area P, and pass through grid between gate electrode and N-type drift region and source configuration
Oxide layer connection；Al is provided between gate oxide and N-type drift regionxGa1-xN layers, AlxGa1-xN layers of correspondence simultaneously connect described
N-type drift region, 0 x≤1 <.
According to an aspect of an embodiment of the present invention, AlxGa1-xN layers with a thickness of 5nm~500nm.
According to an aspect of an embodiment of the present invention, AlxGa1-xN layers with a thickness of 10nm~100nm.
According to an aspect of an embodiment of the present invention, AlxGa1-xN layers with a thickness of 10nm~50nm.
According to an aspect of an embodiment of the present invention, AlxGa1-xIn N layers, 0.1≤x≤0.5.
According to an aspect of an embodiment of the present invention, the adjacent base area P passes through N-type drift region interval, AlxGa1-xN layers right
It should and be set to the surface of the N-type drift region between the adjacent base area P.
According to an aspect of an embodiment of the present invention, AlxGa1-xN layers of surface towards N-type drift region and gate oxide
The surface towards N-type drift region flush.
According to an aspect of an embodiment of the present invention, AlxGa1-xN layers of length is equal to or less than between the adjacent base area P
Distance.
According to an aspect of an embodiment of the present invention, semiconductor devices is the metal oxide semiconductor field-effect of plane formula
Transistor MOSFET or insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT).
According to an aspect of an embodiment of the present invention, the adjacent base area P passes through groove interval, the base area P and N-type drift region
Between interface be higher than groove bottom surface；Gate electrode, gate oxide and AlxGa1-xN layers are set in groove；Gate electrode and source electricity
It is isolated between pole by insulating oxide.
According to an aspect of an embodiment of the present invention, AlxGa1-xN layers be set to groove be located at interface wall surface below.
According to an aspect of an embodiment of the present invention, semiconductor devices is the metal oxide semiconductor field-effect of plough groove type
Transistor MOSFET or insulated gate bipolar transistor IGBT.
Semiconductor devices provided in an embodiment of the present invention in the on-state, is formed between gate oxide and N-type drift region
Accumulation layer, electronics can reach N-type drift region by source configuration and through accumulation layer, by drifting about in gate oxide and N-type
Al is set between areaxGa1-xN layers, and make AlxGa1-xN layers of correspondence simultaneously connect N-type drift region, can significantly improve the electricity of accumulation layer
Current density reduces conducting resistance, improves the working efficiency of semiconductor devices.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, will make below to required in the embodiment of the present invention
Attached drawing is briefly described, for those of ordinary skill in the art, without creative efforts, also
Other drawings may be obtained according to these drawings without any creative labor.Attached drawing is not drawn according to actual proportions.
Fig. 1 is the structural schematic diagram of semiconductor devices provided by one embodiment of the present invention.
Fig. 2 is the structural schematic diagram of plane formula MOSFET provided by one embodiment of the present invention.
Fig. 3 is the conducting resistance schematic diagram of plane formula MOSFET in Fig. 2.
Fig. 4 is the structural schematic diagram of plane formula IGBT provided by one embodiment of the present invention.
Fig. 5 is the structural schematic diagram of grooved MOSFET provided by one embodiment of the present invention.
Fig. 6 is the structural schematic diagram for the plough groove type IGBT that another embodiment of the present invention provides.
Label declaration:
110, first electrode layer；
120, substrate layer；121, N+ type substrate layer；122, N+ type buffer layer；123, P+ type current collection layer；
130, N-type drift region；131, accumulation layer；
140, source configuration；141, the base area P；142, N+ doped region；
150, the second electrode lay；151, source electrode；152, gate electrode；153, gate oxide；154,AlxGa1-xN layers；155,
Insulating oxide.
Specific embodiment
The feature and exemplary embodiment of various aspects of the invention is described more fully below, in order to make mesh of the invention
, technical solution and advantage be more clearly understood, with reference to the accompanying drawings and embodiments, the present invention is further retouched in detail
It states.It should be understood that specific embodiment described herein is only configured to explain the present invention, it is not configured as limiting the present invention.
To those skilled in the art, the present invention can be real in the case where not needing some details in these details
It applies.Below the description of embodiment is used for the purpose of better understanding the present invention to provide by showing example of the invention.
It should be noted that, in this document, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence " including ... ", it is not excluded that including
There is also other identical elements in the process, method, article or equipment of the element.In addition, herein, " multiples' "
The meaning for two or more, " more than ", " following " be include this number.
Fig. 1 schematically shows a kind of semiconductor devices provided in an embodiment of the present invention.Please refer to Fig. 1, the present invention one
A kind of semiconductor devices that a embodiment provides includes the first electrode layer 110 being cascading, substrate layer 120, N-type drift
Move area 130, source configuration 140 and the second electrode lay 150；Source configuration 140 includes mutually independent N+ doped region 142, and
Around the base area P 141 of each N+ doped region 142 setting, the adjacent base area P 141 is spaced each other；The second electrode lay 150 includes source
Electrode 151 and gate electrode 152, source electrode 151 corresponds to and connects N+ doped region 142 and the base area P 141 is arranged, and gate electrode 152 is corresponding
N-type drift region 130 between N+ doped region 142, the base area P 141 and the adjacent base area P 141 is arranged, and gate electrode 152 and N-type are floated
It moves between area 130 and source configuration 140 and is connected by gate oxide 153；It is set between gate oxide 153 and N-type drift region 130
It is equipped with AlxGa1-xN layer 154,0 < x≤1, AlxGa1-xN layer 154 is corresponding and connects N-type drift region 130, and gate oxide 153 covers
AlxGa1-xN layer 154 is arranged.
Semiconductor devices provided in an embodiment of the present invention in the on-state, gate oxide 153 and N-type drift region 130 it
Between formed accumulation layer 131, electronics can by source configuration 140 and through accumulation layer 131 reach N-type drift region 130, by
Al is set between gate oxide 153 and N-type drift region 130xGa1-xN layer 154, and make AlxGa1-xN layer 154 is corresponding and connects N-
Type drift region 130, AlxGa1-xN layer 154 can generate two-dimensional electron gas (the two-dimensional electron of high concentration
Gas, 2DEG), to significantly improve the current density of accumulation layer 131, the conducting resistance of semiconductor devices is reduced, improves semiconductor
The working efficiency of device.
Further, AlxGa1-xThe thickness of N layer 154 can be required according to the specific targets of semiconductor devices, pass through theory
It calculates, is determined using simulation softwares such as SENTAURUS or SILVACO, achieve the purpose that most preferably to improve accumulation layer resistance.
In some embodiments, AlxGa1-xThe upper thickness limit of N layer 154 can for 30nm, 50nm, 70nm, 100nm,
120nm,150nm,200nm,300nm,400nm,500nm；AlxGa1-xThe lower thickness limit of N layer 154 can for 5nm, 8nm,
10nm、15nm、20nm、30nm、50nm、80nm、100nm、130nm、180nm、200nm。AlxGa1-xThe thickness of N layer 154 can be with
It is any combination of the upper limit or lower limit.
Optionally, AlxGa1-xN layer 154 with a thickness of 5nm~500nm.
Optionally, AlxGa1-xN layer 154 with a thickness of 10nm~100nm.
Optionally, AlxGa1-xN layer 154 with a thickness of 10nm~50nm.
Optionally, AlxGa1-xIn N layer 154,0.1≤x≤0.5.
Optionally, the material of N-type drift region 130 is Si, SiC, GaAs, GaN or other semiconductor materials.
AlxGa1-xN layer 154 can be after the base area P 141 and N+ doped region 142 are formed, and pass through deposit or other techniques
It is formed.
In some embodiments, it is spaced between the adjacent base area P 141 by N-type drift region 130, AlxGa1-xN layer 154
The surface of N-type drift region 130 for corresponding to and being set between the adjacent base area P 141.
Further, AlxGa1-xThe surface towards N-type drift region 130 of N layer 154 and gate oxide 153 towards N-
The surface of type drift region 130 flushes.
Further, AlxGa1-xThe length of N layer 154 can be equal to or less than the distance between the adjacent base area P 141 L.
Such as AlxGa1-xThe length of N layer 154 is equal to the distance between the adjacent base area P 141 L, can preferably improve accumulation layer 131
Current density reduces the conducting resistance of semiconductor devices.
Semiconductor devices can be plane formula MOSFET.As an example, please with reference to Fig. 2, plane formula MOSFET
Including first electrode layer 110, substrate layer 120, N-type drift region 130, source configuration 140 and the second electrode being cascading
Layer 150；Source configuration 140 includes mutually independent N+ doped region 142, and around the base area P of each N+ doped region 142 setting
141, it is spaced by N-type drift region 130 between the adjacent base area P 141；The second electrode lay 150 includes source electrode 151 and grid electricity
Pole 152, source electrode 151 is corresponding and connects N+ doped region 142 and the setting of the base area P 141, gate electrode 152 corresponding N+ doped region 142, P
N-type drift region 130 between base area 141 and the adjacent base area P 141 is arranged, and gate electrode 152 and N-type drift region 130 and source electrode
It is connected between structure 140 by gate oxide 153；Al is provided between gate oxide 153 and N-type drift region 130xGa1-xN
Layer 154, AlxGa1-xN layer 154 is corresponding and connects N-type drift region 130, and gate oxide 153 covers AlxGa1-xN layer 154 is arranged.
Wherein, first electrode layer 110 is drain electrode.
Substrate layer 120 is N+ type substrate layer 121.Optionally, the material of N+ type substrate layer 121 is Si, SiC, GaAs, GaN
Or other semiconductor materials.
Optionally, the material of N-type drift region 130 is Si, SiC, GaAs, GaN or other semiconductor materials.
As shown in figure 3, the conducting resistance of plane formula MOSFET includes source contact resistance RCS, source resistance RN+, channel electricity
Hinder RCH, accumulation layer resistance RA, JFET zone resistance RJFET, drift zone resistance RD, resistance substrate RSUB, drain contact resistance RCD.By
Al is provided between gate oxide 153 and N-type drift region 130 in plane formula MOSFETxGa1-xN layer 154, AlxGa1-xN layers
154 can generate the two-dimensional electron gas of high concentration, significantly improve the current density of accumulation layer 131, make accumulation layer resistance RASignificant drop
It is low, to reduce the conducting resistance of semiconductor devices, improve the working efficiency of semiconductor devices.
In order to more clearly show AlxGa1-xThe beneficial effect of N layer 154, is provided in gate oxide 153 and N-type drift region
Al is not provided between 130xGa1-xThe conventional plane formula MOSFET of N layer 154 in gate oxide 153 and N-type drift region 130
Between be provided with AlxGa1-xThe plane formula MOSFET of N layer 154 as a comparison, conventional plane formula MOSFET and the embodiment of the present invention
Plane formula MOSFET other features it is identical.Wherein, the plane formula of conventional plane formula MOSFET and the embodiment of the present invention
Cellular size (cell pitch) width W of MOSFET is 20 μm, and the distance between adjacent base area P 141 L is 6 μm, this hair
Al in the plane formula MOSFET of bright embodimentxGa1-xN layer 154 with a thickness of 30nm, x=0.3.
Conventional plane formula MOSFET, voltage rating are accumulation layer resistance R under 50VAFor 0.66m Ω cm2, in its electric conduction
Accounting in resistance is 29.5%, is only second to channel resistance RCH.According to formula RA=ρ × L=L/ (q × μn× n), it is available to be somebody's turn to do
Electron amount in the accumulation layer of conventional plane formula MOSFET is n=L/ (q × μn×RA).By between the adjacent base area P 141 away from
From L=6 μm, quantity of electric charge q=1.6 × 10-19C, accumulation layer resistance RA=0.66m Ω cm2, accumulation layer electron mobility μn=
200cm2It is available that/(Vs) brings formula into, accumulation layer electron amount n=2.84 × 1016cm-3。
And the plane formula MOSFET of the embodiment of the present invention, due to being arranged between gate oxide 153 and N-type drift region 130
There is AlxGa1-xN layer 154, AlxGa1-xThe two-dimensional electron gas that N layer 154 generates is up to 5 × 1019cm-3, significantly improve accumulation layer
131 current density makes accumulation layer resistance RAIt significantly reduces, is only about 6.6 × 10-4mΩ·cm2, 3 orders of magnitude are reduced,
Component part compared to other conducting resistances can be ignored substantially, therefore, significantly reduce the electric conduction of semiconductor devices
Resistance, improves the working efficiency of semiconductor devices.
Semiconductor devices can be plane formula IGBT.As an example, include please with reference to Fig. 4, plane formula IGBT
First electrode layer 110, substrate layer 120, N-type drift region 130, source configuration 140 and the second electrode lay being cascading
150；Source configuration 140 includes mutually independent N+ doped region 142, and around the base area P of each N+ doped region 142 setting
141, it is spaced by N-type drift region 130 between the adjacent base area P 141；The second electrode lay 150 includes source electrode 151 and grid electricity
Pole 152, source electrode 151 is corresponding and connects N+ doped region 142 and the setting of the base area P 141, gate electrode 152 corresponding N+ doped region 142, P
N-type drift region 130 between base area 141 and the adjacent base area P 141 is arranged, and gate electrode 152 and N-type drift region 130 and source electrode
It is connected between structure 140 by gate oxide 153；Al is provided between gate oxide 153 and N-type drift region 130xGa1-xN
Layer 154, AlxGa1-xN layer 154 is corresponding and connects N-type drift region 130, and gate oxide 153 covers AlxGa1-xN layer 154 is arranged.
Wherein, first electrode layer 110 is collector.
Substrate layer 120 includes the N+ type buffer layer 122 and P+ type current collection layer 123 being stacked, wherein N+ type buffer layer
122 is adjacent with N-type drift region 130, and P+ type current collection layer 123 and first electrode layer 110 are adjacent.
Optionally, the material of N-type drift region 130 is Si, SiC, GaAs, GaN or other semiconductor materials.
In some embodiments, the adjacent base area P 141 is by groove interval, between the base area P 141 and N-type drift region 130
Interface be higher than groove bottom surface；Gate electrode 152, gate oxide 153 and AlxGa1-xN layer 154 is set in groove；Gate electrode
It is isolated between 152 and source electrode 151 by insulating oxide 154.
Further, AlxGa1-xN layer 154 is set to the boundary between the base area P 141 and N-type drift region 130 of groove
Face wall surface below.That is AlxGa1-xInterface of the N layer 154 between the base area P 141 and N-type drift region 130 changes hereinafter, reaching
Kind accumulation layer resistance RAEffect.
Optionally, AlxGa1-xN layer 154 be set to the wall surface of groove and the partial sidewall face that is connect with wall surface on,
AlxGa1-xThe top surface of N layer 154 is flushed with the interface between the base area P 141 and N-type drift region 130.In other examples,
AlxGa1-xThe top surface of N layer 154 may also be below the interface between the base area P 141 and N-type drift region 130.Can play compared with
Improve accumulation layer resistance R wellAEffect.
It is understood that can also be the interface between the base area P 141 and N-type drift region 130 of groove with
Under part wall on Al is setxGa1-xN layer 154, such as in groove between the base area P 141 and N-type drift region 130
Al is set in the side wall surface below of interfacexGa1-xN layer 154, is arranged Al on the wall surface of groovexGa1-xN layer 154, or in ditch
It is arranged in the side wall surface below of the interface between the base area P 141 and N-type drift region 130 of slot and on base wall portion face
AlxGa1-xN layer 154, can play improves accumulation layer resistance RAEffect.
Further, when being provided with Al in the side wall surface of groovexGa1-xWhen N layer 154, AlxGa1-xN layer 154 towards N-type
The surface of drift region 130 is flushed with the surface towards source configuration 140 of gate oxide 153.
Semiconductor devices can be grooved MOSFET.As an example, please with reference to Fig. 5, grooved MOSFET
Including first electrode layer 110, substrate layer 120, N-type drift region 130, source configuration 140 and the second electrode being cascading
Layer 150；Source configuration 140 includes mutually independent N+ doped region 142, and around the base area P of each N+ doped region 142 setting
141, by groove interval between the adjacent base area P 141, and the interface between the base area P 141 and N-type drift region 130 is higher than ditch
The bottom surface of slot；The second electrode lay 150 includes source electrode 151 and gate electrode 152, and gate electrode 152 is set in groove, and gate electrode
It is connected between 152 and N-type drift region 130 and source configuration 140 by gate oxide 153；Insulation is covered in the notch of groove
Oxide layer 155, source electrode 151 covers insulating oxide 155 and is arranged, and source electrode 151 is corresponding and connects N+ doped region 142 and P
Base area 141 is arranged；Al is provided between gate oxide 153 and N-type drift region 130xGa1-xN layer 154, AlxGa1-xN layer 154
N-type drift region 130 is corresponded to and connects, gate oxide 153 covers AlxGa1-xN layer 154 is arranged.
Wherein, first electrode layer 110 is drain electrode.
Substrate layer 120 is N+ type substrate layer 121.Optionally, the material of N+ type substrate layer 121 is Si, SiC, GaAs, GaN
Or other semiconductor materials.
Optionally, the material of N-type drift region 130 is Si, SiC, GaAs, GaN or other semiconductor materials.
Semiconductor devices can be plough groove type IGBT.As an example, include please with reference to Fig. 6, plough groove type IGBT
First electrode layer 110, substrate layer 120, N-type drift region 130, source configuration 140 and the second electrode lay being cascading
150；Source configuration 140 includes mutually independent N+ doped region 142, and around the base area P of each N+ doped region 142 setting
141, by groove interval between the adjacent base area P 141, and the interface between the base area P 141 and N-type drift region 130 is higher than ditch
The bottom surface of slot；The second electrode lay 150 includes source electrode 151 and gate electrode 152, and gate electrode 152 is set in groove, and gate electrode
It is connected between 152 and N-type drift region 130 and source configuration 140 by gate oxide 153；Insulation is covered in the notch of groove
Oxide layer 155, source electrode 151 covers insulating oxide 155 and is arranged, and source electrode 151 is corresponding and connects N+ doped region 142 and P
Base area 141 is arranged；Al is provided between gate oxide 153 and N-type drift region 130xGa1-xN layer 154, AlxGa1-xN layer 154
N-type drift region 130 is corresponded to and connects, gate oxide 153 covers AlxGa1-xN layer 154 is arranged.
Wherein, first electrode layer 110 is collector.
Substrate layer 120 includes the N+ type buffer layer 122 and P+ type current collection layer 123 being stacked, wherein N+ type buffer layer
122 is adjacent with N-type drift region 130, and P+ type current collection layer 123 and first electrode layer 110 are adjacent.
Optionally, the material of N-type drift region 130 is Si, SiC, GaAs, GaN or other semiconductor materials.
The above description is merely a specific embodiment, it is apparent to those skilled in the art that,
For convenience of description and succinctly, the specific work process of the system of foregoing description, can be with reference in aforementioned system embodiment
It is correspondingly connected with structure, details are not described herein.It should be understood that scope of protection of the present invention is not limited thereto, it is any to be familiar with this technology
The technical staff in field in the technical scope disclosed by the present invention, can readily occur in various equivalent modifications or substitutions, these are repaired
Changing or replacing should be covered by the protection scope of the present invention.
Claims (10)
1. a kind of semiconductor devices, which is characterized in that first electrode layer, substrate layer, N-type including being cascading are drifted about
Area, source configuration and the second electrode lay；The source configuration includes mutually independent N+ doped region, and around each N+
The base area P of doped region setting, the adjacent base area P is spaced each other；The second electrode lay includes source electrode and gate electrode, institute
It is corresponding and connect the N+ doped region and the base area P setting to state source electrode, the gate electrode corresponds to the N+ doped region, described
N-type drift region setting between the base area P and the adjacent base area P, and the gate electrode and the N-type drift region and the source
It is connected between the structure of pole by gate oxide；
Al is provided between the gate oxide and the N-type drift regionxGa1-xN layers, the AlxGa1-xN layers of correspondence simultaneously connect
Connect the N-type drift region, 0 x≤1 <.
2. semiconductor devices according to claim 1, which is characterized in that the AlxGa1-xN layers with a thickness of 5nm~
500nm；
Alternatively, the AlxGa1-xN layers with a thickness of 10nm~100nm；
Alternatively, the AlxGa1-xN layers with a thickness of 10nm~50nm.
3. semiconductor devices according to claim 1, which is characterized in that the AlxGa1-xIn N layers, 0.1≤x≤0.5.
4. semiconductor devices according to claim 1-3, which is characterized in that the adjacent base area P passes through institute
State N-type drift region interval, the AlxGa1-xN layers of correspondence and the N-type drift region being set between the adjacent base area P
Surface.
5. semiconductor devices according to claim 4, which is characterized in that the AlxGa1-xN layers towards the N-type float
The surface for moving area is flushed with the surface towards the N-type drift region of the gate oxide.
6. semiconductor devices according to claim 4, which is characterized in that the AlxGa1-xN layers of length is equal to or less than
The distance between adjacent described base area P.
7. semiconductor devices according to claim 4, which is characterized in that the semiconductor devices is the metal oxygen of plane formula
Compound semiconductor field effect transistor MOSFET or insulated gate bipolar transistor IGBT.
8. semiconductor devices according to claim 1-3, which is characterized in that the adjacent base area P passes through ditch
Slot interval, the interface between the base area P and the N-type drift region are higher than the bottom surface of the groove；
The gate electrode, the gate oxide and the AlxGa1-xN layers are set in the groove；
It is isolated between the gate electrode and the source electrode by insulating oxide.
9. semiconductor devices according to claim 8, which is characterized in that the AlxGa1-xN layers are set to the groove
Positioned at interface wall surface below.
10. semiconductor devices according to claim 8, which is characterized in that the semiconductor devices is the metal of plough groove type
Oxide semiconductor field effect transistor MOSFET or insulated gate bipolar transistor IGBT.
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