CN109587014A - SRIO real-time online analog simulation verification method, system and medium - Google Patents
SRIO real-time online analog simulation verification method, system and medium Download PDFInfo
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- CN109587014A CN109587014A CN201910075383.1A CN201910075383A CN109587014A CN 109587014 A CN109587014 A CN 109587014A CN 201910075383 A CN201910075383 A CN 201910075383A CN 109587014 A CN109587014 A CN 109587014A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
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- H04L43/0847—Transmission error
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Abstract
The present invention provides a kind of SRIO real-time online analog simulation verification method, system and media, include: PL logic module inside FPGA: completing the transmission of SRIO agreement IP kernel, complete the transmitting-receiving of SRIO analog frame and data frame, it completes real time monitoring and error message summarizes, complete to interact with the real time data of ARM1 inside FPGA by ACP interface and error message is interactive；ARM1 module inside FPGA: SRIO analog simulation function is realized.The present invention uses the proof scheme of online analog simulation in real time, data frame, protocol package etc. can be by the customized tissues of upper computer software, pass through regular data, purposive pack arrangement, the entire SRIO system of fast verification whether there is security risk, and multiple hardware platforms is supported to interconnect, it is whether correct to verify custom system hardware configuration.
Description
Technical field
The present invention relates to fields of communication technology, and in particular, to SRIO real-time online analog simulation verification method, system and
Medium.
Background technique
Existing scheme is mostly SRIO interactive system, SRIO interconnection interaction, SRIO+PCIE/SRIO+SATA；These schemes are equal
For the application scheme of SRIO, rather than analog simulation scheme.
SRIO transmission rate is fast, and consensus standard single channel supports that platform includes FPGA/ up to 10.3125Gbps at present
DSP/PPC supports the various topological structures such as starlike/netted/annular/tree-like/chrysanthemum chain, supports 256 individual end points and 16
In the case that the big system address space in position, so high speed, link are complicated, data are difficult quickly to position error reason once error.
The technical issues that need to address are embodied in the following at present:
1) the design is simulated in real time by the achievable SRIO online programmable of software+hardware platform, supports DPS platform/ARM
Platform/PPC platform/VPX cabinet；
2) software, which can dynamically set SRIO, needs simulation model and data, and hardware platform completes multi-channel data transmitting-receiving process,
This hardware platform can access in true SRIO routing or VPX cabinet simultaneously, verifies other SRIO board softwares and whether hardware is deposited
In BUG.
3) customized client layer data frame structure, such as transmission DMA data packet -> doorbell interruption -> register data frame ->
Message frame -> reception DMA data packet.
Patent document CN108156099A (publication number: 201711131865.1) disclosing a kind of SRIO exchange system,
It is characterized in that, including PowerPC, RapidIO exchange chip and peripheral circuit, RapidIO exchange chip pass through
High speed SerDes interface and PowerPC interconnect, and realize that 1.25,2.5,3.125,5.0 and 6.25Gbaud of single channel can match
The inner exchanging bandwidth of totally 48 road serial-ports, highest 240Gbps are realized in the transmission rate set, 5 exchange chip combinations；
PowerPC is converted electrical signals to by photoelectric conversion module and realizes that data are handed over outside fiber-optic signal and exchange system
It changes；Peripheral circuit includes power module, clock module, reseting module and interrupt management logic module.But in the patent document
The analog simulation scheme of the non-SRIO of scheme.
Patent document CN103530245A (it is mutual 201310527634.8) application number: to disclose a kind of SRIO based on FPGA
Coupling device is arranged SRIO interconnection module, fifo module and SRIO interface module, the data of each source device in FPGA and passes through respectively
SRIO interface module enters SRIO interconnection module, and fifo module is entered after the scheduling of SRIO interconnection module, and fifo module will
Data are transferred to SRIO interface module, and SRIO interface module is to purpose device output data；If SRIO interface module provides n and connects
Mouthful, each interface supports one device of connection, SRIO interconnection module to provide a moderator, each moderator phase for each device
A fifo module should be set；When the device of some interface connection is purpose device, the corresponding moderator of purpose device is active to institute
Data in data packet that device is inputted from interface carries out time-division slice scheduling, the data packet after scheduling through corresponding fifo module from
Corresponding SRIO interface output.But the analog simulation scheme of the non-SRIO of scheme described in the patent document.
Summary of the invention
For the defects in the prior art, the object of the present invention is to provide a kind of SRIO real-time online analog simulation authentications
Method, system and medium.
A kind of SRIO real-time online analog simulation verifying system provided according to the present invention, comprising:
PL logic module inside FPGA: completing the transmission of SRIO agreement IP kernel, completes the receipts of SRIO analog frame and data frame
Hair, completes real time monitoring and error message summarizes, and completes to interact and go out with the real time data of ARM1 inside FPGA by ACP interface
Wrong information exchange；
ARM1 module inside FPGA: SRIO analog simulation function is realized；
ARM0 module inside FPGA: realizing the interaction with host software, realizes the control and data interaction of multi-protocols chip；
Host software console module: customization analog frame and data, data monitoring and error message analysis when realizing simulation.
Preferably, PL logic module includes: inside the FPGA
SRIO protocol IP core module: IP kernel is carried by XILINX and completes SRIO physical layer and link layer functionality；In realization
Position machine software automatically configures transmission rate；Realize that upper computer software automatically switches channel pattern, the channel pattern includes: single-pass
Road mode, dual channel mode, 4 channel patterns；
SRIO analog frame and data frame transceiver module: by dma mode obtain ARM1 inside DDR3 simulation frame data and
Instruction, according to dependent instruction tissue data frame corresponding with sending port initiator or target port target, line number of going forward side by side
According to sending or receiving for frame；
The data frame include it is following any or appoint it is a variety of: NREAD frame, NWRITE frame, NWRITE_R frame, DOOR frame,
SWRITE frame, MESSAGE frame；
SRIO real time monitoring and error message summarizing module, comprising:
Sending port initiator: received data are monitored and are stored in DDR3；
Sending port initiator: monitoring doorbell, message interrupt are stored in DDR3 with the presence or absence of abnormal and generation error information
In；
Sending port initiator: monitoring maintenance frame response is with the presence or absence of in abnormal and generation error information deposit DDR3；
Target port target: received data are monitored and are stored in DDR3；
Target port target: monitoring other equipment doorbell, message interrupt are deposited with the presence or absence of abnormal and generation error information
Enter in DDR3；
Target port target: in monitoring maintenance frame data deposit DDR3；
Preferably, ARM0 module inside the FPGA:
PETELINUX is run, interacts, is interacted by OCM and FPGA ARM1, and real-time update with host computer
C code in ARM1, to complete the customization function of different simulation protocol chips.
Preferably, the host software console module:
Visual Simulation flow scheme is provided, data interaction and data monitoring and mistake are carried out by ICP/IP protocol and FPGA
Accidentally data analysis；Monitoring and update receive frame data；Summarize error message, and analyzes error node ID and error time etc.；Control
Whole system operating status processed；Real-time update simulation system.
A kind of SRIO real-time online analog simulation verification method provided according to the present invention, comprising:
PL logic step inside FPGA: completing the transmission of SRIO agreement IP kernel, completes the receipts of SRIO analog frame and data frame
Hair, completes real time monitoring and error message summarizes, and completes to interact and go out with the real time data of ARM1 inside FPGA by ACP interface
Wrong information exchange；
ARM1 step inside FPGA: SRIO analog simulation function is realized；
ARM0 step inside FPGA: realizing the interaction with host software, realizes the control and data interaction of multi-protocols chip；
Host software platform step: customization analog frame and data, data monitoring and error message analysis when realizing simulation.
Preferably, PL logic step includes: inside the FPGA
SRIO agreement IP kernel step: IP kernel is carried by XILINX and completes SRIO physical layer and link layer functionality；In realization
Position machine software automatically configures transmission rate；Realize that upper computer software automatically switches channel pattern, the channel pattern includes: single-pass
Road mode, dual channel mode, 4 channel patterns；
SRIO analog frame and data frame transceiving step: by dma mode obtain ARM1 inside DDR3 simulation frame data and
Instruction, according to dependent instruction tissue data frame corresponding with sending port initiator or target port target, line number of going forward side by side
According to sending or receiving for frame；
The data frame include it is following any or appoint it is a variety of: NREAD frame, NWRITE frame, NWRITE_R frame, DOOR frame,
SWRITE frame, MESSAGE frame；
SRIO real time monitoring and error message aggregation step, comprising:
Sending port initiator: received data are monitored and are stored in DDR3；
Sending port initiator: monitoring doorbell, message interrupt are stored in DDR3 with the presence or absence of abnormal and generation error information
In；
Sending port initiator: monitoring maintenance frame response is with the presence or absence of in abnormal and generation error information deposit DDR3；
Target port target: received data are monitored and are stored in DDR3；
Target port target: monitoring other equipment doorbell, message interrupt are deposited with the presence or absence of abnormal and generation error information
Enter in DDR3；
Target port target: in monitoring maintenance frame data deposit DDR3；
Preferably, ARM0 step inside the FPGA:
PETELINUX is run, interacts, is interacted by OCM and FPGA ARM1, and real-time update with host computer
C code in ARM1, to complete the customization function of different simulation protocol chips.
Preferably, the host software platform step:
Visual Simulation flow scheme is provided, data interaction and data monitoring and mistake are carried out by ICP/IP protocol and FPGA
Accidentally data analysis；Monitoring and update receive frame data；Summarize error message, and analyzes error node ID and error time etc.；Control
Whole system operating status processed；Real-time update simulation system.
Preferably, analog simulation parameter configuration and monitoring data the host software platform step: are carried out；
ARM0 step inside the FPGA: operation LINUX system and host carry out order and data interaction；
ARM1 step inside the FPGA: corresponding SRIO frame data are generated according to host software platform transmitting order to lower levels；
PL logic step inside the FPGA: data and instruction interaction are carried out with ARM1 in real time；SRIO IP kernel is controlled to carry out
Analog simulation data send or receive.
A kind of computer readable storage medium for being stored with computer program provided according to the present invention, the computer journey
The step of SRIO real-time online analog simulation verification method described in any of the above embodiments is realized when sequence is executed by processor.
Compared with prior art, the present invention have it is following the utility model has the advantages that
1, data frame of the present invention, protocol package etc. by regular data, can be had by the customized tissue of upper computer software
Purpose pack arrangement, the entire SRIO system of fast verification whether there is security risk；
2, the present invention accelerates software and hardware staff development progress, quickly positions BUG, can directly improve working efficiency and economy
Benefit；
3, whether the present invention supports multiple hardware platform interconnection, correct to verify custom system hardware configuration.
4, the present invention uses ACP DMA channel technology, and high speed completes FPGA and inside ARM data interaction, using 250MHz,
The dma mode of 64bits, burst=16, every bag data delay < 100ns, data throughout reaches 1200MB/s, for real-time
Property requires high chip also and can be carried out simulation.
5, for the present invention using the proof scheme of online analog simulation in real time, data frame, protocol package etc. can be soft by host computer
The customized tissue of part, by regular data, purposive pack arrangement, the entire SRIO system of fast verification is with the presence or absence of safety
Hidden danger, and multiple hardware platforms is supported to interconnect, it is whether correct to verify custom system hardware configuration.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, other feature of the invention,
Objects and advantages will become more apparent upon:
Fig. 1 is the real-time mould of SRIO of SRIO real-time online analog simulation verification method provided by the invention, system and medium
Quasi- simulation flow schematic diagram.
Specific embodiment
The present invention is described in detail combined with specific embodiments below.Following embodiment will be helpful to the technology of this field
Personnel further understand the present invention, but the invention is not limited in any way.It should be pointed out that the ordinary skill of this field
For personnel, without departing from the inventive concept of the premise, several changes and improvements can also be made.These belong to the present invention
Protection scope.
A kind of SRIO real-time online analog simulation verifying system provided according to the present invention, comprising:
PL logic module inside FPGA: completing the transmission of SRIO agreement IP kernel, completes the receipts of SRIO analog frame and data frame
Hair, completes real time monitoring and error message summarizes, and completes to interact and go out with the real time data of ARM1 inside FPGA by ACP interface
Wrong information exchange；
ARM1 module inside FPGA: SRIO analog simulation function is realized；
ARM0 module inside FPGA: realizing the interaction with host software, realizes the control and data interaction of multi-protocols chip；
Host software console module: customization analog frame and data, data monitoring and error message analysis when realizing simulation.
Specifically, PL logic module includes: inside the FPGA
SRIO protocol IP core module: IP kernel is carried by XILINX and completes SRIO physical layer and link layer functionality；In realization
Position machine software automatically configures transmission rate；Realize that upper computer software automatically switches channel pattern, the channel pattern includes: single-pass
Road mode, dual channel mode, 4 channel patterns；
SRIO analog frame and data frame transceiver module: by dma mode obtain ARM1 inside DDR3 simulation frame data and
Instruction, according to dependent instruction tissue data frame corresponding with sending port initiator or target port target, line number of going forward side by side
According to sending or receiving for frame；
The data frame include it is following any or appoint it is a variety of: NREAD frame, NWRITE frame, NWRITE_R frame, DOOR frame,
SWRITE frame, MESSAGE frame；
SRIO real time monitoring and error message summarizing module, comprising:
Sending port initiator: received data are monitored and are stored in DDR3；
Sending port initiator: monitoring doorbell, message interrupt are stored in DDR3 with the presence or absence of abnormal and generation error information
In；
Sending port initiator: monitoring maintenance frame response is with the presence or absence of in abnormal and generation error information deposit DDR3；
Target port target: received data are monitored and are stored in DDR3；
Target port target: monitoring other equipment doorbell, message interrupt are deposited with the presence or absence of abnormal and generation error information
Enter in DDR3；
Target port target: in monitoring maintenance frame data deposit DDR3；
Specifically, ARM0 module inside the FPGA:
PETELINUX is run, interacts, is interacted by OCM and FPGA ARM1, and real-time update with host computer
C code in ARM1, to complete the customization function of different simulation protocol chips.
Specifically, the host software console module:
Visual Simulation flow scheme is provided, data interaction and data monitoring and mistake are carried out by ICP/IP protocol and FPGA
Accidentally data analysis；Monitoring and update receive frame data；Summarize error message, and analyzes error node ID and error time etc.；Control
Whole system operating status processed；Real-time update simulation system.
SRIO real-time online analog simulation provided by the invention verifies system, and the SRIO that can be given through the invention exists in real time
The step process of line analog simulation verification method is realized.Those skilled in the art can be by the SRIO real-time online analog simulation
Verification method is interpreted as a preference of the SRIO real-time online analog simulation verifying system.
A kind of SRIO real-time online analog simulation verification method provided according to the present invention, comprising:
PL logic step inside FPGA: completing the transmission of SRIO agreement IP kernel, completes the receipts of SRIO analog frame and data frame
Hair, completes real time monitoring and error message summarizes, and completes to interact and go out with the real time data of ARM1 inside FPGA by ACP interface
Wrong information exchange；
ARM1 step inside FPGA: SRIO analog simulation function is realized；
ARM0 step inside FPGA: realizing the interaction with host software, realizes the control and data interaction of multi-protocols chip；
Host software platform step: customization analog frame and data, data monitoring and error message analysis when realizing simulation.
Specifically, PL logic step includes: inside the FPGA
SRIO agreement IP kernel step: IP kernel is carried by XILINX and completes SRIO physical layer and link layer functionality；In realization
Position machine software automatically configures transmission rate；Realize that upper computer software automatically switches channel pattern, the channel pattern includes: single-pass
Road mode, dual channel mode, 4 channel patterns；
SRIO analog frame and data frame transceiving step: by dma mode obtain ARM1 inside DDR3 simulation frame data and
Instruction, according to dependent instruction tissue data frame corresponding with sending port initiator or target port target, line number of going forward side by side
According to sending or receiving for frame；
The data frame include it is following any or appoint it is a variety of: NREAD frame, NWRITE frame, NWRITE_R frame, DOOR frame,
SWRITE frame, MESSAGE frame；
SRIO real time monitoring and error message aggregation step, comprising:
Sending port initiator: received data are monitored and are stored in DDR3；
Sending port initiator: monitoring doorbell, message interrupt are stored in DDR3 with the presence or absence of abnormal and generation error information
In；
Sending port initiator: monitoring maintenance frame response is with the presence or absence of in abnormal and generation error information deposit DDR3；
Target port target: received data are monitored and are stored in DDR3；
Target port target: monitoring other equipment doorbell, message interrupt are deposited with the presence or absence of abnormal and generation error information
Enter in DDR3；
Target port target: in monitoring maintenance frame data deposit DDR3；
Specifically, ARM0 step inside the FPGA:
PETELINUX is run, interacts, is interacted by OCM and FPGA ARM1, and real-time update with host computer
C code in ARM1, to complete the customization function of different simulation protocol chips.
Specifically, the host software platform step:
Visual Simulation flow scheme is provided, data interaction and data monitoring and mistake are carried out by ICP/IP protocol and FPGA
Accidentally data analysis；Monitoring and update receive frame data；Summarize error message, and analyzes error node ID and error time etc.；Control
Whole system operating status processed；Real-time update simulation system.
Specifically, analog simulation parameter configuration and monitoring data the host software platform step: are carried out；
ARM0 step inside the FPGA: operation LINUX system and host carry out order and data interaction；
ARM1 step inside the FPGA: corresponding SRIO frame data are generated according to host software platform transmitting order to lower levels；
PL logic step inside the FPGA: data and instruction interaction are carried out with ARM1 in real time；SRIO IP kernel is controlled to carry out
Analog simulation data send or receive.
A kind of computer readable storage medium for being stored with computer program provided according to the present invention, the computer journey
The step of SRIO real-time online analog simulation verification method described in any of the above embodiments is realized when sequence is executed by processor.
Below by preference, the present invention is more specifically illustrated:
Preference 1:
As shown in Figure 1, realizing that SRIO real-time online analog simulation is tested the present invention is based on the FGPA platform of XILINX ZYNQ
Card.
Analog simulation step includes:
Host software platform carries out analog simulation parameter configuration and monitoring data；
ARM0 operation LINUX system and host carry out order and data interaction inside FPGA；
ARM1 generates corresponding SRIO frame data according to host software platform transmitting order to lower levels inside FPGA；
PL logic carries out data and instruction interaction with ARM1 in real time by ACP dma mode inside FPGA；ACP DMA is
The integrated ACP of XILINX company ZYNQ Series FPGA can be accessed directly inside FPGA from port DMA high speed data transfer mode
ARM shared drive, handling capacity are not required to ARM and are controlled up to 1200MB/s, in this system design, are passed using this mode
Transmission of data can accomplish every frame data delay < 100ns, and mainly for requirement of real-time height, data throughout is big.
PL logic control SRIO IP kernel carries out the transmission of analog simulation data or receiving inside FPGA
1, it the interaction with the system that is verified: by can configure SRIO interface, supporting X1/X2/X4, supporting link rate dynamic
It is adjustable；
Support that optical fiber interface is transmitted；
Support that VPX chassis interface is transmitted；
2, PL logic inside FPGA: the transmission of SRIO agreement IP kernel is completed, completion SRIO simulates the transmitting-receiving of frame data, it is real to complete
When monitoring and error message summarize, by ACP interface completion interacted with the real time data of FPGA ARM1 and error message interact,
Upper computer software is facilitated to be monitored analysis；
2.1, SRIO agreement IP kernel:
IP kernel, which is carried, by XILINX completes SRIO physical layer and link layer functionality
Realize that upper computer software automatically configures transmission rate；
Realize that upper computer software automatically switches the channel X1/X2/X4；
2.2, the data transmit-receive of SRIO analog frame and data frame:
The simulation frame data of DDR3 and instruction inside ARM1 are obtained by dma mode, according to dependent instruction tissue
The data frame of initiator mode or target mode, comprising NREAD frame, NWRITE frame, NWRITE_R frame, DOOR frame,
SWRITE frame, MESSAGE frame, and sent or received according to frame length information.
2.3, SRIO module real time monitoring and error message summarizing module:
When being initiator: monitoring received data and be stored in DDR3；
When being initiator: monitoring doorbell, message interrupt are with the presence or absence of in abnormal and generation error information deposit DDR3；
When being initiator: monitoring maintenance frame response is with the presence or absence of in abnormal and generation error information deposit DDR3；
When being target: monitoring received data and be stored in DDR3；
When being target: monitoring other equipment doorbell, message interrupt are with the presence or absence of the deposit of abnormal and generation error information
In DDR3；
When being target: in monitoring maintenance frame data deposit DDR3；
High speed ACP DMA channel, real-time consistency treatment are communicated with ARM1 inside FPGA
Analogue data real-time tranception is carried out by ACP DMA channel, this mode directly maps DDR3 memory in ARM1 core, adopts
With the dma mode of 250MHz, 64bits, burst=16, every bag data delay < 100ns；
3, ARM1 program inside FPGA, SRIO analog simulation function are realized:
3.1, according to upper computer software order, corresponding SRIO analogue data frame is organized, and is stored in DDR3 and is mentioned for the part PL
It takes；
3.2, the end implementing monitoring PL incoming monitoring data and error message, and be stored in DDR3 to extract for PC software and divide
Analysis；
3.3, simulated technological process:
Simulation doorbell frame: different doorbell information can freely be set, doorbell sends interval and tested；
Simulation MESSAGE frame: mailbox, mail, message and its length can be freely set, sends to be spaced and be tested；
Data frame: each frame head of NREAD/NWRITE/NWRITE_R/SWRITE, data, length, transmission time interval are equal
Configuration, which is carried out, according to upper computer software generates frame data；
Maintenance frame: the relevant informations such as maintenance frame hop count, register can freely be set；
Purpose ID and source ID is simulated: can be changed ID number automatically on demand and be tested.
4, ARM0 runs PETALINUX inside FPGA, and realization is interacted with host software, and multi-protocols chip controls, data are handed over
It is mutual:
PETELINUX is run, is interacted by gigabit networking and host computer, is handed over by OCM and FPGA ARM1
Mutually, and can C code in real-time update ARM1, to complete the customization functions of different simulation protocol chips.
5, host software platform: data monitoring and error message analysis when analog frame and data customization, simulation
5.1, visual Simulation flow scheme is provided, data interaction and data monitoring are carried out by ICP/IP protocol and FPGA
And error data analysis.
5.2, monitoring data: monitoring and update receive frame data
5.3, error analysis: error message summarizes, and analyzes error node ID and error time etc.；
5.4, control module: control whole system operating status
5.5, update module: implement to update simulation system
Transmit real-time: delay is low, and rate is fast
FPGA PL arrives ARM section communication in part using ACP dma mode in this system, and every bag data transmission delay <
100ns, most rapid rate is up to 1200MB/s；FPGA ARM arrives part upper computer software using gigabit networking, and overtime transmission delay <
10us。
Analog simulation function:
Any one node in all frame structures of this system analog SRIO and data and SRIO network sends simulation
Data receive emulation data.
Implementation example 1: it realizes the simulating, verifying function under SRIO routing and DSP6678 platform, is quickly matched by this system
It sets SRIO router and makes its normal work, complete to transmit various frame data to DSP6678 platform, verifying dsp software configuration is
It is no that there are mistakes；
Implementation example 2: being fitted into VPX cabinet, and whether each node work of verifying VPX system is normal, and as a node
Monitoring host computer transmits data.
One skilled in the art will appreciate that in addition to realizing system provided by the invention in a manner of pure computer readable program code
It, completely can be by the way that method and step be carried out programming in logic come so that provided by the invention other than system, device and its modules
System, device and its modules are declined with logic gate, switch, specific integrated circuit, programmable logic controller (PLC) and insertion
The form of controller etc. realizes identical program.So system provided by the invention, device and its modules may be considered that
It is a kind of hardware component, and the knot that the module for realizing various programs for including in it can also be considered as in hardware component
Structure；It can also will be considered as realizing the module of various functions either the software program of implementation method can be Hardware Subdivision again
Structure in part.
Specific embodiments of the present invention are described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, those skilled in the art can make a variety of changes or modify within the scope of the claims, this not shadow
Ring substantive content of the invention.In the absence of conflict, the feature in embodiments herein and embodiment can any phase
Mutually combination.
Claims (10)
1. a kind of SRIO real-time online analog simulation verifies system characterized by comprising
PL logic module inside FPGA: completing the transmission of SRIO agreement IP kernel, completes the transmitting-receiving of SRIO analog frame and data frame, complete
Summarize at real time monitoring and error message, completes to interact and malfunction letter with the real time data of ARM1 inside FPGA by ACP interface
Breath interaction；
ARM1 module inside FPGA: SRIO analog simulation function is realized；
ARM0 module inside FPGA: realizing the interaction with host software, realizes the control and data interaction of multi-protocols chip；
Host software console module: customization analog frame and data, data monitoring and error message analysis when realizing simulation.
2. SRIO real-time online analog simulation according to claim 1 verifies system, which is characterized in that inside the FPGA
PL logic module includes:
SRIO protocol IP core module: IP kernel is carried by XILINX and completes SRIO physical layer and link layer functionality；Realize host computer
Software automatically configures transmission rate；Realize that upper computer software automatically switches channel pattern, the channel pattern includes: single channel mould
Formula, dual channel mode, 4 channel patterns；
SRIO analog frame and data frame transceiver module: obtaining the simulation frame data of DDR3 and instruction inside ARM1 by dma mode,
According to dependent instruction tissue data frame corresponding with sending port initiator or target port target, and carry out data frame
Send or receive；
The data frame include it is following any or appoint it is a variety of: NREAD frame, NWRITE frame, NWRITE_R frame, DOOR frame,
SWRITE frame, MESSAGE frame；
SRIO real time monitoring and error message summarizing module, comprising:
Sending port initiator: received data are monitored and are stored in DDR3；
Sending port initiator: monitoring doorbell, message interrupt are with the presence or absence of in abnormal and generation error information deposit DDR3；
Sending port initiator: monitoring maintenance frame response is with the presence or absence of in abnormal and generation error information deposit DDR3；
Target port target: received data are monitored and are stored in DDR3；
Target port target: monitoring other equipment doorbell, message interrupt are with the presence or absence of the deposit of abnormal and generation error information
In DDR3；
Target port target: in monitoring maintenance frame data deposit DDR3；
3. SRIO real-time online analog simulation according to claim 2 verifies system, which is characterized in that inside the FPGA
ARM0 module:
PETELINUX is run, interacts, is interacted by OCM and FPGA ARM1, and real-time update ARM1 with host computer
In C code, with complete it is different simulation protocol chips customization functions.
4. SRIO real-time online analog simulation according to claim 3 verifies system, which is characterized in that the host software
Console module:
Visual Simulation flow scheme is provided, data interaction and data monitoring and error number are carried out by ICP/IP protocol and FPGA
According to analysis；Monitoring and update receive frame data；Summarize error message, and analyzes error node ID and error time etc.；It controls whole
A system running state；Real-time update simulation system.
5. a kind of SRIO real-time online analog simulation verification method characterized by comprising
PL logic step inside FPGA: completing the transmission of SRIO agreement IP kernel, completes the transmitting-receiving of SRIO analog frame and data frame, complete
Summarize at real time monitoring and error message, completes to interact and malfunction letter with the real time data of ARM1 inside FPGA by ACP interface
Breath interaction；
ARM1 step inside FPGA: SRIO analog simulation function is realized；
ARM0 step inside FPGA: realizing the interaction with host software, realizes the control and data interaction of multi-protocols chip；
Host software platform step: customization analog frame and data, data monitoring and error message analysis when realizing simulation.
6. SRIO real-time online analog simulation verification method according to claim 5, which is characterized in that inside the FPGA
PL logic step includes:
SRIO agreement IP kernel step: IP kernel is carried by XILINX and completes SRIO physical layer and link layer functionality；Realize host computer
Software automatically configures transmission rate；Realize that upper computer software automatically switches channel pattern, the channel pattern includes: single channel mould
Formula, dual channel mode, 4 channel patterns；
SRIO analog frame and data frame transceiving step: obtaining the simulation frame data of DDR3 and instruction inside ARM1 by dma mode,
According to dependent instruction tissue data frame corresponding with sending port initiator or target port target, and carry out data frame
Send or receive；
The data frame include it is following any or appoint it is a variety of: NREAD frame, NWRITE frame, NWRITE_R frame, DOOR frame,
SWRITE frame, MESSAGE frame；
SRIO real time monitoring and error message aggregation step, comprising:
Sending port initiator: received data are monitored and are stored in DDR3；
Sending port initiator: monitoring doorbell, message interrupt are with the presence or absence of in abnormal and generation error information deposit DDR3；
Sending port initiator: monitoring maintenance frame response is with the presence or absence of in abnormal and generation error information deposit DDR3；
Target port target: received data are monitored and are stored in DDR3；
Target port target: monitoring other equipment doorbell, message interrupt are with the presence or absence of the deposit of abnormal and generation error information
In DDR3；
Target port target: in monitoring maintenance frame data deposit DDR3；
7. SRIO real-time online analog simulation verification method according to claim 6, which is characterized in that inside the FPGA
ARM0 step:
PETELINUX is run, interacts, is interacted by OCM and FPGA ARM1, and real-time update ARM1 with host computer
In C code, with complete it is different simulation protocol chips customization functions.
8. SRIO real-time online analog simulation verification method according to claim 7, which is characterized in that the host software
Platform step:
Visual Simulation flow scheme is provided, data interaction and data monitoring and error number are carried out by ICP/IP protocol and FPGA
According to analysis；Monitoring and update receive frame data；Summarize error message, and analyzes error node ID and error time etc.；It controls whole
A system running state；Real-time update simulation system.
9. SRIO real-time online analog simulation verification method according to claim 7, which is characterized in that the host software
Platform step: analog simulation parameter configuration and monitoring data are carried out；
ARM0 step inside the FPGA: operation LINUX system and host carry out order and data interaction；
ARM1 step inside the FPGA: corresponding SRIO frame data are generated according to host software platform transmitting order to lower levels；
PL logic step inside the FPGA: data and instruction interaction are carried out with ARM1 in real time；Control SRIO IP kernel is simulated
Emulation data send or receive.
10. a kind of computer readable storage medium for being stored with computer program, which is characterized in that the computer program is located
Manage the step of SRIO real-time online analog simulation verification method described in any one of claim 5 to 9 is realized when device executes.
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