CN109585375A - 半导体元件的制造方法 - Google Patents

半导体元件的制造方法 Download PDF

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Publication number
CN109585375A
CN109585375A CN201811107006.3A CN201811107006A CN109585375A CN 109585375 A CN109585375 A CN 109585375A CN 201811107006 A CN201811107006 A CN 201811107006A CN 109585375 A CN109585375 A CN 109585375A
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CN
China
Prior art keywords
laying
dielectric material
predecessor
containing metal
layer
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CN201811107006.3A
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English (en)
Inventor
彭羽筠
林耕竹
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN109585375A publication Critical patent/CN109585375A/zh
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • C23C16/45548—Atomic layer deposition [ALD] characterized by the apparatus having arrangements for gas injection at different locations of the reactor for each ALD half-reaction
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Abstract

一种半导体元件的制造方法包括蚀刻半导体基板以形成从半导体基板的顶表面延伸到半导体基板中的沟槽。第一衬垫层在沟槽的侧壁及底部上形成。沟槽在沉积第一衬垫层之后填充有介电材料。介电材料及第一衬垫层包括实质上相同的含金属三元介电材料。移除介电材料及第一衬垫层在半导体基板的顶表面上方的过量部分。

Description

半导体元件的制造方法
技术领域
本揭露是关于一种半导体元件的制造方法。
背景技术
随着半导体技术中的进展，已经存在对高储存容量、快速处理***、高效能、及低成本的不断增长的需求。为了满足这些需求，半导体工业继续缩小半导体元件的尺寸，这些半导体元件诸如金属氧化物半导体场效晶体管(MOSFET)、及finFET，并且亦增加集成电路(IC)上的这些半导体元件的封装密度以适应IC上的更大数量的半导体元件。此缩小已增加IC中半导体元件的处理及制造的复杂性。
发明内容
一种半导体元件的制造方法，包含蚀刻半导体基板以形成从半导体基板的顶表面延伸到半导体基板中的沟槽；在沟槽的侧壁及底部上沉积第一衬垫层；在沉积第一衬垫层之后用介电材料填充沟槽，其中介电材料及第一衬垫层包含实质上相同的含金属三元介电材料；以及移除介电材料及第一衬垫层在半导体基板的该顶表面上方的过量部分。
附图说明
当结合随附附图阅读时，自以下详细描述将很好地理解本揭示的态样。应注意，根据工业中的标准实务，各个特征并非按比例绘制。事实上，出于论述清晰的目的，可任意增加或减小各个特征的尺寸。
图1A至图1F是根据本揭示的一些实施例的各个阶段处的用于制造半导体结构的方法的横截面图；
图2是根据本揭示的一些实施例的半导体结构的横截面图；
图3A至图3D是根据本揭示的一些实施例的各个阶段处的用于制造半导体结构的方法的横截面图；
图4A是根据本揭示的一些实施例的旋转沉积设备400及晶圆的透视图；
图4B是图4A的旋转沉积设备的俯视图。
具体实施方式
以下揭示内容提供许多不同实施例或实例，以便实施所提供标的的不同特征。下文描述部件及排列的特定实例以简化本揭示。当然，这些仅为实例且并不意欲为限制性。例如，以下描述中在第二特征上方或第二特征上形成第一特征可包括以直接接触形成第一特征及第二特征的实施例，且亦可包括在第一特征与第二特征之间形成额外特征以使得第一特征及第二特征可不处于直接接触的实施例。另外，本揭示可在各个实例中重复元件符号及/或字母。此重复是出于简便性及清晰的目的且本身并不指示所论述的各个实施例及/或配置之间的关系。
另外，为了便于描述，本文可使用空间相对性术语(诸如“之下”、“下方”、“下部”、“上方”、“上部”及类似者)来描述诸图中所示出的一个元件或特征与另一元件(或多个元件)或特征(或多个特征)的关系。除了诸图所描绘的定向外，空间相对性术语意欲包含使用或操作中元件的不同定向。设备可经其他方式定向(旋转90度或处于其他定向)且由此可类似解读本文所使用的空间相对性描述词。
图1A至图1F是根据本揭示的一些实施例的各个阶段处的制造半导体结构的方法的横截面图。在一些实施例中，图1A至图1F中所示的半导体结构可为在处理集成电路(IC)或其部分期间制造的中间元件，这些中间元件可包括静态随机存取记忆体(SRAM)、逻辑电路、被动组件(诸如电阻器、电容器及电感器)、及/或主动组件(诸如p型场效晶体管(PFET)、n型FET(NFET)、多栅极FET、金属氧化物半导体场效晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极晶体管、高压晶体管、高频晶体管、其他记忆体单元及其组合)。
参考图1A。提供基板110。在一些实施例中，基板110是半导体基板。基板110可包括硅(Si)。或者，基板110可包括锗(Ge)、锗硅、砷化镓(GaAs)、或其他适当半导体材料。在一些替代实施例中，基板110可包括磊晶层。此外，基板110可包括绝缘体上半导体(SOI)结构，此结构其中具有埋入的介电层。埋入的介电层可为例如埋入的氧化物(BOX)层。SOI结构可通过一种方法来形成，此方法被称为通过布植氧来分离(SIMOX)技术、晶圆接合、选择性磊晶生长(SEG)、或其他适当方法。
图案化的遮罩层120(可为硬遮罩层)是在基板110的顶表面112上方形成。在一些实施例中，图案化的遮罩层120包括氮化物。例如，遮罩层120是由氮化硅(SiN)制成。然而，亦可使用其他材料，诸如SiON、碳化硅、或其组合。遮罩层120可通过诸如化学气相沉积(CVD)、电浆增强化学气相沉积(PECVD)、或低压化学气相沉积(LPCVD)的制程来形成。或者，遮罩层120可由氧化硅制成，且随后通过氮化而转化为SiN。
在一些实施例中，保护层130是在基板110的顶表面112上方且在遮罩层120与基板110之间形成。保护层130保护顶表面112而不与遮罩层120直接接触。例如，保护层130可以保护基板110中形成的主动区域。主动区域用于形成元件(诸如晶体管、电阻器等等)。取决于待形成的元件，如由设计条件所决定，主动区域可包括n阱或p阱。在一些实施例中，保护层130是由热氧化物制成。一旦形成，遮罩层120及保护层130经由适宜的光微影及蚀刻制程来图案化以在顶表面112上方形成开口122及132。
参考图1B。图1A的基板110经由开口122及132的暴露部分通过蚀刻制程(诸如反应性离子蚀刻(RIE))移除以在基板110中形成沟槽114。沟槽114的每一者皆具有底部114b及侧壁114s。在一些实施例中，沟槽114具有不同宽度。沟槽114的每一者皆具有宽度W及深度D。宽度W是在从约6nm至约50nm的范围中，且深度D是在从约48nm至约150nm的范围中。沟槽114的深宽比，深度D(本文有时称为沟槽高度)除以宽度W，可在从约1至约18的范围中。然而，熟悉此项技术者应认识到，在整个说明书中所阐述的尺寸及值是实例，且可改变为适合半导体元件的不同尺寸。
在一些实施例中，半导体元件可以是鳍式场效晶体管(FinFET)，且沟槽114经配置为分离在基板110中形成的相邻的两个半导体鳍116。换言之，半导体鳍116的一者是在沟槽114的相邻的两个沟槽之间。在图1B中，相邻的半导体鳍116具有不同的节距。
参考图1C。第一衬垫层140保形地形成在图1B的结构上方，亦即，在沟槽114的侧壁114s及底部114b上。第一衬垫层140是使用沉积技术来形成，此沉积技术可形成保形介电层，诸如热原子层沉积(ALD)、电浆增强(PE)ALD、脉冲PEALD、或原子层化学气相沉积(AL-CVD)。ALD是填充介电质的方法，此方法涉及在基板110上方沉积单层的前驱物、净化腔室、及将与前驱物反应的反应物引入以余留单层的产物。循环可以重复多次以建立起作用的具有足够厚度的层。在图1C中，第一衬垫层140具有厚度T1，此厚度是通过第一沉积制程的沉积循环来决定。在一些实施例中，第一衬垫层140是通过执行m次循环的第一沉积制程来形成，以达到厚度T1，其中m是等于或大于1。在一些实施例中，厚度T1大于沟槽114的宽度W的一半(参见图1B)，且本揭示不限于此方面。由于第一衬垫层140是通过执行ALD制程来形成，第一衬垫层140具有在不同宽度的沟槽114中的良好保形性。
第一衬垫层140包括元素A、B及氧化物，其中A是金属，诸如Al、Mg、Ti、Zn、Zr、Y、Ta、Hf或其他适宜金属，且B是Si或金属，诸如Al、Mg、Ti、Zn、Zr、Y、Ta、Hf或其他适宜金属。第一衬垫层140是含金属三元介电材料ABO且是以固溶体及/或介稳相的形式，诸如Al2TiO5、MgAl2O4、Al2SiO5、ZnSiO4或其他材料。利用这些形式，可以均匀地形成第一衬垫层140。
在第一沉积制程期间，图1B的结构定位在沉积处理腔室中的夹盘上。随后将真空施加至沉积处理腔室以移除氧气及水分，且将温度升高至适用于沉积的可接受水平。随后将第一前驱物P1及第二前驱物P2相继馈送至沉积处理腔室中。第一前驱物P1提供元素A，第二前驱物P2提供元素B，且第一前驱物P1、第二前驱物P2及氧气在图1B的结构上方(亦即，在基板110及图案化的遮罩层120上方且在沟槽114中)形成第一衬垫层140。第一前驱物P1及第二前驱物P2可为有机或卤素前驱物，且本揭示不限于此方面。
第一前驱物P1是含金属的前驱物，且具有写为ALn的式，L是[Cp]-、[Cp(Me)]-、[Cp(Et)]-、[N(Et)2]-、[N(Me)2]-、[Me]-、[Cl]-或其他适宜配体，且n是整数。Cp是环戊二烯基，Me是金属，Et是乙基，N是氮化物，且Cl是氯化物。第一前驱物P1可以是Al(CH3)3(TMA)、HfCl4、Mg[Cp(Et)]2或其他适宜前驱物。
在一些实施例中，第二前驱物P2是含金属前驱物，且具有写为BLn的式，L是[Cp]-、[Cp(Me)]-、[Cp(Et)]-、[N(Et)2]-、[N(Me)2]-、[Me]-、[Cl]-或其他适宜配体，且n是整数。第二前驱物P2可以是Zr[N(Et)2]4(TDEAZr)或其他适宜前驱物。在一些其他实施例中，第二前驱物P2是含硅前驱物，且具有写为SiHmLn的式，L是[NH2]-、[N(Me)2]-、[N(Et)2]-、[O(Me)]-、[Me]、[Cl]-、[Br]-、[I]-或其他适宜配体，n≥2，且m+n＝4。第二前驱物P2可以是SiCl4、SiH2[N(Et)2]2或其他适宜前驱物。
在一些实施例中，将处理气体馈送至沉积处理腔室中。处理气体是含氧气体，诸如NO、NO2、O2、O3、H2O及/或其他适宜气体。在一些实施例中，将载体气体馈送至沉积处理腔室中。载体气体是He、Ar、N2及/或其他适宜气体。在一些实施例中，第一沉积制程可以是电浆增强的沉积制程。亦即，第一沉积制程包括电浆处理，例如，在从约2MHz至约90MHz的范围中的频率下。
在一些实施例中，第一衬垫层140是由以固溶体形式的AlZrO制成，且Al/Zr≤0.05。第一前驱物P1是Al(CH3)3(TMA)，第二前驱物P2是Zr[N(Et)2]4(TDEAZr)，且第一衬垫层140是通过执行PEALD制程来形成。用于形成第一衬垫层140的载体气体是Ar或其他适宜气体。用于形成第一衬垫层140的处理气体是O2或其他适宜气体。沉积温度在从约100℃至约300℃的范围中的温度下执行。在一些实施例中，第一衬垫层140是通过执行m次循环的沉积制程来形成，其中m≧1。第一沉积制程包括电浆处理，例如在从约150瓦至约800瓦的范围中的功率下。
在一些其他实施例中，第一衬垫层140是由以固溶体形式的HfSiO制成，并且Hf/Si是在从约0.25至约1的范围中。第一前驱物P1是HfCl4，第二前驱物P2是SiCl4，且第一衬垫层140是通过执行热ALD制程来形成。用于形成第一衬垫层140的载体气体是N2或其他适宜气体。在一些实施例中，用于形成第一衬垫层140的处理气体是H2O或其他适宜气体，并且沉积温度在从约150℃至约400℃的范围中的温度下执行。在一些其他实施例中，用于形成第一衬垫层140的处理气体是O2或其他适宜气体，且沉积温度在从约350℃至约650℃的范围中的温度下执行。在一些实施例中，第一衬垫层140是通过执行m次循环的沉积制程来形成，其中m≧1。
在又一些其他实施例中，第一衬垫层140是由以固溶体形式的MgSiO制成，并且Si/Mg≤0.02。或者，第一衬垫层140是由以介稳相形式的MgSiO(诸如Mg2SiO4或MgSiO3)制成。第一前驱物P1是Mg[Cp(Et)]2，第二前驱物P2是SiH2[N(Et)2]2，且第一衬垫层140是通过执行热ALD制程来形成。用于形成第一衬垫层140的载体气体是N2及Ar，或其他适宜气体。用于形成第一衬垫层140的处理气体是H2O或其他适宜气体，并且沉积温度在从约150℃至约250℃的范围中的温度下执行。在一些实施例中，第一衬垫层140是通过执行m次循环的沉积制程来形成，其中m≧1。或者，第一衬垫层140是通过执行PEALD制程来形成。用于形成第一衬垫层140的载体气体是N2及Ar，或其他适宜气体。用于形成第一衬垫层140的处理气体是O2或其他适宜气体，并且沉积温度是在从约50℃至约250℃的范围中的温度下执行。在一些实施例中，第一衬垫层140是通过执行m次循环的沉积制程来形成，其中m≧1。第一沉积制程包括电浆处理，例如，在从约20瓦至约500瓦的范围中的功率下。
参考图1D。介电材料150是在图1C的结构上方(亦即，在第一衬垫层140上方)形成，并且通过执行第二沉积制程来填充沟槽114。介电材料150是使用可以形成填充介电材料的沉积技术形成，此沉积技术诸如热化学气相沉积(CVD)、PECVD、或远端PEALD。在图1D中，介电材料150具有最小的底部至顶部厚度T2，T2大于或等于沟槽114的宽度W，且本揭示不限于此方面。最小的底部至顶部厚度T2可为介电材料150在最宽沟槽114中的一部分的厚度。
介电材料150及第一衬垫层140具有实质上相同的含金属三元介电材料。亦即，介电材料150包括元素A、B及氧化物。介电材料150是三元化合物ABO并且以固溶体及/或介稳相的形式，诸如Al2TiO5、MgAl2O4、Al2SiO5、ZnSiO4或其他材料。利用这些形式，介电材料150可以均匀地形成。
在第二沉积制程期间，图1C的结构定位在沉积处理腔室中的夹盘上，此沉积处理腔室可与第一沉积制程的沉积处理腔室相同或不同。随后将第三前驱物P3及第四前驱物P4相继馈送至沉积处理腔室中。第三前驱物P3提供元素A，第四前驱物P4提供元素B，且第三前驱物P3、第四前驱物P4及氧气在图1C的结构上方(亦即，在第一衬垫层140上方)形成介电材料150。第三前驱物P3及第四前驱物P4可为有机或卤素前驱物，并且本揭示不限于此方面。
第三前驱物P3是含金属前驱物并具有写为ALn的式，L是[Cp]-、[Cp(Me)]-、[Cp(Et)]-、[N(Et)2]-、[N(Me)2]-、[Me]-、[Cl]-或其他适宜配体，并且n是整数。Cp是环戊二烯基，Me是金属，Et是乙基，N是氮化物，且Cl是氯化物。第三前驱物P3可以是Al(CH3)3(TMA)、Hf[N(Et)2]4、Mg[Cp]2或其他适宜前驱物。
在一些实施例中，第四前驱物P4是含金属前驱物且具有写为BLn的式，L是[Cp]-、[Cp(Me)]-、[Cp(Et)]-、[N(Et)2]-、[N(Me)2]-、[Me]-、[Cl]-或其他适宜配体，且n是整数。第四前驱物P4可以是Zr[N(Et)2]4(TDEAZr)或其他适宜前驱物。在一些其他实施例中，第四前驱物P4是含硅前驱物并具有写为SiHmLn的式，L是[NH2]-、[N(Me)2]-、[N(Et)2]-、[O(Me)]-、[Me]、[Cl]-、[Br]-、[I]-或其他适宜配体，n≥2，且m+n＝4。第四前驱物P4可以是SiH4、SiH2[O(Me)]2或其他适宜前驱物。
在一些实施例中，将处理气体馈送至沉积处理腔室中。处理气体是含氧气体，诸如NO、NO2、O2、O3、H2O及/或其他适宜气体。在一些实施例中，将载体气体馈送至沉积处理腔室中。载体气体是He、Ar、N2及/或其他适宜气体。在一些实施例中，第二沉积制程可以是电浆增强的沉积制程。亦即，第一沉积制程包括电浆处理，例如在从约2MHz至约90MHz的范围中的频率下。
在一些实施例中，第一衬垫层140及介电材料150是由以固溶体形式的AlZrO制成，且Al/Zr≤0.05。第三前驱物P3是Al(CH3)3(TMA)，第四前驱物P4是Zr[N(Et)2]4(TDEAZr)，且介电材料150是通过执行PECVD制程来形成。用于形成介电材料150的载体气体是N2或其他适宜气体。用于形成介电材料150的处理气体是O2或其他适宜气体。沉积温度在从约400℃至约600℃的范围中的温度下执行。第二沉积制程包括电浆处理，例如在从约150瓦至约800瓦的范围中的功率下。
在一些其他实施例中，第一衬垫层140及介电材料150是由以固溶体形式的HfSiO制成，且Hf/Si是在从约0.25至约1的范围中。第三前驱物P3是Hf[N(Et)2]4，第四前驱物P4是SiH4，且介电材料150是通过执行PECVD制程来形成。用于形成介电材料150的载体气体是N2或其他适宜气体。在一些实施例中，用于形成介电材料150的处理气体是O2或其他适宜气体，并且沉积温度在从约300℃至约450℃的范围中的温度下执行。第二沉积制程包括电浆处理，例如，在从约150瓦至约800瓦的范围中的功率下。
在又一些其他实施例中，第一衬垫层140及介电材料150是由以固溶体形式的MgSiO制成，且Si/Mg≤0.02。或者，介电材料150是由以介稳相形式的MgSiO(诸如Mg2SiO4或MgSiO3)制成。第三前驱物P3是Mg[Cp]2，第四前驱物P4是SiH2[O(Me)]2，且介电材料150是通过执行PECVD制程来形成。用于形成介电材料150的载体气体是N2或其他适宜气体。用于形成介电材料150的处理气体是O2或其他适宜气体，且沉积温度在从约350℃至约550℃的范围中的温度下执行。第二沉积制程包括电浆处理，例如，在从约200瓦至约750瓦的范围中的功率下。
参考图1E。退火制程190是在第一衬垫层140及介电材料150上执行。执行退火制程190以移除第一衬垫层140及介电材料150中的氢，以强化其机械强度。在一些实施例中，当第一衬垫层140及介电材料150是由AlZrO制成时，退火制程190可以在从约250℃至约600℃的范围中的温度下执行。在一些其他实施例中，当第一衬垫层140及介电材料150是由HfSiO制成时，退火制程190可以在从约350℃至约650℃的范围中的温度下执行。在又一些其他实施例中，当第一衬垫层140及介电材料150是由MgSiO制成，退火制程190可以在从约350℃至约1100℃的范围中的温度下执行。
在一些实施例中，当第一衬垫层140及介电材料150是由AlZrO制成时，所得第一衬垫层140及介电材料150具有在从约200GPa至约350GPa的范围中的杨氏模量。第一衬垫层140及介电材料150具有在从约5至约8的范围中的对氧化物的(CHxFy+O2)电浆干式蚀刻选择性。在本揭示中，对氧化物的蚀刻选择性是通过所选择蚀刻剂(亦即，在此情况下的(CHxFy+O2))蚀刻氧化物的速率除以所选择蚀刻剂蚀刻第一衬垫层140及介电材料150的速率来定义。此外，第一衬垫层140及介电材料150传导约10-8A/cm2至约10-10A/cm2的泄漏电流密度及约7.5MV/cm至约13MV/cm的击穿电场。
在一些其他实施例中，当第一衬垫层140及介电材料150是由HfSiO制成时，所得第一衬垫层140及介电材料150具有在从约70GPa至约175GPa的范围中的杨氏模量。第一衬垫层140及介电材料150具有在从约5至约8的范围中的对氧化物的(NF3+NH3)蚀刻选择性、在约10至约14的范围中的对Si的基于Cl2蚀刻选择性、及在约3.3至约5的范围中的对氮化物的dHF1000:1湿式蚀刻选择性。此外，第一衬垫层140及介电材料150传导约10-7A/cm2至约10- 10A/cm2的泄漏电流密度及约7.5MV/cm至约12MV/cm的击穿电场。
在又一些其他实施例中，当第一衬垫层140及介电材料150是由MgSiO制成时，所得第一衬垫层140及介电材料150具有在从约70GPa至约230GPa的范围中的杨氏模量。第一衬垫层140及介电材料150具有在从约20至约26的范围中的对氧化物的(NF3+NH3)蚀刻选择性、在从约10至约15的范围中的对Si的基于Cl2蚀刻选择性、及在约0至约30埃/秒的范围中的约70℃下的20％vol H2SO4湿式蚀刻速率。此外，第一衬垫层140及介电材料150传导约10- 8A/cm2至约10-10A/cm2的泄漏电流密度及约10MV/cm至约13MV/cm的击穿电场。
参考图1F。执行平坦化制程以移除沟槽114外部的第一衬垫层140及介电材料150以相应地形成第一衬垫层145’及隔离材料155’，其中第一衬垫层145’缠绕在隔离材料155’周围。由于第一衬垫层145’及隔离材料155’具有良好的机械强度及化学选择性，可以改良平坦化结构的效能。详细而言，若在沟槽114中填充的介电层具有弱机械强度(与半导体鳍116的机械强度失配)，介电层在最宽沟槽114中的一部分具有较低机械强度，且介电层在最窄沟槽114中的另一部分具有较高机械强度。介电层的此两部分可以易于移除且因此经平坦化至不同水平。亦即，平坦化介电层在最宽沟槽114中的部分具有低于平坦化介电层在最窄沟槽114中的部分的水平(顶表面)，使得平坦化制程可不形成均匀的顶表面。相比之下，由于图1F的第一衬垫层145’及隔离材料155’具有良好机械强度(与半导体鳍116的机械强度匹配)，与弱机械强度材料相比，此两层不易于移除，使得平坦化制程可以形成更均匀的顶表面。在一些实施例中，平坦化制程是化学机械研磨(CMP)制程。在一些实施例中，平坦化制程亦移除遮罩层120及保护层130(参见图1E)。所得第一衬垫层140及介电材料150可以被称为浅沟槽隔离(STI)结构以隔离半导体鳍116。在一些实施例中，栅极介电层及栅电极(未图示)可以在半导体鳍116上或上方形成以形成FinFET。
图2是根据本揭示的一些实施例的半导体结构的横截面图。在图2及图1F的半导体结构之间的差异涉及第二衬垫层160。在图2中，半导体结构进一步包括在基板110与第一衬垫层140之间的第二衬垫层160。第二衬垫层160可以由氮化物制成以保护在第二衬垫层160(亦即，在此情况中的基板110)下方的材料。例如，第二衬垫层160可以保护在第二衬垫层160下方的材料不被氧化。图2的半导体结构的其他相关结构细节类似于图1F的半导体元件，且由此，在此方面的描述将不在后文重复。
图3A至图3D是根据本揭示的一些实施例的各个阶段处的用于制造半导体结构的方法的横截面图。在一些实施例中，图3A至图3D所示的半导体结构可为在处理集成电路(IC)或其部分期间制造的中间元件，这些中间元件可包括静态随机存取记忆体(SRAM)、逻辑电路、被动组件(诸如电阻器、电容器及电感器)、及/或主动组件(诸如p型场效晶体管(PFET)、n型FET(NFET)、多栅极FET、金属氧化物半导体场效晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极晶体管、高压晶体管、高频晶体管、其他记忆体单元及其组合)。
参考图3A。提供基板310。在一些实施例中，基板310是半导体基板。基板310可包括硅(Si)。或者，基板310可包括锗(Ge)、锗硅、砷化镓(GaAs)或其他适当半导体材料。在一些替代实施例中，基板310可包括磊晶层。此外，基板310可包括绝缘体上半导体(SOI)结构，其中具有埋入的介电层。埋入的介电层可为例如埋入的氧化物(BOX)层。SOI结构可通过一种方法形成，此方法被称为通过布植氧来分离(SIMOX)技术、晶圆接合、选择性磊晶生长(SEG)或其他适当方法。
虚设栅极堆叠320在基板310上方形成。间隔305在两个相邻的虚设栅极堆叠320之间定义。虚设栅极堆叠320包括虚设栅极介电层322及在虚设栅极介电层322上方的虚设栅电极324。在一些实施例中，介电层(未图示)及虚设栅极层(未图示)可在基板310上方相继形成。虚设栅极层及介电层随后经图案化以相应地形成虚设栅电极324及虚设栅极介电层322。在一些实施例中，虚设栅电极324可由多晶硅(多Si)、多晶锗硅(多SiGe)或其他适宜材料制成。虚设栅极电介层322可由二氧化硅或其他适宜材料制成。
间隔结构330是至少在虚设栅极堆叠320的相对侧上形成。间隔结构330包括一或多种介电材料，诸如氧化硅、氮化硅、氮氧化硅、SiCN、SiCxOyNz或其组合。间隔结构330可以使用沉积方法形成，此沉积方法诸如电浆增强化学气相沉积(PECVD)、低压化学气相沉积(LPCVD)、亚常压化学气相沉积(SACVD)或类似者。形成间隔结构330可包括毯覆式形成间隔层并且随后执行蚀刻操作以移除间隔层的水平部分。间隔层的剩余垂直部分形成间隔结构330。
多个源极/漏极特征340在基板310中并邻近间隔结构330(部分)形成。在一些实施例中，源极/漏极特征340可以是掺杂的区域。在一些其他实施例中，源极/漏极特征340可以是磊晶结构。例如，多个凹槽可以在基板310中形成，并且半导体材料随后在凹槽中磊晶生长以形成磊晶结构。在一些其他实施例中，磊晶结构可以在不形成凹槽的情况下形成。
接触蚀刻终止层(CESL)350在源极/漏极特征340、间隔结构330、虚设栅极堆叠320、及基板310上方保形地形成。在一些实施例中，接触蚀刻终止层350可以是一或多个应变层。在一些实施例中，接触蚀刻终止层350具有拉伸应力且由Si3N4形成。在一些其他实施例中，接触蚀刻终止层350包括诸如氮氧化物的材料。在又一些其他实施例中，接触蚀刻终止层350可以具有包括多个层的复合结构，诸如在氧化硅层之上的氮化硅层。接触蚀刻终止层350可以使用电浆增强CVD(PECVD)形成，然而，亦可以使用其他常用方法，诸如低压CVD(LPCVD)、原子层沉积(ALD)及类似者。
参考图3B。含金属三元介电层360在图3A的结构上方(亦即，在接触蚀刻终止层350上方)保形地形成。由于含金属三元介电层360及第一衬垫层140(参见图1C)具有相同或类似的材料、结构及/或制造制程，此方面的描述将不在后文重复。随后，含金属三元介电材料370在含金属三元介电层360上方形成并且填充在虚设栅极堆叠320之间的间隔305。由于顶部金属三元介电材料370及介电材料150(参见图1D)具有相同或类似材料、结构及/或制造制程，此方面的描述将不在后文重复。
参考图3C。在含金属三元介电层360及含金属三元介电材料370上执行退火制程390。执行退火制程390以移除含金属三元介电层360及含金属三元介电材料370中的氢以强化其机械强度。在一些实施例中，由于含金属三元介电层360及含金属三元介电材料370不是可流动材料，退火后制程(用于固化可流动材料)可以在沉积此两层之后省略。亦即，退火制程390是可选的。此外，尽管执行退火制程390，但退火制程390的退火温度低于用于固化可流动材料的退火温度。在一些实施例中，当含金属三元介电层360及含金属三元介电材料370是由AlZrO制成时，退火制程390可以在从约350℃至约600℃的范围中的温度下执行。在一些其他实施例中，当含金属三元介电层360及含金属三元介电材料370是由HfSiO制成时，退火制程390可以在从约350℃至约650℃的范围中的温度下执行。在又一些其他实施例中，当含金属三元介电层360及含金属三元介电材料370是由MgSiO制成时，退火制程390可以在从约350℃至约1100℃的范围中的温度下执行。若退火温度是超出先前提及的范围，则退火制程390可不从含金属三元介电层360及含金属三元介电材料370有效地移除氢。之后执行平坦化制程以使含金属三元介电层360、含金属三元介电材料370、及接触蚀刻终止层350与虚设栅极堆叠320的顶表面326水平。在此方面，剩余的含金属三元介电层360及含金属三元介电材料370被称为层间介电层(ILD)。由于含金属三元介电层360及含金属三元介电材料370具有良好的机械强度及化学选择性，可以改良平坦化结构的效能。在一些实施例中，平坦化制程是化学机械研磨(CMP)制程。
参考图3D。采用替换栅极(RPG)处理方案。在RPG处理方案中，虚设多晶硅栅极(在此情况下的虚设栅电极324(参见图3A))提前形成并且稍后由金属栅极替换。在一些实施例中，移除虚设栅电极324以形成具有间隔结构330作为其侧壁的开口。在一些其他实施例中，亦移除虚设栅极介电层322(参见图3C)。或者，在一些实施例中，移除虚设栅电极324，同时保留虚设栅极介电层322。虚设栅极电极324(及虚设栅极介电层322)可通过干式蚀刻、湿式蚀刻或干式及湿式蚀刻的组合来移除。例如，湿式蚀刻制程可包括暴露至含氢氧化物溶液(例如，氢氧化铵)、去离子水及/或其他适宜蚀刻剂溶液。由于含金属三元介电层360及含金属三元介电材料370具有对硅、氧化物及/或氮化物的良好蚀刻选择性，可以改良在移除制程之后的剩余结构的效能。亦即，在移除制程期间不移除(或几乎不移除)含金属三元介电层360、含金属三元介电材料370。
金属栅极结构380分别形成在开口中及间隔结构330之间。金属栅极结构380是通过沉积包括导电金属(诸如铝、铜、钨、钛或其他适宜材料)的金属层来形成。在一些实施例中，沉积金属栅极结构380包括在沉积金属填充层386之前沉积高k介电层382及至少一个功函数层384。
图4A是根据本揭示的一些实施例的旋转沉积设备400及晶圆900的透视图，且图4B是图4A的旋转沉积设备400的俯视图。在一些实施例中，图1D中的第一衬垫层140及介电材料150以及图3B中的含金属三元介电层360及含金属三元介电材料370可以使用旋转沉积设备400来形成。旋转沉积设备400包括沉积处理腔室402、旋转基座405、多个净化气体供应管线490、及多个注入器412、422、432、442、452、462、472及482。旋转基座405经设置在沉积处理腔室402中。净化气体供应管线490经设置在沉积处理腔室402中，在旋转基座405上方，并且经配置以将沉积处理腔室402分为多个区段410、420、430、440、450、460、470及480。在一些实施例中，区段410、420、430及440经配置以形成第一衬垫层140及含金属三元介电层360，而区段450、460、470及480经配置以形成介电材料150及含金属三元介电材料370。亦即，注入器412经配置以将第一前驱物P1(参见图1C)提供至沉积处理腔室402中，注入器432经配置以将第二前驱物P2(参见图1C)提供至沉积处理腔室402中，注入器452经配置以将第三前驱物P3(参见图1D)提供至沉积处理腔室402中，注入器472经配置以将第四前驱物P4(参见图1D)提供至沉积处理腔室402中，且注入器422、442、462及482经配置以将反应气体(亦即，含氧气体)提供至沉积处理腔室402中。注入器412、422、432、442、452、462、472及482的每一者具有面向旋转基座405(及晶圆900)的开口(未图示)，且注入器412、422、432、442、452、462、472及482中的气体流出开口。
在形成第一衬垫层140(或含金属三元介电层360)期间，注入器412、422、432及442是打开的，而注入器452、462、472及482是关闭的。至少一个晶圆900(诸如图1B或图3A中的结构)经设置在沉积处理腔室402中。在一些实施例中，沉积处理腔室402可以容纳如图4A所示的多个晶圆900。旋转基座405顺时针旋转，且沉积处理腔室402经设置为真空。通过加热器将旋转基座405提前加热至预定温度(例如，在从约80℃至约350℃的范围中)，且晶圆900亦可以通过放置在旋转基座405上而在实质上相同的温度下加热。在将晶圆900加热并维持在预定温度下之后，净化气体(诸如N2)从净化气体供应管线490进入沉积处理腔室402。净化气体分离区段410、420、430、440、450、460、470及480并防止气体在不同区段410、420、430、440、450、460、470及480之中流动。随后，通过压力调节部分及真空泵将处理腔室402的内压设置于预定处理压力。接下来，将第一前驱物P1从注入器412供应至区段410，将第二前驱物P2从注入器432供应至区段430，并将反应气体从注入器422及442供应至区段420及440。
当晶圆900归因于旋转基座405的旋转而经过注入器412下方的区段410时，第一前驱物P1吸附在晶圆900上。接下来，当晶圆900经过注入器422下方的区段420时，反应气体(包括氧气)吸附在晶圆900上，并且因此晶圆900上的第一前驱物P1是由反应气体氧化。亦即，当晶圆900经过区段410及420一次时，在晶圆900上形成单层的金属氧化物。晶圆900随后经过注入器432下方的区段430，第二前驱物P2吸附在晶圆900上。随后，当晶圆900经过注入器442下方的区段440时，反应气体(包括氧气)吸附在晶圆900上，且因此晶圆900上的第二前驱物P2是由反应气体氧化。亦即，当晶圆900经过区段430及440一次时，在晶圆900上形成另一单层的金属氧化物。随后，晶圆900旋转并经过区段410、420、430及440复数次，并且因此具有预定厚度的第一衬垫层140(或含金属三元介电层360)在晶圆900上沉积。在沉积具有预定厚度的第一衬垫层140(或含金属三元介电层360)之后，停止供应第一前驱物P1、第二前驱物P2及反应气体。
随后，接着形成介电材料150(或含金属三元介电材料370)。注入器452、462、472及482是打开的，而注入器412、422、432及442是关闭的。在此阶段中，旋转基座405的旋转速度及/或前驱物及反应气体的流速可以经调谐以增加介电材料150(或含金属三元介电材料370)的沉积速率。例如，与形成第一衬垫层140(或含金属三元介电层360)相比，旋转基座405的旋转速度减小及/或前驱物及反应气体的流速增加。接下来，将第三前驱物P3供应至来自注入器452的区段450，将第四前驱物P4供应至来自注入器472的区段470，并将反应气体供应至来自注入器462及482的区段460及480。
当晶圆900经过注入器452下方的区段450时，第三前驱物P3吸附在晶圆900上。接下来，当晶圆900经过注入器462下方的区段460时，反应气体(包括氧气)吸附在晶圆900上，并且因此晶圆900上的第三前驱物P3是由反应气体氧化。亦即，当晶圆900经过区段450及460一次时，金属氧化物化合物层在晶圆900上形成。晶圆900随后经过注入器472下方的区段470，且第四前驱物P4吸附在晶圆900上。随后，当晶圆900经过注入器482下方的区段480时，反应气体(包括氧气)吸附在晶圆900上，且因此晶圆900上的第四前驱物P4是由反应气体氧化。亦即，当晶圆900经过区段470及480一次时，在晶圆900上形成另一金属氧化物化合物层。随后，晶圆900旋转并经过区段450、460、470及480复数次，并且因此具有预定厚度的介电材料150(或含金属三元介电材料370)在晶圆900上沉积。在一些实施例中，区段460及480装备有电浆模组，诸如微波电浆模组，以产生用于反应的自由基。在沉积具有预定厚度的介电材料150(或含金属三元介电材料370)之后，停止供应第三前驱物P3、第四前驱物P4及反应气体。接下来，将晶圆传送出沉积处理腔室402。
在一些实施例中，旋转沉积设备400可以用于形成图1D中的第一衬垫层140及介电材料150以及具有类似沉积温度的图3B中的含金属三元介电层360及含金属三元介电材料370。例如，旋转沉积设备400可以用于形成由MgSiO制成的图1D中的第一衬垫层140及介电材料150(图3B中的含金属三元介电层360及含金属三元介电材料370)。在形成MgSiO第一衬垫层140或MgSiO含金属三元介电层360期间，沉积处理腔室402的温度是在从约80℃至约350℃的范围中，注入器412提供Mg[Cp(Et)Cp]2,，注入器432提供SiH2[N(Et)2]2，并且注入器422及442提供氧源，诸如H2O或O2。此外，关闭注入器452、462、472及482。
在形成MgSiO介电材料150或MgSiO含金属三元介电材料370期间，旋转基座405的旋转速度及/或前驱物及反应气体的流速经调谐以增加MgSiO层的沉积速率。此外，沉积处理腔室402的温度是在从约80℃至约350℃的范围中，注入器452提供Mg[Cp]2，注入器472提供SiH2[N(Me)]2，并且注入器462及482提供氧源，诸如NO、NO2或O2。此外，区段460及480装备有电浆模组以产生用于反应的自由基。此外，关闭注入器412、422、432及442。
在形成MgSiO介电材料150或MgSiO含金属三元介电材料370之后，退火制程可以在MgSiO层上执行以移除层140及150(或层360及370)中的氢来强化其机械强度。例如，在约350℃至约1100℃的范围中的温度下执行退火制程。
根据一些实施例，形成包括保形底层及填充顶层的含金属三元介电结构。含金属三元介电结构具有良好的机械强度及化学选择性，使得含金属三元介电结构在平坦化制程之后不变形。此外，含金属三元介电结构亦具有对硅、氧化物及/或氮化物的良好蚀刻选择性，使得含金属三元介电结构不易于在蚀刻制程期间移除。此外，含金属三元介电结构可在相同的沉积处理腔室中形成，从而导致时间节省及成本降低。
根据一些实施例，一种方法包括蚀刻半导体基板以形成从半导体基板的顶表面延伸到半导体基板中的沟槽。第一衬垫层在沟槽的侧壁及底部上形成。沟槽在沉积第一衬垫层之后填充有介电材料。介电材料及第一衬垫层包括实质上相同的含金属三元介电材料。移除介电材料及第一衬垫层在半导体基板的顶表面上方的过量部分。
在一些实施例中，含金属三元介电材料为介稳相。
在一些实施例中，含金属三元介电材料是固溶体。
在一些实施例中，沉积第一衬垫层是通过原子层沉积制程来执行。
在一些实施例中，此方法进一步包括在沉积第一衬垫层之前在沟槽的侧壁及底部上沉积第二衬垫层。第二衬垫层包括氮。
在一些实施例中，含金属三元介电材料包括硅。
在一些实施例中，含金属三元介电材料包括氧。
在一些实施例中，含金属三元介电材料包括Al、Mg、Ti、Zn、Zr、Y、Ta、Hf或其组合。
在一些实施例中，在相同腔室中执行沉积第一衬垫层及填充沟槽。
在一些实施例中，此方法进一步包括退火第一衬垫层及介电材料。
根据一些实施例中，一种方法包括在半导体基板上方形成第一及第二栅极堆叠。含金属三元介电层在第一及第二栅极堆叠以及半导体基板上方保形地沉积。第一及第二栅极堆叠之间的间隔填充有含金属三元介电材料。移除含金属三元介电层及含金属三元介电材料在第一及第二栅极堆叠的顶表面上方的过量部分。
在一些实施例中，含金属三元介电层及含金属三元介电材料包括实质上相同的氧化物材料。
在一些实施例中，含金属三元介电层包括介稳相的材料。
在一些实施例中，含金属三元介电层包括固溶体。
在一些实施例中，在相同腔室中执行沉积含金属三元介电层及填充间隔。
在一些实施例中，含金属三元介电层包括Al、Mg、Ti、Zn、Zr、Y、Ta、Hf或其组合。
在一些实施例中，含金属三元介电层包括硅。
根据一些实施例，一种元件包括半导体基板、及半导体基板中的浅沟槽隔离(STI)结构。STI结构包括隔离材料及第一衬垫层。隔离材料是在半导体基板中。第一衬垫层缠绕在隔离材料周围。隔离材料及第一衬垫层包括实质上相同的含金属三元氧化物材料。
在一些实施例中，此元件进一步包括缠绕在第一衬垫层周围的第二衬垫层。第二衬垫层包括氮。
在一些实施例中，隔离材料包括Al、Mg、Ti、Zn、Zr、Y、Ta、Hf或其组合。
上文概述了若干实施例的特征，使得熟习此项技术者可更好地理解本揭示的态样。熟悉此项技术者应了解，可轻易使用本揭示作为设计或修改其他制程及结构的基础，以便实施本文所介绍的实施例的相同目的及/或实现相同优点。熟悉此项技术者亦应认识到，此类等效结构并未脱离本揭示的精神及范畴，且可在不脱离本揭示的精神及范畴的情况下产生本文的各种变化、替代及更改。

Claims (1)

1.一种半导体元件的制造方法，其特征在于，包含：
蚀刻一半导体基板以形成从该半导体基板的一顶表面延伸到该半导体基板中的一沟槽；
在该沟槽的侧壁及一底部上沉积一第一衬垫层；
在沉积该第一衬垫层之后用一介电材料填充该沟槽，其中该介电材料及该第一衬垫层包含实质上相同的一含金属三元介电材料；以及
移除该介电材料及该第一衬垫层在该半导体基板的该顶表面上方的过量部分。
CN201811107006.3A 2017-09-29 2018-09-21 半导体元件的制造方法 Pending CN109585375A (zh)

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