CN109585291A - 半导体结构的形成方法 - Google Patents

半导体结构的形成方法 Download PDF

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Publication number
CN109585291A
CN109585291A CN201711092274.8A CN201711092274A CN109585291A CN 109585291 A CN109585291 A CN 109585291A CN 201711092274 A CN201711092274 A CN 201711092274A CN 109585291 A CN109585291 A CN 109585291A
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China
Prior art keywords
layer
silicon
recess
fin
seed layer
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CN201711092274.8A
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Inventor
沙哈吉·B·摩尔
李承翰
潘正扬
王俊杰
张世杰
杨怀德
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本公开实施例描述形成p型完全应变沟道或n型完全应变沟道的例示性方法，其可减少因工艺造成沟道区中的外延成长缺陷或结构变形。例示性方法可包含(i)搭配三氟化氮与氨的等离子体的两个或多个表面预清洁处理循环，之后进行热处理；(ii)预烘烤；以及(iii)搭配硅籽晶层、硅锗籽晶层、或上述的组合外延成长硅锗。

Description

半导体结构的形成方法
技术领域
本公开实施例涉及半导体装置，更具体涉及完全应变沟道与其形成方法。
背景技术
互补金属氧化物半导体装置中的完全应变沟道，可改善载子移动率并降低装置的沟道电阻。此外，具有缩小沟道长度的互补金属氧化物半导体装置，可因载子移动率改善而保留应变诱发的增大驱动电流。
发明内容
本公开一实施例提供的半导体结构的形成方法，包括：提供掺杂区于基板的顶部上；成长第一外延层于掺杂区上；形成凹陷于第一外延层中，且凹陷对准掺杂区，其中形成凹陷的步骤包括部分蚀刻第一外延层；进行一或多道的表面预清洁处理循环，其中每一表面预清洁处理循环包括：暴露凹陷至等离子体；以及进行回火；以及形成第二外延层于凹陷中，其中形成第二外延层的步骤包括：在第一温度下进行预烘烤；在第二温度下形成籽晶层于凹陷中；以及在第三温度下形成第二外延层于籽晶层上，以填满凹陷。
附图说明
图1是一些实施例中，在鳍状物上形成完全应变沟道区的例示性方法其流程图。
图2是一些实施例中，具有氧化物层成长其上的基板剖视图。
图3是一些实施例中，光致抗蚀剂层中的开口对准n型区的剖视图。
图4是一些实施例中，硅外延层形成于基板的p型区与n型区上的剖视图。
图5是一些实施例中，在蚀刻工艺后形成凹陷于硅外延层中的剖视图。
图6是一些实施例中，在表面预清洁处理步骤之后，硅外延层中的凹陷其剖视图。
图7是一些实施例中，成长于硅外延层中的凹陷中的硅锗外延层其剖视图。
图8是一些实施例中，在化学机械平坦化步骤以及沉积硅层、氧化物层、与氮化物层之后，成长于硅外延层中的凹陷中的硅锗外延层其剖视图。
图9是一些实施例中，具有硅锗外延层与硅外延层形成其上的鳍状物其剖视图。
图10是一些实施例中，在沉积介电层于鳍状物之间后，具有硅锗外延层与硅外延层的鳍状物其剖视图。
图11是一些实施例中，在使鳍状物之间的介电层凹陷后，具有硅锗外延层与硅外延层的鳍状物其剖视图。
附图标记说明：
H、530 高度
W、520 宽度
100 方法
110、120、130、140、150、160 步骤
200 基板
210、820 氧化物层
300 光致抗蚀剂层
310 开口
320 n型区
400 p型区
410、510 硅外延层
420 盖层
500 凹陷
540 区域
700 硅锗外延层
800 堆叠
810 硅层
830 氮化物层
900、910 鳍状物
920 氮化物衬垫
1000 介电层
具体实施方式
下述内容提供的不同实施例或实例可实施本公开的不同结构。特定构件与排列的例子是用以简化本公开而非局限本公开。举例来说，形成第一结构于第二结构上的叙述包含两者直接接触，或两者之间隔有其他额外结构而非直接接触。此外，本公开的多种例子中可重复标号，但这些重复仅用以简化与清楚说明，不代表不同实施例及/或设置之间具有相同标号的单元之间具有相同的对应关系。
此外，空间性的相对用语如「下方」、「其下」、「较下方」、「上方」、「较上方」、或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件，而非局限于图示方向。元件亦可转动90°或其他角度，因此方向性用语仅用以说明图示中的方向。
场效晶体管指的是金属氧化物半导体场效晶体管。金属氧化物半导体场效晶体管可为建立在基板如半导体晶片的平坦表面之中或之上的平面结构。金属氧化物半导体场效晶体管亦可为三维垂直取向结构，其可具有称作鳍状物的半导体材料。用语「鳍状场效晶体管」指的是形成于半导体如硅的鳍状物上的场效晶体管，且鳍状物相对于晶片的平面表面为垂直取向。
用语“外延层”指的是结晶材料的层状物或结构。同样地，用语“外延成长”指的是成长结晶材料的层状物或结构的工艺。外延成长的材料可掺杂或未掺杂。
此处所述的用语“名义上的”，指的是在产品或工艺的设计阶段时，用于构件或工艺的特性或参数的期望值或目标值，以及高于及/或低于期望值的范围。数值范围通常来自于工艺中的微小变数或容忍度。除非特别定义，此处所述的技术或科学用语将与本领域技术人员通常理解的意义相同。
互补式金属氧化物半导体装置中的完全应变沟道，可改善载子移动率并降低装置的沟道电阻。此外，改善载子移动率可增加应变诱导的驱动电流，仍可维持于沟道长度缩小的互补式金属氧化物半导体装置中。用于p型场效晶体管与n型场效晶体管中的应变沟道材料可不同。举例来说(但不限于下述例子)，完全应变的硅/掺杂碳的硅沟道可增加n型场效晶体管中的电子移动率，而完全应变的硅锗沟道可增加p型场效晶体管中的空穴移动率。
完全应变外延沟道，可由硅鳍状物的顶部上的外延层形成。完全应变沟道的形成工艺需要多道光刻、蚀刻、预处理、回火、及成长步骤。一些步骤可能具有挑战性并导致不想要的效应，比如因外延成长层中存在的应力而产生的沟道区变形(如非垂直的侧壁)与外延成长缺陷(如堆叠错误)。这些不想要的效应会抵消全应变沟道的改良移对率。与n型全应变沟道(可采用硅、掺杂碳的硅、或上述的组合)相较，p型全应变沟道的硅对硅锗的晶格不匹配较大而更易产生缺陷。
此处所述的实施例关于p型全应变沟道的例示性制作方法，其可缓解因工艺造成的沟道区结构变形或外延成长缺陷。在一些实施例中，例示性工艺可包含(i)两次或多次搭配三氟化氮与氨等离子体的表面预清洁处理循环，接着进行热处理；(ii)预烘烤(回火)；以及(iii)搭配硅籽晶层、硅锗籽晶层、掺杂碳的硅籽晶层、或上述的组合外延成长硅锗。上述例示性方法亦可用以形成n型全应变沟道，其中步骤(iii)可置换为搭配硅籽晶层外延成长掺杂碳的硅。
图1是例示性方法100的流程图。方法100可形成p型的完全应变的硅锗沟道区于鳍状物的顶部上，且一晶体管可具有此沟道区。在一些实施例中，例示性的方法100可提供硅锗沟道区，其实质上不具有结构变形与外延成长缺陷如堆叠错误。在例示性方法100的多种步骤之间可进行其他步骤，但为简化而省略其他步骤的说明。例示性方法100不限于下述步骤，而可包含额外步骤。
举例来说，例示性方法100描述为形成p型全应变沟道于硅鳍状物的顶部中。依据下述说明，p型全应变沟道亦可形成于平面晶体管中。平面晶体管亦属本公开精神与范畴。此外如上所述，例示性方法100可用以形成n型全应变沟道。
例示性方法100的步骤110形成n型区于基板的顶部中。举例来说(但不限于下述例子)，n型区的形成方法如下述。如图2所示，沉积氧化物层210于基板200上。在一些实施例中，基板200可为基体半导体晶片或绝缘层上半导体晶片。此外，基板200的组成可为硅或另一半导体元素如锗；半导体化合物如硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、及/或锑化铟；半导体合金如硅锗、磷砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟、及/或磷砷化镓铟；或上述的组合。举例来说，例示性方法100中的基板200可为硅(比如单晶)。依据上述内容，基板200亦可采用其他材料。这些材料属于本公开精神与范畴。
在一些实施例中，氧化物层210的厚度可介于约至约之间(比如至)。在一些实施例中，氧化物层210为氧化硅层。在一些实施例中，氧化物层210可保护基板200的上表面免于污染，避免离子注入对基板200的多余损伤，以及控制离子注入步骤时的掺质深度。
接着可沉积光致抗蚀剂层300于氧化物层210上，如图3所示。在一些实施例中，可图案化光致抗蚀剂层300以形成开口310于部分的氧化物层210上，如图3所示。在一些实施例中，可采用离子注入以形成n型区320于基板200中。在一些实施例中，n型区320实质上对准开口310，因此光致抗蚀剂层300可作为注入掩模。在一些实施例中，n型掺质可包含砷、锑、或磷。在一些实施例中，n型区320中的n型掺质浓度可介于约5×1016原子/cm3至约1×1019原子/cm3之间。举例来说(但不限于下述例子)，n型区320的深度(沿着z方向)可介于约100nm至约500nm之间。然而n型区320其宽度(比如沿着x方向)与长度(比如沿着y方向)的变化可视装置种类而定。举例来说，装置可为逻辑装置、静态随机存取存储器、或类似装置。在形成n型区320后，可移除光致抗蚀剂层300。
在一些实施例中，与图案化光致抗蚀剂层相关的类似工艺可用以形成p型区400于基板200中。p型区400与n型区320相邻，如图4所示。在一些实施例中，可采用p型掺质如硼的离子注入工艺，形成p型区400。举例来说(但不限于下述例子)，p型区400的掺质浓度可介于约5×1016原子/cm3至约1×1019原子/cm3之间。
在形成n型区320与p型区400之后，可采用湿式清洁工艺移除任何残留的光致抗蚀剂层。在一些实施例中，可进行回火步骤以电性活化掺质(比如使掺质自间隙位置移动至硅晶格位置)，并修复在离子注入步骤中发生的任何硅晶格损伤。举例来说(但不限于下述例子)，晶体损伤修复可发生在约500℃，而掺质活化可发生在约950℃。举例来说(但不限于下述例子)，回火步骤可在回火炉或快速热回火腔室中进行。在一些实施例中，在掺质活化回火后可移除氧化物层210。
在图1所示的步骤120中，可直接外延成长硅外延层410于基板200上，如图4所示。在一些实施例中，硅外延层410的厚度可介于约至约之间。举例来说(但不限于下述例子)，硅外延层410的沉积方法可为化学气相沉积工艺。用于硅外延层的源气体可包含硅烷、四氯化硅、三氯硅烷、或二氯硅烷。氢气可作为反应物气体，其可减少前述的源气体。外延层的沉积温度可介于约700℃至约1250℃之间，端视采用的气体而定。举例来说，氯原子越少的源气体(如二氯硅烷)所需的外延成长温度，低于氯原子越多的源气体(如四氯硅烷)所需的外延成长温度。上述气体种类与参数范围仅用以举例说明而非局限本公开。
在一些实施例中，盖层420可成长于硅外延层410的顶部上。盖层420的厚度可大于或等于约(比如介于至约之间)。在一些实施例中，盖层420可为氧化物层如氧化硅。在其他实施例中，盖层420可为氮化物如氮化硅。
如图5与步骤130所示，可采用干蚀刻工艺形成凹陷500于硅外延层410中。在一些实施例中，凹陷500可对准n型区320。在一些实施例中，凹陷500的至少一尺寸名义上等于n型区320的尺寸。举例来说，凹陷500与n型区320沿着x方向的宽度可相同，但沿着y方向的长度不同。举例来说，可通过光刻使凹陷500对准n型区320。举例来说(但不限于下述例子)，可施加光致抗蚀剂层于硅外延层410上。可依据所需图案曝光并显影光致抗蚀剂。举例来说，所需图案可为开口，其对准n型区320并露出部分的盖层420。光致抗蚀剂未曝光的区域可由湿式清洁步骤移除，以保留显影光致抗蚀剂的所需图案于盖层420上(比如p型区400上的硅外延层410与盖层420上)。干蚀刻工艺可移除盖层420的露出区域，并部分地蚀刻硅外延层410。显影光致抗蚀剂(比如位于p型区400的顶部上)可覆盖部分的盖层420，保护其免于干蚀刻工艺的蚀刻化学品造成的蚀刻。一旦蚀刻盖层420的露出区域与部分蚀刻硅外延层410，可采用湿式清洁步骤移除残留的显影光致抗蚀剂。此工艺的结果为蚀刻部分的硅外延层410，以形成图5所示的凹陷500。形成凹陷500于硅外延层410中的干蚀刻工艺，可调整为不移除n型区320其顶部上的薄硅外延层如上述。在一些实施例中，保留于n型区320其顶部上的硅层510的厚度，可介于约至约之间。在一些实施例中，硅层510原本沉积为硅外延层410的一部分。在一些实施例中，干蚀刻工艺可采用不同的气体化学品，以分别用于盖层420与硅外延层410。
在一些实施例中，硅外延层410中的凹陷500可具有宽度520与高度530。宽度520可介于约至约之间，且名义上可等于n型区320的宽度。硅外延层410的厚度与凹陷500其底部处的硅层510的厚度之间的差距，可等于凹陷500的高度530。
在一些实施例中，在形成凹陷500于硅外延层410中之后，凹陷500的顶角处的盖层420其边缘将圆润化。上述圆润化可能来自于蚀刻工艺。此外，蚀刻工艺中可能蚀刻部分盖层420，因此蚀刻工艺后可能薄化盖层420。
如图1所示，步骤140可进行一或多个表面预清洁处理循环，使凹陷500的表面准备形成后续的外延层。在一些实施例中，表面预清洁处理循环可包含两步工艺：等离子体蚀刻步骤与回火步骤。在一些实施例中，可重复表面预清洁处理循环，比如进行两次或更多次的表面预清洁处理循环。在一些实施例中，表面预清洁处理设计为处理硅外延层410中的凹陷500其露出的表面。盖层420覆盖的硅外延层410的表面(比如p型区400上的硅外延层410其上表面)，将不会暴露至表面预清洁处理，因此不会被处理。
在一些实施例中，等离子体蚀刻步骤可包含三氟化氮与氨的气体混合物。等离子体亦可包含钝气如氩气、氦气、氢气、氮气、或上述的组合。在一些实施例中，提供至等离子体的电源可为射频或直流电。举例来说(但不限于下述例子)，等离子体蚀刻的温度可介于室温至约150℃之间，压力可介于约0.5Torr至约10Torr之间(比如2Torr至5Torr之间)。然而工艺参数不限于上述范围，因为这些参数范围取决于设备。在一些实施例中，等离子体蚀刻可自凹陷500的表面移除原生氧化硅及/或污染如碳、氟、氯、或磷。在一些实施例中，等离子体蚀刻可包含盐酸蒸气。
图6是图5的区域540的放大图，其显示暴露至三氟化氮与氨等离子体后的凹陷500。由于三氟化氮与氨等离子体的目标为氧化硅，等离子体蚀刻工艺会蚀刻部分的盖层420。如此一来，可减少硅外延层410其顶部的盖层厚度(或高度H)。此外，具有宽度W的凹陷可形成于凹陷500的顶角。如前所述，在形成凹陷时会使盖层420圆润化。在一些实施例中，高度H可大于或等于凹陷的宽度W，即H≥W。举例来说，凹陷的盖层420其高度H与宽度W的比例(H/W)可介于约1至1.5之间。在一些实施例中，依据等离子体蚀刻条件，表面预清洁处理的循环次数、或每一表面预清洁处理循环的时间，盖层420的高度H可缩小约至在一些实施例中，可调整盖层420的厚度以减缓蚀刻工艺中的负载效应，因此可一致地蚀刻具有不同装置密度的芯片。举例来说，芯片的逻辑区、静态随机存取存储器区、或输入/输出装置所在的区域，可具有不同的装置密度。在一些实施例中，可在后续的化学机械平坦化工艺之前，先以稀氢氟酸进一步控制盖层420的厚度。一些实施例中盖层420的厚度，以及芯片中具有不同密度的区域(如逻辑区与静态随机存取存储器)之间的化学机械平坦化负载之间具有相关性。如此一来，盖层420的厚度可用以减缓芯片其高密度区(如静态随机存取存储器)与低密度区(如逻辑区)之间的研磨速率差异(负载)。
可持续表面预清洁处理循环与回火步骤。回火步骤的温度可介于约30℃至约200℃之间(比如60℃至200℃)。在一些实施例中，回火步骤的压力小于等离子体蚀刻步骤的压力，比如低于1Torr(如0.6Torr)。在一些实施例中，回火步骤的氛围可为钝气如氩气、氦气、氮气、或上述的组合。在一些实施例中，回火步骤可自凹陷500的表面诱发污染与水气的脱气。在一些实施例中，回火步骤可持续约30秒(如约25秒)。如前所述，可依需求重复表面预清洁处理(等离子体蚀刻与回火)，使凹陷500的露出表面预备进行后续工艺。
在一些实施例中，表面清洁处理的每一循环可包括下述步骤之一：(i)回火、蚀刻、与回火的组合；(ii)蚀刻与回火的组合；以及(iii)蚀刻而不回火。在一些实施例中，每一上述程序可具有不同的原生氧化物移除速率。如此一来，不同的上述程序可采用不同的循环次数。举例来说，程序(i)与(ii)的循环次数可为两次，而程序(iii)的循环次数可为一次。在一些实施例中，省略回火可改善晶片中的蚀刻一致性(或晶片对晶片的蚀刻一致性)。在一些实施例中，原生氧化物的移除量可介于约至约之间。
方法100接着进行步骤150，以形成外延层于凹陷中。在一些实施例中，步骤150包含三个子步骤：(i)预烘烤、(ii)形成籽晶层、以及(iii)形成外延层于籽晶层上。
在一些实施例中，第一子步骤为加热处理或预烘烤，其温度T1可高于后续形成籽晶与外延层的温度T2与T3。换言之，温度T1>温度T2或温度T3。举例来说，预烘烤的温度T1可比籽晶层与外延层的形成温度T2与T3高约20％至约30％之间。在一些实施例中，预烘烤温度可介于约650℃至约1500℃之间，比如650℃至900℃之间或1000℃至1500℃之间。在一些实施例中，预烘烤氛围可为钝气如氩气、氮气、氦气、或上述的组合。此外，预烘烤压力可介于约1Torr至约500Torr之间(比如10Torr至50Torr之间或200Torr至300Torr之间)。举例来说(但不限于下述例子)，若预烘烤温度高则预烘烤压力低，反之亦然。举例来说，若预烘烤温度介于约1000℃至约1500℃之间，则预烘烤压力可介于约10Torr至约50Torr之间。相反地，若预烘烤温度介于约650℃至约900℃之间，则预烘烤压力可介于约200Torr至约300Torr之间。在一些实施例中，预烘烤时间可介于约50秒至约200秒之间(比如约100秒)。在一些实施例中，预烘烤工艺可减少凹陷的表面粗糙度，并减缓宽度改变或侧壁渐缩。在一些实施例中，在预烘烤步骤后，凹陷500的侧壁与下表面之间的角度可大于或等于90°。
在步骤150的第二子步骤中，形成籽晶层于盖层420未覆盖的硅外延层410其露出的表面上，比如凹陷500。在一些实施例中，籽晶层可成长于盖层420上。举例来说，籽晶层可成长于氧化硅或氮化硅上。在一些实施例中，籽晶层可为硅层、掺杂碳的硅层、硅锗层、或上述的组合，且其厚度介于约至约之间。举例来说，籽晶层可为硅/掺杂碳的硅/硅锗、硅/硅锗、或掺杂碳的硅/硅锗。在一些实施例中，
掺杂碳的硅中的碳掺质其原子％可介于约0.01原子％至约2原子％之间。在一些实施例中，籽晶层的厚度不足以填满凹陷。如此一来，籽晶层覆盖凹陷500其露出的表面，而不会填满凹陷500。举例来说(但不限于下述例子)，籽晶层的沉积方法可为化学气相沉积。举例来说(但不限于下述例子)，在氢气或氮气的存在下可采用硅烷及/或二氯硅烷形成硅籽晶层。(i)硅烷、硅乙烷、锗烷、或盐酸与(ii)氢气、氮气、氦气、或氩气的组合，可用以形成硅锗籽晶层。前述的气体种类仅用以举例而非局限本公开。
在一些实施例中，沉积籽晶层的温度T2可大于成长外延层的温度T3。籽晶层的沉积温度T2可介于约600℃至约750℃之间(比如700℃至750℃之间)。在一些实施例中，在温度T2的范围上限(比如约750℃)可达较高品质的籽晶层(具有较少缺陷)。在一些实施例中，籽晶层的形成工艺压力可介于约5Torr至约30Torr之间(比如15Torr)。在一些实施例中，籽晶层的沉积工艺时间可介于约5秒至约15秒之间，端视籽晶层的成长速率与所需的籽晶层厚度而定。上述参数范围仅用以举例而非局限本公开。一些实施例中，在之前工艺扩大凹陷500的宽度520的情况下，可调整籽晶层厚度以复原凹陷500的预定宽度522。厚度调整亦可减缓凹陷500中顶角与底角的圆润化现象。
在步骤150的第三子步骤中，形成外延层于籽晶层上，以填入凹陷500。在一些实施例中，外延层为硅锗，且其成长的温度T3可介于约550℃至约700℃之间。如前所述，温度T3低于温度T2与T1。举例来说(但不限于下述例子)，用于成长硅锗外延层的前驱物气体可包含下述物质(i)与(ii)的组合：(i)硅烷、硅乙烷、二氯硅烷、锗烷、或盐酸；以及(ii)氢气、氮气、或氩气。
在一些实施例中，硅锗外延层沿着厚度方向的锗浓度(原子％)可为定值，其介于约20原子％至约40原子％之间。在一些实施例中，硅锗外延层可包含第一子层与第二子层，第一子层的锗浓度为约5原子％，而第二子层沿着硅锗外延层的厚度方向的锗浓度介于约20原子％至约40原子％之间。第一子层的厚度可介于约至约之间。
如图7所示，硅锗外延层700成长于图6中的凹陷500中。硅锗外延层700成长于籽晶层上。此外，硅锗外延层700不会形成于盖层420上。举例来说，硅锗外延层700不会成长于氧化硅或氮化硅上。在一些实施例中，在成长硅锗外延层700后的凹陷500其侧壁，可实质上垂直于凹陷500的下表面。举例来说，凹陷500的下表面与侧壁之间的角度，可介于约90°至100°之间。举例来说(但不限于下述例子)，掺杂碳的硅外延可成长于p型区上的硅籽晶层上，以用于形成n型全应变沟道。在一些实施例中，后续的化学机械平坦化工艺可平坦化硅锗外延层700与硅外延层410。在化学机械平坦化工艺中，可移除盖层420、部分的硅锗外延层700、与部分的硅外延层410，如图8所示。
在一些实施例中，上述步骤150的子步骤可成功地进行，而不需破真空。举例来说，可在单一大型主机的不同工艺腔室中进行每一子步骤。换言之，例示性方法100的步骤150为临场工艺。
如图1所示的一些实施例中，例示性方法100的步骤160可蚀刻图8中的部分堆叠800以形成鳍状物，其可包含n型区320组成的底部、硅外延层510组成的中间部、与籽晶层及硅锗外延层700组成的顶部。在一些实施例中，鳍状物亦可包含p型区400组成的底部，与硅外延层410组成的顶部。
举例来说(但不限于下述例子)，鳍状物的形成工艺可先沉积硅层810于硅锗外延层700与硅外延层410的平坦化表面上。在一些实施例中，硅层810的厚度可介于约至约之间(如)，且其成长方法可与用以成长硅外延层410的方法类似。接着可沉积氧化物层820与氮化物层830于硅层810上。硅层810、氮化物层820、与氮化物层830在后续的蚀刻工艺中，可保护硅锗外延层700与硅外延层410。光刻可定义鳍状的尺寸与鳍状物之间的空间(间距)。举例来说，可涂布光致抗蚀剂层于氮化物层上。接着可依据所需图案曝光及显影光致抗蚀剂。可进行湿式清洁以移除光致抗蚀剂的未曝光区，并保留显影光致抗蚀剂的所需图案于氮化物层830上。举例来说，所需图案可为决定所需鳍状物间距(鳍状物之间的所需距离)及鳍状物长度的开口。光致抗蚀剂可作为蚀刻掩模，因此可移除光致抗蚀剂未掩模的堆叠材料。
举例来说，干蚀刻工艺可自堆叠800移除图案化光致抗蚀剂未覆盖的材料。举例来说(但不限于下述例子)，干蚀刻工艺可包含多个步骤，且每一步骤具有不同的蚀刻化学品，端视欲蚀刻的材料而定。在蚀刻工艺后，可采用湿式清洁工艺移除显影的光致抗蚀剂。在一些实施例中，形成的鳍状物900与910如图9所示。图9中所示的鳍状物数目仅用以举例而非局限本公开。如此一来，鳍状物的数目可更少或更多，端视鳍状物间距与每一鳍状物所需的宽度而定。在一些实施例中，鳍状物900可包含n型区320的底部、硅外延层510的中间部、以及籽晶层与硅锗外延层700的顶部。鳍状物910可包含p型区400的底部与硅外延层410的顶部。
在一些实施例中，可沉积氮化物衬垫920于鳍状物900与910上，以覆盖鳍状物900与910的侧壁及p型区320与n型区400的水平表面。举例来说，氮化物衬垫920可为氮化硅。在一些实施例中，氮化物衬垫920可在后续工艺中，提供结构支撑至鳍状物900与910。在一些实施例中，介电层1000可沉积于鳍状物900与910上，以填入鳍状物之间的空间，如图10所示。举例来说，介电层1000可为浅沟槽隔离如氧化硅、氮化硅、氮氧化硅、掺杂氟的硅酸盐玻璃、低介电常数介电材料、或具有适当填充性质的的其他合适绝缘材料。此外，介电层可包含多层结构，比如具有一或多层的介电层。在一些实施例中，介电层的沉积方法可为化学气相沉积、等离子体增强化学气相沉积、或可流动的化学气相沉积。
在一些实施例中，化学机械平坦化工艺可移除鳍状物900与910上的部分介电层1000。在一些实施例中，化学机械平坦化工艺可停止于氮化物衬垫920上。后续的回蚀刻工艺可使介电层1000凹陷至n型区320与p型区400的高度，如图11所示。在前述的回蚀刻步骤中，可移除氮化物层830、氧化物层820、与硅层810。此外，亦可使氮化物衬垫920凹陷至介电层1000的高度。
如上所述，例示性的方法100可用以形成n型的完全应变沟道。举例来说，在步骤110中形成p型的掺杂区，以及在步骤150中成长掺杂碳的硅于硅籽晶层上以作为外延层，即可形成n型的完全应变沟道。
本公开关于p型或n型完全应变沟道的例示性制作方法，其可减少沟道区中的外延成长缺陷如堆叠错误。此外，例示性的制作方法可减少沟道区中的结构变形，比如因工艺产生的侧壁渐缩。在一些实施例中，例示性的工艺包括(i)两次或多次搭配三氟化氮与氨等离子体的表面预清洁处理循环，接着进行热处理；(ii)预烘烤(回火)；以及(iii)搭配硅籽晶层、硅锗籽晶层、或上述的组合外延成长硅锗，或搭配硅籽晶层的外延成长掺杂碳的硅。在一些实施例中，形成的鳍状物可包含具有掺杂区的底部、具有硅外延层的中间部、以及具有籽晶及外延层的顶部。
在一些实施例中，半导体结构的形成方法包括：提供掺杂区于基板的顶部上，以及成长第一外延层于掺杂区上。接着形成凹陷于第一外延层中，且凹陷对准掺杂区。形成凹陷的步骤包括部分蚀刻第一外延层。进行一或多道的表面预清洁处理循环。每一表面预清洁处理循环包括：暴露凹陷至等离子体；以及进行回火。形成第二外延层于凹陷中，包括：在第一温度下进行预烘烤；在第二温度下形成籽晶层于凹陷中；以及在第三温度下形成第二外延层于籽晶层上，以填满凹陷。
在一些实施例中，上述方法还包括：将光致抗蚀剂置于第二外延层上；形成至少两个开口于光致抗蚀剂中，以露出第二外延层的至少两个个别部分；以及形成鳍状物，其中形成鳍状物的步骤包括：蚀刻穿过光致抗蚀剂层中的至少两个开口、籽晶层、第一外延层、与部分的掺杂区；以及形成介电层于鳍状物之间。
在一些实施例中，上述方法的鳍状物包括具有掺杂区的底部、具有第一外延层的中间部、以及具有籽晶层与第二外延层的顶部。
在一些实施例中，上述方法在形成第二外延层之后，凹陷的侧壁角度介于90°至100°之间。
在一些实施例中，上述方法的掺杂区包含n型材料。
在一些实施例中，上述方法的等离子体包含三氟化氮、氨、与钝气。
在一些实施例中，上述方法的籽晶层包含硅、掺杂碳的硅、硅锗、或上述的组合，且籽晶层的厚度介于至之间。
在一些实施例中，上述方法的第一温度介于650℃至1500℃之间，且第一温度高于第二温度与第三温度。
在一些实施例中，第二温度介于600℃至750℃之间，且第三温度介于500℃至700℃之间。
在一些实施例中，上述方法的第一外延层包含硅，且第二外延层包含硅锗。
在一些实施例中，半导体结构的形成方法包括：形成n型区于基板的顶部上，以及成长硅外延层于n型区上。形成介电层于硅外延层上。形成开口于介电层中，其对准n型区以露出硅外延层。此外，经由开口，部分地蚀刻硅外延层以形成凹陷。进行预清洁处理循环，以及形成外延堆叠于凹陷中，其中形成外延堆叠的步骤包括：进行预烘烤，形成籽晶层于凹陷中，以及形成外延层于籽晶层上，以填满凹陷。
在一些实施例中，上述方法的预清洁处理循环包括：将凹陷暴露至等离子体；以及进行回火。
在一些实施例中，上述方法还包括：形成鳍状物，其中形成鳍状物的步骤包括：沉积光致抗蚀剂于硅外延层上；形成至少两个开口于光致抗蚀剂中，以露出外延层的至少两个个别部分；蚀刻穿过光致抗蚀剂层中的至少两个开口，以移除外延层、籽晶层、硅外延层、与部分的n型区；以及形成介电层于鳍状物之间。
在一些实施例中，上述方法的外延层为硅锗。
在一些实施例中，上述方法的籽晶层包括硅、硅锗、掺杂碳的硅、或上述的组合。
在一些实施例中，上述方法的等离子体包括三氟化氮、氨、与钝气。
在一些实施例中，上述方法的回火的温度介于60℃至200℃之间，且压力介于0.2Torr至1Torr之间。
在一些实施例中，半导体结构包括：鳍状物位于基板上，且鳍状物包括：n型掺杂区位于基板上；硅外延层位于n型掺杂区上；以及外延堆叠位于硅外延层上。此外，衬垫物围绕鳍状物的n型掺杂区，而介电物围绕衬垫物。
在一些实施例中，上述半导体结构的外延堆叠包含第一子层与第二子层，第一子层的锗浓度为约5原子％，而第二子层的锗浓度介于20原子％至40原子％之间。
在一些实施例中，上述半导体结构的硅外延层厚度介于至之间。
上述实施例的特征有利于本领域技术人员理解本公开实施例。本领域技术人员应理解可采用本公开作基础，设计并变化其他工艺与结构以完成上述实施例的相同目的及/或相同优点。本领域技术人员亦应理解，这些等效置换并未脱离本公开构思与范畴，并可在未脱离本公开的构思与范畴的前提下进行改变、替换、或更动。

Claims (1)

1.一种半导体结构的形成方法，包括：
提供一掺杂区于一基板的顶部上；
成长一第一外延层于该掺杂区上；
形成一凹陷于该第一外延层中，且该凹陷对准该掺杂区，其中形成该凹陷的步骤包括部分蚀刻该第一外延层；
进行一或多道的表面预清洁处理循环，其中每一表面预清洁处理循环包括：
暴露该凹陷至一等离子体；以及
进行一回火；以及
形成一第二外延层于该凹陷中，其中形成该第二外延层的步骤包括：
在一第一温度下进行预烘烤；
在一第二温度下形成一籽晶层于该凹陷中；以及
在一第三温度下形成该第二外延层于该籽晶层上，以填满该凹陷。
CN201711092274.8A 2017-09-28 2017-11-08 半导体结构的形成方法 Pending CN109585291A (zh)

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