CN109582491B

CN109582491B - Read data error handling based on machine learning

Info

Publication number: CN109582491B
Application number: CN201710957814.8A
Authority: CN
Inventors: 薛立成
Original assignee: Beijing Starblaze Technology Co ltd
Current assignee: Beijing Starblaze Technology Co ltd
Priority date: 2017-09-28
Filing date: 2017-10-16
Publication date: 2023-10-10
Anticipated expiration: 2037-10-16
Also published as: CN109582491A; CN117215824A

Abstract

The application provides read data error handling based on machine learning. The data recovery method comprises the following steps: receiving a read access command sent by a host; issuing a read command to the nonvolatile memory according to the read access command; receiving read data provided by a nonvolatile memory; performing error correction on the read data; if the error correction is successful, the corrected read data is sent to the host; and training the neural network with the scenario in which the read command is applied and the read command parameters indicated by the read command.

Description

Read data error handling based on machine learning

Technical Field

The present application relates to the field of memory, and in particular to error handling for reading data from an NVM chip.

Background

Flash memories store information by maintaining an amount of charge in a memory cell. The amount of charge in the memory cell determines the read voltage of the memory cell. When the flash memory data is read, the read voltage of the memory cell is compared with the threshold voltage to identify the information stored in the memory cell. Phase change memories, resistive random access memories, magnetic spin memories, DRAMs each utilize memory cells based on different principles to store information.

The storage medium is generally not entirely reliable. The amount of charge in a memory cell is affected by various factors such as the quality, lifetime, time, etc. of the memory cell, and the non-uniformity of signal transmission paths from a plurality of memory cells to a sense amplifier, which results in deviation of data read from the memory cell from written data, and thus information originally written to the memory cell cannot be correctly embodied.

In the prior art, some means are used to prevent or cope with the problem that the read data cannot correctly represent the written data due to the change of the charge amount of the memory cell, for example, in US patent No. 9070454B1, a threshold voltage (a threshold voltage or a decision voltage used when reading data from the memory cell or writing data into the memory cell) is calculated according to the number of erasing times, the holding time, and other factors of the memory cell, and the data is written into the memory cell using the calculated threshold voltage. The threshold voltages may include a read threshold for a read operation and a write threshold for a write operation.

In a flash memory chip, the threshold voltage used in a read operation is selected by indicating different parameters for the read operation. The data read from the memory cells will have different results by read operations with different threshold voltages. Some results have a lower Bit Error rate (percentage of erroneous bits to the total number of bits transmitted) and some results have a higher Bit Error rate. In combination with the use of ECC (Error Correction Code ) techniques, the probability of a read result with a lower bit error rate being corrected by the ECC technique is higher, thus coping with errors encountered in the read operation by trying different parameters. The parameters may be incorporated to be provided to the flash memory chip in a read operation or set in the flash memory chip for use in a read operation, and the set parameters are used when the flash memory chip processes the read operation.

The error correction capability of the ECC technique is limited, for example, to correct 40-bit errors in 1 kbyte data (referred to as an ECC data frame) at most. When the number of error bits of the stored data exceeds the error correction capability of the ECC unit, a read operation with other parameters needs to be attempted in hopes of obtaining read data with a smaller number of error bits to meet the error correction capability requirement of the ECC unit.

Data is typically stored and read on a storage medium on a page basis, while data is erased on a block basis. Typically, a block contains multiple pages, with pages on the storage medium (called physical pages) having a fixed size, e.g., 17664 bytes, although physical pages may have other sizes. In reading or writing data, the same threshold voltage is typically set for all memory cells of each page.

Disclosure of Invention

The read operation has a plurality of parameters, each indicating a different read threshold voltage. In error handling of read operations, it is desirable to increase the efficiency of selecting read operation parameters to speed up the data read process and reduce the number of repeated reads of data from the NVM chip to increase the effective bandwidth of the read data.

The application aims to provide a data recovery method and solid-state storage equipment so as to improve the accuracy of data read by a read command.

According to a first aspect of the present application, there is provided a first data recovery method according to the first aspect of the present application, comprising: receiving a read access command sent by a host; issuing a read command to the nonvolatile memory according to the read access command; receiving read data provided by a nonvolatile memory; performing error correction on the read data; if the error correction is successful, the corrected read data is sent to the host; and training the neural network with the scenario in which the read command is applied and the read command parameters indicated by the read command.

According to a first data recovery method of the first aspect of the present application, there is provided a second data recovery method according to the first aspect of the present application, wherein a scene in which a read command is applied is taken as an input of the neural network, and a read command parameter indicated by the read command is taken as an output of the neural network.

According to the first or second data recovery method of the first aspect of the present application, there is provided a third data recovery method according to the first aspect of the present application, wherein the neural network classifies a scene to which the read command is applied.

According to a third data recovery method of the first aspect of the present application, there is provided a fourth data recovery method according to the first aspect of the present application, wherein the category of the scene corresponds to a read command parameter under which data that can be successfully error-corrected can be read out.

According to a third data recovery method of the first aspect of the present application, there is provided a fifth data recovery method according to the first aspect of the present application, wherein the category of the scene corresponds to a read command parameter capable of reading out data having a probability of being successfully error-corrected larger than the first value under the scene.

According to a third data recovery method of the first aspect of the present application, there is provided the sixth data recovery method according to the first aspect of the present application, wherein the category of the scene corresponds to a read command parameter capable of reading out data having a number of error bits lower than the second value in the scene.

According to a third data recovery method of the first aspect of the present application, there is provided a seventh data recovery method according to the first aspect of the present application, wherein the category of the scene corresponds to a read command parameter sequence.

According to a seventh data recovery method of the first aspect of the present application, there is provided the eighth data recovery method of the first aspect of the present application, wherein a probability that a combination of data read from the nonvolatile memory using a read command sequence generated from the read command parameter sequence can be successfully error corrected or successfully error corrected is greater than a third value.

According to a seventh data recovery method of the first aspect of the present application, there is provided the ninth data recovery method of the first aspect of the present application, wherein a probability that a data combination read from the nonvolatile memory by soft decoding can be successfully error-corrected or successfully error-corrected using a read command sequence generated from the read command parameter sequence is larger than a fourth value.

According to a first to ninth data recovery methods of the first aspect of the present application, there is provided the tenth data recovery method according to the first aspect of the present application, wherein the attribute of the scene to which the read command is applied includes a logical unit number, a physical block, a physical page type, a time interval since data on the physical block was written to, the number of times the physical block was erased, the number of times the physical block was read, and/or whether the physical block was completely written.

According to a tenth data recovery method of the first aspect of the present application, there is provided the eleventh data recovery method according to the first aspect of the present application, wherein the time interval from when the data on the physical block was written to so far includes or does not include the time when the solid-state storage device is in the power-down state.

According to a tenth data recovery method of the first aspect of the present application, there is provided the twelfth data recovery method according to the first aspect of the present application, wherein the attribute of the scene includes an error rate of the physical block.

According to a first data recovery method of a first aspect of the present application, there is provided a thirteenth data recovery method according to the first aspect of the present application, wherein the attribute of the scene includes a physical page accessed by the read command and a read command parameter corresponding to successful error correction of data read from the physical page last time.

According to a first to thirteenth data recovery methods of the first aspect of the present application, there is provided a fourteenth data recovery method according to the first aspect of the present application, wherein a re-read command is generated to re-acquire the read data in response to an error correction failure.

According to a fourteenth data recovery method of the first aspect of the present application, there is provided the fifteenth data recovery method according to the first aspect of the present application, wherein the neural network is trained with the read command parameter corresponding to the re-read command and the scene where the re-read command is applied in response to successful error correction of the read data of the re-read command.

According to a fifteenth data recovery method of the first aspect of the present application, there is provided the sixteenth data recovery method according to the first aspect of the present application, wherein the neural network is trained with a read command parameter corresponding to the read command and a scene in which the read command is applied in response to an error correction failure for the read data.

According to a first to sixteenth data recovery method of the first aspect of the present application, there is provided a seventeenth data recovery method according to the first aspect of the present application, wherein parameters of the neural network are set in response to a command of the host, the parameters of the neural network being stored in the nonvolatile memory or provided by the host.

According to first to seventeenth data recovery methods of the first aspect of the present application, there is provided the eighteenth data recovery method according to the first aspect of the present application, wherein parameters of the neural network are acquired in response to a command of the host, and the parameters of the neural network are provided to the host or stored in the nonvolatile memory.

According to a first to eighteenth data recovery method of the first aspect of the present application, there is provided a nineteenth data recovery method according to the first aspect of the present application, wherein training results of the neural network are recorded in a memory, a dynamic random access memory, or a nonvolatile memory.

According to a first to nineteenth data recovery methods of the first aspect of the present application, there is provided a twentieth data recovery method according to the first aspect of the present application, wherein a plurality of neural networks, each serving one or more logical unit numbers or one or more physical blocks of the solid state storage device, are trained.

According to a twentieth data recovery method of the first aspect of the present application, there is provided the twentieth data recovery method according to the first aspect of the present application, wherein the read command parameter corresponding to the read command and the scene in which the read command is applied are provided to the corresponding neural network according to the logical unit number or the physical block indicated in the scene in which the read command is applied.

According to a fourteenth or fifteenth data recovery method of the first aspect of the present application, there is provided the twentieth data recovery method according to the first aspect of the present application, wherein in response to an error correction failure, the neural network infers a read command parameter corresponding to a scene from which a received read command is applied, and generates a re-read command, and transmits the re-read command to the nonvolatile memory.

According to a twenty-third data recovery method of the first aspect of the present application, there is provided the twenty-third data recovery method of the first aspect of the present application, wherein read data of a read-over command is received from a nonvolatile memory; performing error correction on read data of the re-read command; if the error correction fails, repeatedly generating a rereading command until the error correction is successful; and if the error correction is successful, sending the read data of the corrected re-reading command to the host.

According to a first to twenty-third data recovery methods of the first aspect of the present application, there is provided a twenty-fourth data recovery method according to the first aspect of the present application, wherein in response to an error correction failure, a re-read command is generated according to a scene to which the corresponding read command is applied, and is transmitted to the media interface controller.

According to a twenty-fourth data recovery method of the first aspect of the present application, there is provided the twenty-fifth data recovery method of the first aspect of the present application, wherein in response to an error correction failure, a re-read command is generated according to a scene in which the corresponding read command is applied and a read command parameter, and is transmitted to the media interface controller.

According to a first to twenty-fifth data recovery method of the first aspect of the present application, there is provided a twenty-sixth data recovery method according to the first aspect of the present application, wherein, in response to a first failure of error correction of read data, a first re-read command generated by a neural network is employed; and in response to a subsequent failure of the error correction, generating a second read command, a read command parameter in the second read command indicating the second read command, and sending the second read command to the non-volatile memory.

According to a twenty-sixth data recovery method of the first aspect of the present application, there is provided the twenty-seventh data recovery method of the first aspect of the present application, wherein a read command parameter of the second read command is determined by counting the number of bits having the first value and/or the number of bits having the second value in the read data for generating the second read command.

According to a twenty-seventh data recovery method of the first aspect of the present application, there is provided the twenty-eighth data recovery method of the first aspect of the present application, wherein the adjustment direction and the adjustment amplitude of the read threshold voltage of the second read command corresponding to the read command parameter are determined depending on the number of bits having the first value and/or the number of bits having the second value in the read data.

According to a twenty-eighth data recovery method of the first aspect of the present application, there is provided the twenty-ninth data recovery method according to the first aspect of the present application, wherein if the number of bits having the first value in the data read out from the physical page of the first type, which corresponds to the first read threshold voltage, is greater than the first number threshold value, the read command parameter corresponding to the first read threshold voltage used by the second re-read command is adjusted in a direction to decrease the number of bits having the first value.

According to a first to twenty-fifth data recovery method of the first aspect of the present application, there is provided the thirty-first data recovery method according to the first aspect of the present application, wherein, in response to a first failure of error correction of the read data, a third read command generated by the re-reading section is employed, the third read command indicating a read command parameter of the third read command; and generating a fourth read command using the neural network in response to a subsequent failure of the error correction.

According to a thirty-first data recovery method of the first aspect of the present application, there is provided the thirty-first data recovery method of the first aspect of the present application, wherein a read command parameter of the third read command is determined by counting the number of bits having the first value and/or the number of bits having the second value in the read data for generating the third read command.

According to a thirty-first data recovery method of a first aspect of the present application, there is provided the thirty-first data recovery method according to the first aspect of the present application, wherein the adjustment direction and the adjustment amplitude of the read threshold voltage corresponding to the read command parameter of the third read command are determined according to the number of bits having the first value and/or the number of bits having the second value in the read data.

According to a thirty-third data recovery method of the first aspect of the present application, there is provided the thirty-third data recovery method of the first aspect of the present application, wherein if the number of bits having the first value in the data read out from the physical page of the first type, which corresponds to the first read threshold voltage, is greater than the first number threshold value, the read command parameter corresponding to the first read threshold voltage used by the third read command is adjusted in a direction to decrease the number of bits having the first value.

According to the thirty-third data recovery method of the first aspect of the present application, there is provided the thirty-fourth data recovery method according to the first aspect of the present application, wherein the neural network infers a scene category that best matches a current scene from a scene to which the received read command is applied, and selects a read command parameter and/or a read command sequence according to the best matching scene category.

According to a first to thirty-third data recovery methods of the first aspect of the present application, there is provided the thirty-fifth data recovery method of the first aspect of the present application, wherein the neural network obtains a scene category that best matches a current scene according to a scene to which the read command is applied, generates a re-read command or a re-read command sequence according to the scene category, and transmits the re-read command or the re-read command sequence to the nonvolatile memory.

According to a first to thirty-third data recovery methods of the first aspect of the present application, there is provided a thirty-sixth data recovery method according to the first aspect of the present application, wherein the neural network obtains a scene category that best matches a current scene according to a scene to which the read command is applied, and generates a re-read command or a re-read command sequence according to the scene to which the read command is applied and a read command parameter of the current read command corresponding to an error correction failure.

According to a first to thirty-sixth data recovery method of the first aspect of the present application, there is provided a thirty-seventh data recovery method according to the first aspect of the present application, wherein a plurality of neural networks are trained, each neural network serving one or more logical unit numbers and/or one or more physical blocks of the solid state storage device; in response to the error correction failure, providing the current read command applied scene to the corresponding neural network according to the logical unit number and/or the physical block indicated in the read command applied scene to infer a read command parameter and/or a read command sequence suitable for the current read command applied scene.

According to a second aspect of the present application, there is provided a first solid-state storage device according to the second aspect of the present application, comprising a control unit and a non-volatile memory chip, the control unit being adapted to perform the data recovery method described above.

According to a third aspect of the present application, there is provided a first control unit according to the third aspect of the present application, comprising a command issue queue, a media interface controller, an error correction unit, an artificial intelligence unit, and a command completion queue; the command issuing queue is coupled with the medium interface controller, receives a read access command of the host computer and forwards the read access command to the medium interface controller; the medium interface controller sends a read command to the nonvolatile memory and receives read data of the nonvolatile memory; an error correction component coupled to the media interface controller, the error correction component performing error correction on the read data; the command completion queue is coupled with the error correction component, and responds to the success of error correction, the command completion queue receives the error corrected data sent by the error correction component and sends the error corrected data to the host; the artificial intelligence component is coupled to the error correction component, and the artificial intelligence component trains the neural network using the context in which the read command is applied and the read command parameters corresponding to the read command.

According to a first control component of a third aspect of the present application, there is provided a second control component according to the third aspect of the present application, wherein the artificial intelligence component is coupled with the media interface controller; in response to the error correction failure, the artificial intelligence component generates a re-read command and sends the re-read command to the media interface controller.

The beneficial effects achieved by the application are as follows:

(1) According to the embodiment of the application, the artificial intelligent component trains the neural network by utilizing the applied scene of the read command and the read command parameters, so that the read command parameters which are more matched are provided for the read command according to the training result, and the accuracy of the data read by the read command is improved.

(2) The embodiment of the application generates the reread command through the cooperation of the artificial intelligent component and the reread component, thereby improving the data processing speed.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to these drawings to those skilled in the art.

FIG. 1 is a schematic diagram of a solid state storage device according to a first embodiment of the present application;

FIG. 2 is a schematic diagram of a solid state storage device according to a second embodiment of the present application;

FIG. 3 is a prior art structure of a NAND flash memory;

fig. 4 is a graph of a read voltage distribution of a memory cell in one example.

Fig. 5 is a graph of a read voltage distribution of a memory cell in yet another example.

Fig. 6 is a graph of a read voltage distribution of a memory cell in yet another example.

Fig. 7 is a schematic diagram of a solid state storage device according to a third embodiment of the application.

Fig. 8 is a graph of a read voltage distribution of a memory cell of another example.

Fig. 9 is a correspondence of states of the memory cells of fig. 8 with stored bits.

Fig. 10 is a correspondence of three bits stored by a memory cell in one example to a physical page.

Fig. 11 is a correspondence between threshold values and states of memory cells in the embodiment shown in fig. 8.

Fig. 12 is a manner of adjusting the read threshold voltage corresponding to the physical page type in the embodiments shown in fig. 8-10.

Fig. 13 is a graph showing a read voltage distribution of a memory cell according to still another example.

Fig. 14 is a correspondence of states of the memory cells in fig. 13 with stored bits.

Fig. 15 is a correspondence relationship of three bits stored by a storage unit and a physical page in another example.

Fig. 16 is a correspondence of threshold values and states of memory cells of the embodiment shown in fig. 13.

Fig. 17 is a manner of adjusting the read threshold voltage corresponding to the physical page type in the embodiments shown in fig. 13-15.

Fig. 18 is a schematic diagram of a solid state storage device according to a fourth embodiment of the present application.

FIG. 19 is a schematic diagram of a solid state storage device processing read commands according to the embodiment of FIG. 18.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Example 1

FIG. 1 is a schematic diagram of a solid state storage device according to a first embodiment of the present application. The solid state storage device includes a control component and one or more NVM (non-volatile memory) chips coupled to the controller component. NVM chips are, for example, NAND flash memory, phase change memory, resistance change memory, magnetic spin memory. The control component is also coupled to the host in response to commands issued by the host to access the solid state storage device. The control component includes a command issue queue, a command completion queue, an ECC component, and a media interface controller.

The medium interface controller is coupled to the NVM chip and issues commands to the NVM chip in a manner conforming to an interface protocol of the NVM chip to operate the NVM chip and receive command execution results output from the NVM chip. Known NVM chip interface protocols include "Toggle", "ONFI", and the like.

As shown in fig. 1, a host issues a command (1) to access a solid state storage device to the solid state storage device. The command issuing queue is used for receiving and caching commands which are sent by the host and access the solid-state storage device. Commands issued by the host are processed and forwarded to the media interface controller (2). The media interface controller issues a command (3) to the NVM chip based on the command issued by the host. The media interface controller also obtains command processing results from the NVM chip (4). Taking a read command as an example, the data read from the NVM chip is provided to an ECC unit for error correction (5). The processed command is added to the command completion queue (6). By accessing the command completion queue, the host acquires the command processing result (7).

It will be appreciated that in order to use the ECC component to perform error correction on the read data, the data to be written is also error correction encoded (not shown in FIG. 1) with the ECC component when writing data to the NVM chip.

Error correction by the ECC component on data read from the NVM chip may be successful or may fail. In one embodiment, a command processing completion indication is added to the command completion queue even if the ECC component fails to correct errors in the read data. If an error correction failure of the data is identified from the command processing completion indication in the command completion queue, the host generates a re-read command (the re-read command indicates a different read command parameter than the read command that failed the error correction) in response to the error correction failure, and sends the re-read command to the command issuing queue of the solid state storage device. And repeating steps 1-7 to try again to read the data.

Typically, the host will attempt multiple or all of the re-read commands provided by the NVM chip. If all re-read commands are attempted, and the result of error correction success is still not obtained, then the data needs to be acquired by other error handling means (e.g., by RAID techniques). And when correct data with successful error correction is obtained by a certain re-read command, the attempt to other re-read commands is terminated.

Optionally, some NVM chips provide different forms of re-read commands. The function of the reread command is implemented, for example, by a combination of a Set Feature command and a read command. The read command parameters are set using the set feature command, and in the read command, the set read command parameters are used.

Still alternatively, the same read command parameters as the read command failing the error correction are indicated in the re-read command.

Obviously, the re-read process, controlled by the host, greatly increases the latency of command processing due to the multiple interactions of data and commands between the host and the solid state storage device.

Example two

Fig. 2 is a schematic diagram of a solid-state storage device according to a second embodiment of the present application. In this embodiment, the control component of the solid state storage device includes a command issue queue, a command completion queue, a media interface controller, an ECC component, and a reread component.

The rereading component is coupled to the ECC component and the media interface controller. In response to the ECC component indicating an error correction failure, the re-read component generates a re-read command to the media interface controller and indicates a read command parameter in the re-read command that is different from the read command that failed the error correction. Under control of the reread unit, multiple or all of the reread commands provided by the NVM chip are attempted.

Taking the solid-state storage device read command processing flow as an example, as shown in fig. 2, the host sends a read access command (1) to a command issuing queue of the solid-state storage device. The read access command issued by the host is forwarded to the media interface controller (2) after processing. The media interface controller issues a read command (3) to the NVM chip based on the read access command issued by the host. The media interface controller also obtains command processing results, i.e., read data (4) of the read command, from the NVM chip. The data read from the NVM chip is provided to an ECC unit for error correction (5). If the ECC means fails to correct errors in the read data, the information such as the read command or read command access address, the read data length, the read command parameters used by the read command, etc. is forwarded to the re-read means (6). The re-reading means generates a re-read command (optionally, a re-read command selects a read command parameter) and sends the re-read command to the media interface controller (7). The media interface controller issues a re-read command to the NVM chip based on the re-read command (8). The media interface controller also obtains the processing result of the re-read command from the NVM chip (9). The data read out by the re-read command is supplied to the ECC unit (10). If the ECC component fails to correct the read data of the re-read command, the process from step (6) to step (10) is initiated again by the re-read component. If the ECC component is successful in correcting errors in the read data, the processed command (and optionally the read data) is added to a command completion queue (11). By accessing the command completion queue, the host obtains command processing results (12).

In this embodiment, in the case of error correction failure of the ECC unit, the rereading unit controls to issue one or more rereading processes, so that interaction between the solid-state storage device and the host is reduced, and processing delay of a read command is reduced.

Example III

Fig. 3 shows a structure of a related art NAND flash memory. The flash memory block includes a plurality of word lines and bit lines. The word line is coupled to a plurality of transistors for storing information, each transistor providing a memory cell (Cn, cn-1, …, C1, C0) each capable of storing 1 bit or more of data. The plurality of memory cells in each word line provide one or more physical pages, with bits constituting one physical page stored in transistors coupled to the same word line.

FIG. 4 is a graph of a read voltage distribution of a memory cell. After the memory cell is programmed, a charge is stored in the memory cell depending on the programmed value. When reading a memory cell, different read voltages are obtained from memory cells storing different charges. Referring to fig. 4, a bell line L (0) is a read voltage distribution of a memory cell storing a "1" value, and a bell line L (1) is a read voltage distribution of a memory cell storing a "0" value. When the read threshold voltage Vt1 is used, the memory cell having a value of "1" to the left of the read threshold voltage Vt1 is correctly read, while the memory cell having a value of "0" to the right of the read threshold voltage Vt1 is also correctly read.

Fig. 5 is a graph of a read voltage distribution of a memory cell in yet another example. The read voltage distribution of the memory cell changes due to time, programming times, temperature, etc. The bell line L (0) is a read voltage distribution of a memory cell storing a value of "1", and the bell line L (1) is a read voltage distribution of a memory cell storing a value of "0". When the read threshold voltage Vt1 is used, the memory cell having the value of "0" at the left side of the read threshold voltage Vt1 is erroneously read as the value of "1", and the memory cell having the value of "0" at the right side of the read threshold voltage Vt1 is correctly read. If the read threshold voltage Vt2 is used, the memory cell having the "1" value on the left side of the read threshold voltage Vt2 is correctly read, and the memory cell having the "0" value on the right side of the read threshold voltage Vt2 is also correctly read. Thus, during the re-reading process, if the read threshold voltage Vt2 is indicated by the read command parameter, there is a higher probability of reading the correct data, or reading data with a lower error rate that can be successfully error corrected by the ECC component.

Fig. 7 is a schematic diagram of a solid state storage device according to a third embodiment of the application. In this embodiment, the control section of the solid state storage device includes a command issue queue, a command completion queue, a media interface controller, an ECC section, a re-reading section, a scrambling section (not shown in the figure), and a descrambling section. The rereading component is coupled to the ECC component and the media interface controller. A descrambling unit couples the ECC unit with the command completion queue. And descrambling the data subjected to error correction by the ECC component, and providing a descrambling result to a command completion queue.

In response to the ECC component indicating an error correction failure, the re-read component generates a re-read command to the media interface controller and indicates a different read command parameter in the re-read command. Under control of the reread unit, multiple or all of the reread commands provided by the NVM chip are attempted.

According to the embodiment of fig. 7, in response to the ECC unit failing to correct errors in the read data a plurality of times, the rereading unit initiates the process from step (6) to step (10) a plurality of times accordingly, and updates parameters of the read command (e.g., read command parameters corresponding to the read threshold voltage) in the generated rereading command. If the error correction of the read data by the ECC means is successful, the error corrected data is descrambled (11) by the descrambling means and the processed command (and optionally the descrambled data) is added to the command completion queue (11). By accessing the command completion queue, the host obtains command processing results (12).

In this embodiment, the data is scrambled by a scrambling component (not shown) before being written to the NVM chip. And after the data is read out from the NVM chip and error corrected, the data is descrambled by the descrambling unit in a manner inverse to the scrambling process.

The scrambling process is to randomize the data. For example, the specified randomization seed is operated on with the data to be written according to a specified algorithm (e.g., the randomization seed is used to generate an m-sequence and exclusive-or with the data to be written) to obtain the scrambled data. The data written to the NVM chip, by scrambling, has specified statistical properties, e.g., the number of bits having a "0" value is substantially the same as the number of bits having a "1" value, e.g., 50%, in the data read out in the same physical page, word line, or ECC data frame of the NVM chip. As an example, a physical page stores 16K bytes of data, and is scrambled and written to the physical page, with about 8K x 8 bits having a "0" value and about 8K x 8 bits having a "1" value.

The descrambling process is the inverse of the randomization process described above to obtain the pre-scrambling data.

Optionally, as an embodiment, the data to be written to the NVM chip is scrambled and then error correction coded. Accordingly, for the data read out from the NVM chip, error correction decoding is first performed, and then descrambling is performed.

Optionally, as another embodiment, the data to be written to the NVM chip is scrambled after being error correction coded. Accordingly, the data read from the NVM chip is descrambled before error correction decoding.

Still alternatively, the scrambling and descrambling process is implemented by the media interface controller.

In this embodiment, the data is read with the standard parameters of the read command (e.g., vt1 in fig. 5 is the read threshold voltage), and in response to the ECC unit indicating that the error correction of the read data fails, the re-reading unit counts the data before the error correction or the error corrected data by the ECC unit, and identifies the number of bits having a value of "0" and the number of bits having a value of "1" therein.

In the example of fig. 7, after the scrambled data is written in the memory cell, the data is read with the standard parameters of the read command (e.g., vt1 in fig. 5 is the read threshold voltage). In the read data, if the ratio of the number of bits having a value of "0" to the number of bits having a value of "1" is significantly lower than 1, it can be determined that the read voltage distribution in the memory cell has shifted as shown in fig. 5 (the read voltage distribution of the memory cell is shifted to the left as a whole). Accordingly, by shifting the read threshold voltage to the left (e.g., modifying the read threshold voltage from Vt1 to Vt 2), there will be an opportunity to have the ratio of bits in the read data having a "0" value to the number of bits having a "1" value approaching 1.

Similarly, the data is read with the standard parameters of the read command (e.g., vt1 in FIG. 5 is the read threshold voltage). In the read data, if the ratio of the number of bits having a value of "0" to the number of bits having a value of "1" is significantly larger than 1, it can be determined that the read voltage distribution in the memory cell has shifted to the right (the read voltage distribution of the memory cell has shifted to the right as a whole). Accordingly, by shifting the read threshold voltage to the right (e.g., modifying the read threshold voltage from Vt1 to a value greater than Vt 1), there will be an opportunity to have the ratio of bits in the read data having a value of "0" to the number of bits having a value of "1" approach 1.

Thus, according to the embodiment of fig. 7, the re-reading unit identifies the offset direction of the read voltage distribution of the corresponding memory cell according to the bit number statistics of the "0" value and/or the "1" value in the read data, further determines the direction of updating the read threshold voltage, generates the re-reading command, and makes the read command parameter of the re-reading command indicate the updated read threshold voltage, so that the ratio of the bit number having the "0" value to the bit number having the "1" value in the read data corresponding to the re-reading command is expected to be close to 1, so as to facilitate the ECC unit to have a higher probability of successful error correction.

It will be appreciated that in fig. 5, the state of the readout voltage distribution corresponding to Zhong Xingxian L (0) may be defined as storing the value "0", while the state of the readout voltage distribution corresponding to Zhong Xingxian L (1) may be defined as storing the value "1", as shown in fig. 6. Thus, in response to the ECC unit recognizing an error correction failure, the rereading unit recognizes that the ratio of the bit having a value of "0" to the number of bits having a value of "1" in the read data is significantly lower than 1 (e.g., lower than 0.96), and in the generated reread command, indicates that the read threshold voltage is shifted rightward with respect to the read threshold voltage corresponding to the preceding read command causing the error correction failure. If the rereading section recognizes that the ratio of the number of bits having a value of "0" to the number of bits having a value of "1" is significantly greater than 1 (for example, higher than 1.04), in the read data, the read threshold voltage is shifted leftward with respect to the read threshold voltage corresponding to the preceding read command causing error correction failure in the generated rereading command.

Further, if error correction of the read data of the re-read command fails again, the re-read means may generate the re-read command again according to the ratio of the number of bits having a value of "0" to the number of bits having a value of "1" in the read data, and indicate the updated read threshold voltage in the re-read command.

In an alternative embodiment, the re-reading means determines not only the direction of change (increase or decrease) of the updated read threshold voltage corresponding to the re-reading command with respect to the read threshold voltage of the preceding read command, but also the magnitude of change of the updated read threshold voltage with respect to the read threshold voltage of the preceding read command, depending on the ratio of the number of bits having a value of "0" to the number of bits having a value of "1" in the read data. For example, the farther from 1 the ratio of the number of bits having a value of "0" to the number of bits having a value of "1" in the read data, the larger the magnitude of change in the updated read threshold voltage with respect to the read threshold voltage of the preceding read command. Optionally, a mapping relationship of the ratio of the number of bits having a value of "0" to the number of bits having a value of "1" in the read data to the magnitude (and direction) of change of the updated read threshold voltage with respect to the read threshold voltage of the preceding read command is established by a look-up table or a function obtained by fitting. The mapping relationship can be obtained in a laboratory through a characteristic experiment on the memory device.

Still alternatively, the re-reading section changes the readout threshold voltage in units of unit steps, and determines the adjustment direction (increase or decrease) of the readout threshold voltage in proportion to the number of bits having a value of "0" to the number of bits having a value of "1" in the readout data.

Alternatively, in the case where the amount of read data is known (e.g., physical page size, ECC data frame size), the rereading section counts the number of bits having a value of "0" and/or the number of bits having a value of "1" in the read data, and determines the adjustment direction and/or the adjustment amplitude of the read threshold voltage in accordance with the respective numbers.

Optionally, in response to an error correction failure of the read data of the preceding read command, the rereading section generates a reread command that accesses the same address as the preceding read command. Still alternatively, since the NVM chips of solid state storage devices are generally in a similar operating environment (temperature, number of erasures, etc.), it is advantageous for the reread component to apply the read command parameters used by the reread command (e.g., read threshold voltage) to read commands that access other addresses of the NVM chips. Optionally, the re-reading component instructs the media interface controller to update default read command parameters such that the general read commands issued by the media interface controller all use the default read command parameters of the re-reading component. Further, after the re-reading unit generates the re-reading command, the error correction result of the ECC unit is tracked, and a read command parameter for successful error correction is recorded, and the media interface controller is instructed to use the read command parameter for a general read command.

In an alternative embodiment, the data to be written to the NVM chip is first scrambled and then error correction coded in response to a command from the host to write the data to the solid-state storage device. And the data read from the NVM chip is scrambled data. The re-reading section recognizes (before error correction decoding) the ratio of the number of bits having a value of "0" to the number of bits having a value of "1" in the read data, generates a re-read command, and indicates the updated read threshold voltage in the re-read command. Alternatively, a threshold value, such as 1% or 2%, is provided for the ratio of the number of bits having a value of "0" to the number of bits having a value of "1". If the ratio is larger than the threshold value, the probability that the ECC component fails to correct the read data errors is estimated to be larger, the rereading component generates a rereading command and does not send the read data to the ECC component so as to omit an error correction process; if the ratio is not greater than the threshold, the re-reading part does not generate a re-reading command, and sends the read data to the ECC part for error correction, and only after error correction fails, the ratio of the number of bits with a value of '0' to the number of bits with a value of '1' in the read data statistics data after or before error correction is again performed, and the re-reading command is generated. Alternatively, in the case where the amount of read data is known, the re-reading section counts the number of bits having a value of "0" and/or the number of bits having a value of "1" in the read data, and determines the adjustment direction and/or the adjustment amplitude of the read threshold voltage in accordance with the respective number.

Still alternatively, the re-reading section counts the number of bits having a value of "0" and the number of bits having a value of "1" in the read data (before error correction decoding) concurrently with the error correction operation of the ECC section on the read data to reduce the processing delay. If the ECC component indicates that error correction was successful, then the correct data (after descrambling) is provided to the host as a response to the read command. If the ECC unit indicates error correction failure, the re-reading unit generates a re-reading command based on statistics of the number of bits having a value of "0" and the number of bits having a value of "1" in the read data. Still alternatively, in one example, the statistical delay of the number of bits having a value of "0" and the number of bits having a value of "1" in the read data by the re-read unit is much lower than the error correction delay of the read data by the ECC unit, and the re-read unit has generated a re-read command based on the statistical result before the ECC unit determines whether the error correction is successful or not. Optionally, the re-reading component temporarily stores the re-read command to wait for an error correction result of the ECC component, and issues the re-read command to the NVM chip in response to the error correction failure. Still alternatively, the re-read component issues the re-read command to the NVM chip without waiting for the error correction result of the ECC component, and discards the data read from the NVM chip by the re-read command when the ECC component subsequently indicates that the error correction was successful, and uses the data read from the NVM chip by the re-read command when the ECC component subsequently indicates that the error correction was failed.

Fig. 8 is a graph of a read voltage distribution of a memory cell of another example. In the example of fig. 8, the type of memory cell is TLC (Triple Level Cell, three-value memory cell). The read voltages of TLC memory cells are grouped into 8 different states, each corresponding to one of the 3-bit combinations, depending on the degree of programming. The 8 different states of the memory cell are indicated by "L0" through "L7," L0 "being the erased state of the memory cell and" L7 "being the fully programmed state of the memory cell. Referring to fig. 8, the read voltage of the memory cell monotonously varies from "L0" to "L7".

The states of the memory cells are distinguished by a plurality of read threshold voltages. With continued reference to FIG. 8, states "L3" and "L4" are distinguished by a read threshold voltage TH 1; distinguishing states "L1" and "L2" with a read threshold voltage TH 2; distinguishing states "L5" and "L6" with a read threshold voltage TH 3; distinguishing states "L0" and "L1" by a read threshold voltage TH 4; distinguishing states "L2" and "L3" with a read threshold voltage TH 5; distinguishing states "L4" and "L5" with a read threshold voltage TH 6; states "L6" and "L7" are distinguished by a read threshold voltage TH 7. As an example, a register is provided for each read threshold voltage to store the value of the read threshold voltage, and the value of the read threshold voltage is compared with the read voltage of the memory cell by a comparator to identify the state in which the memory cell is located.

The states of the memory cells are provided with codes, one for each state. Fig. 9 shows the correspondence of the states of the memory cells with the stored bits. For example, referring to fig. 9, state "L0" represents three-bit code "111", and state "L1" represents three-bit code "011". In fig. 9, only one bit is changed between two three-bit value codes corresponding to any adjacent two states, and the other two bits are identical.

Fig. 10 shows correspondence of three bits stored in the memory cell with physical pages. To improve parallelism of physical page accesses, three bits stored in each memory cell respectively belong to different physical pages. For example, in fig. 10, the memory cell stores three bits "101", respectively referred to as MSB (most significant bit ), CSB (middle significant bit, central Significant Bit) and LSB (least significant bit ) in order from left to right. The physical page constituted by MSBs of the plurality of memory cells is referred to as an MSB page, the physical page constituted by CSBs of the plurality of memory cells is referred to as a CSB page, and the physical page constituted by LSBs of the plurality of memory cells is referred to as an LSB page. The value of the bit corresponding to the physical page is read from the memory cell using the corresponding one or more read threshold voltages corresponding to the physical page.

The three bits stored by the TLC memory cell have different reliabilities. Referring back to fig. 8, to identify the LSB of the memory cell, only the read voltage of the memory cell needs to be compared with the read threshold voltage TH1, so that the LSB has a better reliability among the stored three bits. To identify the CSB of a memory cell, the read voltage of the memory cell needs to be compared to the read threshold voltages TH2 and/or TH 3. To identify the MSB of a memory cell, the read voltage of the memory cell needs to be compared with the read threshold voltages TH4, TH5, TH6, and/or TH 7.

Thus, the effect of changing the read threshold voltage of a memory cell on the result read from the memory cell depends on the state of the memory cell. For example, if the memory cell is in the "L7" state, the read result of the memory cell will be hardly affected by changing the value of the read threshold voltage TH 1. As another example, when the value of the read threshold voltage TH6 is changed and data is read, if the memory cell is not in the "L4" and "L5" states, the read result of the memory cell is hardly affected.

If the read result of a memory cell is less affected by a change in a read threshold voltage, an optimum value of the read threshold voltage for the memory cell cannot be found by changing the value of the read threshold voltage. In general, data written to a physical page is scrambled such that the data written to the physical page is a random number sequence such that the states stored by the memory cells are randomly distributed in physical space.

FIG. 11 shows the correspondence between the read threshold voltage and the state of the memory cell of the embodiment shown in FIG. 8. The word line of the NAND flash memory includes memory cells that provide a plurality of data constituting a physical page.

In fig. 11 (see also fig. 8), states "L3" and "L4" are distinguished by a read threshold voltage TH1, states "L1" and "L2" are distinguished by a read threshold voltage TH2, states "L5" and "L6" are distinguished by a read threshold voltage TH3, states "L0" and "L1" are distinguished by a read threshold voltage TH4, states "L2" and "L3" are distinguished by a read threshold voltage TH5, states "L4" and "L5" are distinguished by a read threshold voltage TH6, and states "L6" and "L7" are distinguished by a read threshold voltage TH 7.

When the memory cell type of the NVM chip of the solid state memory device is TLC, the re-read component (see also fig. 7) adjusts the read command parameters (read threshold voltages) accordingly depending on which type of physical page (e.g., MSB page, CSB page, or LBS page) the read data comes from.

Fig. 12 illustrates the manner in which the read threshold voltages corresponding to the physical page types are adjusted in accordance with the embodiments shown in fig. 8-10. Referring to fig. 12, if the read data comes from the LSB page, the rereading section (see also fig. 7) counts the number of bits having a value of "0" to the number of bits having a value of "1" (the ratio of the number of values or both) in the read data (before error correction or after error correction). As an example, if the ratio of the number of bits having a value of "1" to the number of bits having a value of "0" in the read data is significantly greater than 1 (e.g., greater than 1.04), a re-read command is generated, and in the generated re-read command, the read threshold voltage TH1 is instructed to be shifted leftward with respect to the read threshold voltage TH1 corresponding to the preceding read command. If the ratio of the number of bits having a value of "1" to the number of bits having a value of "0" in the read data is significantly less than 1 (e.g., less than 0.96), a re-read command is generated and the read threshold voltage TH1 is shifted rightward with respect to the read threshold voltage TH1 corresponding to the preceding read command indicated in the generated re-read command. It will be appreciated that the re-reading means may select the condition for which the re-reading command needs to be generated according to the bit having a value of "0" and the number of bits having a value of "1" in the read data, depending on the code rate of the error correction code, the operating state (number of erasures, temperature, data retention time, etc.) of the NVM chip. For example, for error correction codes of high code rate, a ratio of the number of bits having a value of "0" to the number of bits having a value of "1" in the read data is greater than 1.1 as a criterion of "significantly greater than 1". It will be still understood that moving the read threshold voltage to the "left" or to the "right" refers to adjusting the value of the read threshold voltage in the left or right direction on the horizontal axis shown in fig. 8 so that the number of bits having a value of "0" is substantially the same as the number of bits having a value of "1" in the data obtained by the re-read command.

With continued reference to FIG. 12, if the read data is from CSB page, the rereading component (see also FIG. 7) counts the number of bits in the read data (either before or after error correction) having a value of "0" versus the number of bits (the value of the number or ratio) having a value of "1". For example, if the ratio of the number of bits having a value of "1" to the number of bits having a value of "0" in the read data is significantly greater than 1, a re-read command is generated, and the read threshold voltage TH2 and the read threshold voltage TH3 corresponding to the previous read command are indicated in the generated re-read command, the read threshold voltage TH2 is shifted leftward and/or the read threshold voltage TH3 is shifted rightward. If the ratio of the number of bits having a value of "1" to the number of bits having a value of "0" in the read data is significantly smaller than 1, a re-read command is generated, and the read threshold voltages TH2 and TH3 corresponding to the previous read command are indicated in the generated re-read command to be shifted rightward by the read threshold voltage TH2 and/or leftward by the read threshold voltage TH3. According to an embodiment of the present application, in the re-read command, only one of the read threshold voltage TH2 and the read threshold voltage TH3, or both of the read threshold voltage TH2 and the read threshold voltage TH3 may be changed.

With continued reference to fig. 12, if the read data is from the MSB page, the rereading section (see also fig. 7) counts the number of bits having a value of "0" versus the number of bits having a value of "1" (the value of the number or ratio) in the read data (before or after error correction). For example, if the ratio of the number of bits having a value of "1" to the number of bits having a value of "0" in the read data is significantly greater than 1, a re-read command is generated, and the read threshold voltage TH4, the read threshold voltage TH5, the read threshold voltage TH6, and the read threshold voltage TH7 corresponding to the previous read command are indicated in the generated re-read command, the read threshold voltage TH4 is shifted leftward, the read threshold voltage TH7 is shifted rightward, the read threshold voltage TH5 is shifted rightward, and/or the read threshold voltage TH6 is shifted leftward. If the ratio of the number of bits having a value of "1" to the number of bits having a value of "0" in the read data is significantly smaller than 1, a re-read command is generated, and the read threshold voltage TH4, the read threshold voltage TH5, the read threshold voltage TH6, and the read threshold voltage TH7 corresponding to the preceding read command are indicated in the generated re-read command, the read threshold voltage TH4 is shifted rightward, the read threshold voltage TH7 is shifted leftward, the read threshold voltage TH5 is shifted leftward, and/or the read threshold voltage TH6 is shifted rightward. According to an embodiment of the present application, in the re-read command, only one of the readout threshold voltage TH4, the readout threshold voltage TH5, the readout threshold voltage TH6, and the readout threshold voltage TH7, or two or more of the readout threshold voltage TH4, the readout threshold voltage TH5, the readout threshold voltage TH6, and the readout threshold voltage TH7 may be changed.

Optionally, the rereading component further determines a direction and/or magnitude of shifting one or more read threshold voltages based on a number of bits having a value of "0" and/or a number of bits having a value of "1" in the read data.

Fig. 13 is a graph showing a read voltage distribution of a memory cell according to still another example. In the example of fig. 13, the type of memory cell is TLC (Triple Level Cell, three-value memory cell). The read voltages of TLC memory cells are grouped into 8 different states, each corresponding to one of the 3-bit combinations, depending on the degree of programming. The 8 different states of the memory cell are indicated by "L0" through "L7," L0 "being the erased state of the memory cell and" L7 "being the fully programmed state of the memory cell. From "L0" to "L7", the read voltage of the memory cell monotonously changes.

The states of the memory cells are distinguished by a plurality of read threshold voltages. With continued reference to FIG. 13, states "L3" and "L4" are distinguished by a read threshold voltage TH 1; distinguishing states "L1" and "L2" with a read threshold voltage TH 2; distinguishing states "L5" and "L6" with a read threshold voltage TH 3; distinguishing states "L0" and "L1" by a read threshold voltage TH 4; distinguishing states "L2" and "L3" with a read threshold voltage TH 5; distinguishing states "L4" and "L5" with a read threshold voltage TH 6; states "L6" and "L7" are distinguished by a read threshold voltage TH 7. The state of the memory cell is identified by comparing the value of the read threshold voltage with the read voltage of the memory cell.

The code is provided for each state of the memory cell, the code representing three bits stored by the TLC memory cell, each state corresponding to a three bit code. Fig. 14 shows the correspondence of the state of a memory cell with the stored bit encoding. For example, referring to fig. 14, state "L0" represents three-bit code "111", state "L1" represents three-bit code "110", and state "L2" represents three-bit code "100". In fig. 14, only one bit is changed between two three-bit codes corresponding to any adjacent two states, and the other two bits are identical.

Fig. 15 shows correspondence of three bits stored in the memory cell with physical pages. The three bits stored in each memory cell belong to different physical pages, respectively. For example, in fig. 15, the memory cell stores three bits "101", respectively referred to as MSB, CSB, and LSB in order from left to right. The physical page constituted by MSBs of the plurality of memory cells is referred to as an MSB page, the physical page constituted by CSBs of the plurality of memory cells is referred to as a CSB page, and the physical page constituted by LSBs of the plurality of memory cells is referred to as an LSB page. One or more read threshold voltages corresponding to a certain type of physical page are used to read the value of the bit corresponding to that type of physical page from the memory cell.

Referring back to fig. 13, to identify the LSB of a memory cell, the read voltage of the memory cell is compared to the read threshold voltages TH4 and/or TH 6. The LSB of the memory cell is "1" when the read voltage is less than the read threshold voltage TH4, and is "0" when the read voltage is between TH4 and TH6, and is "1" when the read voltage is greater than TH 6.

To identify the CSB of a memory cell, the read voltage of the memory cell needs to be compared to the read threshold voltages TH1, TH2, and/or TH 3. When the read voltage is less than TH2, the CSB of the memory cell is "1", when the read voltage is between TH2 and TH1, the CSB of the memory cell is "0", when the read voltage is between TH1 and TH3, the CSB of the memory cell is "1", and when the read voltage is greater than TH3, the CSB of the memory cell is "0".

To identify the MSB of a memory cell, the read voltage of the memory cell needs to be compared with read threshold voltages TH5 and/or TH 7. The MSB of the memory cell is "1" when the read voltage is smaller than TH5, the MSB of the memory cell is "0" when the read voltage is between TH5 and TH7, and the MSB of the memory cell is "1" when the read voltage is larger than TH 7.

Thus, changing the read threshold voltage of the memory cell, the effect on the result read from the memory cell depends on the state of the memory cell. For example, if the memory cell is in the "L7" state, the read result of the memory cell will be hardly affected by changing the value of the read threshold voltage TH 1. As another example, when the value of the read threshold voltage TH6 is changed and data is read, if the memory cell is not in the "L4" and "L5" states, the read result of the memory cell is hardly affected.

FIG. 16 illustrates a correspondence of a read threshold voltage to a state of a memory cell according to an embodiment of the present application.

In fig. 16 (see also fig. 13), states "L3" and "L4" are distinguished by a read threshold voltage TH1, states "L1" and "L2" are distinguished by a read threshold voltage TH2, states "L5" and "L6" are distinguished by a read threshold voltage TH3, states "L0" and "L1" are distinguished by a read threshold voltage TH4, states "L2" and "L3" are distinguished by a read threshold voltage TH5, states "L4" and "L5" are distinguished by a read threshold voltage TH6, and states "L6" and "L7" are distinguished by a read threshold voltage TH 7.

Fig. 17 illustrates the manner in which the read threshold voltages corresponding to the physical page types are adjusted for the embodiments shown in fig. 13-16. Referring to fig. 17, if the read data comes from the LSB page, the rereading section (also referring to fig. 7) counts the number of bits having a value of "0" and the number of bits having a value of "1" (the value of the number or the ratio) in the read data (before or after error correction). For example, if the ratio of the number of bits having a value of "1" to the number of bits having a value of "0" in the read data is significantly greater than 1 (e.g., greater than 1.04), a re-read command is generated and the read threshold voltage TH4 is shifted leftward (i.e., the value of the read threshold voltage TH4 is decreased), and/or the read threshold voltage TH6 is shifted rightward (i.e., the value of the read threshold voltage TH6 is increased) with respect to the read threshold voltage TH4 and the read threshold voltage TH6 corresponding to the preceding read command is indicated in the generated re-read command. If the ratio of the number of bits having a value of "1" to the number of bits having a value of "0" in the read data is significantly less than 1 (e.g., less than 0.96), a re-read command is generated and the read threshold voltage TH4 and the read threshold voltage TH6 corresponding to the previous read command are indicated in the generated re-read command to be shifted rightward by the read threshold voltage TH4 and/or leftward by the read threshold voltage TH6. It will be appreciated that the re-reading means may determine the condition for generating the re-reading command according to the code rate of the error correction code, the operating state of the NVM chip (number of erasures, temperature, data retention time, etc.), and according to the number of bits having a value of "0" and the number of bits having a value of "1" in the read data. For example, for error correction codes of high code rate, a ratio of the number of bits having a value of "0" to the number of bits having a value of "1" in the read data is greater than 1.1 as a criterion of "significantly greater than 1". It will be still understood that moving the read threshold voltage to the "left" or to the "right" refers to adjusting the value of the read threshold voltage in the left or right direction on the horizontal axis shown in fig. 13. The goal of adjusting the read threshold voltage is to make the number of bits with a value of "0" substantially the same as the number of bits with a value of "1" in the data obtained by the re-read command. According to an embodiment of the present application, in the re-read command, only one of the read threshold voltage TH4 and the read threshold voltage TH6, or both of the read threshold voltage TH4 and the read threshold voltage TH6 may be changed.

With continued reference to fig. 17, if the read data is from a CSB page, the rereading component (see also fig. 7) counts the number of bits in the read data (either before or after error correction) that have a value of "0" versus the number of bits (the value of the number or ratio) that have a value of "1". For example, if the ratio of the number of bits having a value of "1" to the number of bits having a value of "0" in the read data is significantly greater than 1, a re-read command is generated, and the read threshold voltage TH1, the read threshold voltage TH2, and the read threshold voltage TH3 corresponding to the previous read command are indicated in the generated re-read command, the read threshold voltage TH2 is shifted leftward, the read threshold voltage TH3 is shifted leftward, and/or the read threshold voltage TH1 is shifted rightward. If the ratio of the number of bits having a value of "1" to the number of bits having a value of "0" in the read data is significantly smaller than 1, a re-read command is generated, and the read threshold voltage TH1, the read threshold voltage TH2, and the read threshold voltage TH3 corresponding to the previous read command are indicated in the generated re-read command, the read threshold voltage TH2 is shifted rightward, the read threshold voltage TH3 is shifted rightward, and/or the read threshold voltage TH1 is shifted leftward. According to an embodiment of the present application, in the re-read command, only one of the read threshold voltage TH1, the read threshold voltage TH2, and the read threshold voltage TH3, or two or more of the read threshold voltage TH1, the read threshold voltage TH2, and the read threshold voltage TH3 may be changed.

With continued reference to fig. 17, if the read data is from the MSB page, the rereading section (see also fig. 7) counts the number of bits having a value of "0" versus the number of bits having a value of "1" (the value of the number or ratio) in the read data (before or after error correction). For example, if the ratio of the number of bits having a value of "1" to the number of bits having a value of "0" in the read data is significantly greater than 1, a re-read command is generated, and the read threshold voltage TH5 and the read threshold voltage TH7 corresponding to the previous read command are indicated in the generated re-read command, the read threshold voltage TH5 is shifted leftward and/or the read threshold voltage TH7 is shifted rightward. If the ratio of the number of bits having a value of "1" to the number of bits having a value of "0" in the read data is significantly smaller than 1, a re-read command is generated, and the read threshold voltage TH5 and the read threshold voltage TH7 corresponding to the previous read command are indicated in the generated re-read command to be shifted rightward by the read threshold voltage TH5 and/or leftward by the read threshold voltage TH7. According to an embodiment of the present application, in the re-read command, only one of the read threshold voltage TH5 and the read threshold voltage TH7, or both of the read threshold voltage TH5 and the read threshold voltage TH7 may be changed.

Example IV

Fig. 18 is a schematic diagram of a solid state storage device according to a fourth embodiment of the present application. The control components of the solid state storage device according to the embodiment of FIG. 18 include a command issue queue, a command completion queue, a media interface controller, an ECC component, and an AI (artificial intelligence ) component. The AI component is coupled to the ECC component. In response to the ECC component indicating that error correction was successful, the context in which the current read command was applied and the read command parameters of the current read command are provided to the AI component for training the AI component. For example, in an AI component implementing a deep learning algorithm, a neural network of the AI component is trained. Optionally, the AI component is further coupled to a DRAM external to the control component to buffer parameters of the neural network of the AI component. The AI component may be an IP core, a CPU core, or an ASIC chip coupled to the controller.

In this embodiment, the scenario in which the read command is applied is the input of the neural network, and the read command parameters (e.g., read threshold voltage, number of erroneous bits of read data, and/or sequence of read command parameters) are the expected outputs corresponding to the input of the neural network for supervision of the learning process. By training, the neural network classifies a plurality of scenes to which the read command is applied, the categories of the scenes correspond to read command parameters capable of reading out data that can be successfully error-corrected by the ECC unit under the scenes, correspond to read command parameters capable of reading out data that can be successfully error-corrected by the ECC unit under the scenes with a higher probability, correspond to read command parameters capable of reading out data with a lower number of error bits or below a threshold under the scenes, or correspond to a read command parameter sequence, wherein the data read out from the NVM chip using the read command sequence generated from the read command parameter sequence are combined, can be successfully error-corrected by the ECC unit with a higher probability and a fewer number of re-reads, or can be successfully error-corrected by the ECC unit by soft decoding or successfully error-corrected with a higher probability.

The attributes of the scenario in which the read command is applied include the LUN (identified by LUN number), the physical block (identified by physical block address), the physical page type (LSB/CSB/MSB), the time interval until the data on the physical block was written, the number of erasures of the physical block, the error rate of the physical block, the number of reads of the physical block, and/or whether the physical block was written intact (and the location currently written (identified by physical page address)).

The scene of the read command application is described in various attribute information and provided to the AI component. By way of example, the time interval in which data on a physical block has been written to so far includes or does not include the time when the solid state storage device is in a powered down state.

Optionally, the attribute information of the scenario in which the read command is applied further includes a physical page (indicated by a physical page address) to which the read command accesses, and a read command parameter (e.g., a read threshold voltage, a number of error bits of read data, a sequence of read command parameters that have been successfully error-corrected by soft decoding, and/or one or more read command parameters that have a high success rate of error correction of previously read data) that have been error-corrected by data that was last read from the physical page.

One or more combinations of the various attribute information may be used to train the neural network of the AI component.

In one embodiment according to the application, the ECC component fails to correct errors in the read data and, in response, re-reads the data by re-reading, etc. And in response to acquiring data that may be successfully error corrected by re-reading or the like, the corresponding read command parameters and the scene in which the read command is applied are used to train the neural network of the AI component.

In a further embodiment according to the application, in response to an error correction failure of the read data by the ECC unit, the corresponding read command parameters and the scenario in which the read command is applied are also used to train the neural network of the AI unit.

In still another embodiment according to the present application, a CPU core (not shown in the drawing) of the control section recognizes an error correction result of the read data by the ECC section and supplies a corresponding read command parameter and a scene in which the read command is applied to the AI section to train a neural network of the AI section. The CPU core controls the training, inference, turning on and/or turning off of the AI component by executing software.

Still alternatively, in response to a command or indication of the host, parameters of the neural network are set for the AI component, which parameters may be stored in the NVM chip of the solid-state storage device or provided by the host. Alternatively, the learned neural network parameters are obtained from the AI component in response to a command or instruction of the host and provided to the host or stored in the NVM chip of the solid-state storage device for use by other solid-state storage devices.

With continued reference to FIG. 18, taking the solid state storage device read command processing flow as an example, the host issues a read access command to the command issue queue of the solid state storage device (1). The read access command issued by the host is processed and forwarded to the media interface controller (2). The media interface controller issues a command (3) to the NVM chip based on the read access command issued by the host. The media interface controller also obtains the processing result of the read command from the NVM chip (4). For a read command, the data read from the NVM chip is provided to the ECC unit for error correction (5). If the ECC component is successful in correcting the error of the data, the processed read command is added to a command completion queue (6), and the scene in which the current read command is applied and the read command parameters are also forwarded to the AI component (6) for training the neural network of the AI component. The results of training the AI component are recorded in the memory of the control component, dynamic Random Access Memory (DRAM), or NVM chip.

Optionally, a plurality of neural networks are provided in the AI component, each neural network serving one or more of the solid-state storage device LUNs or physical blocks, thereby reducing the number of parameters provided to each neural network of the AI component, thereby reducing the need for the size of the neural network and/or training/inference time. For example, the solid state storage device includes 32 LUNs, while the AI component provides 4 or 32 neural networks corresponding to the 32 LUNs, each neural network being responsible for processing read commands for the specified 8 or 1 LUNs. The AI component provides the read command parameters and the context in which the read command was applied to the corresponding neural network to train the neural network in accordance with the LUN indicated in the context in which the read command was applied.

In the embodiment of FIG. 19, the host issues a read access command to the command issue queue of the solid state storage device (1). The read access command issued by the host is processed and forwarded to the media interface controller (2). The media interface controller issues a read command (3) to the NVM chip based on the read access command issued by the host. The media interface controller also obtains command processing results from the NVM chip (4). For a read command, the data read from the NVM chip is provided to the ECC unit for error correction (5). If the ECC component fails to correct the data error, the scenario in which the read command was applied (optionally including also read command parameters (e.g., read threshold voltage, number of error bits of read data, and/or sequence of read command parameters)) is forwarded to the AI component (6). The AI component infers the optimal read command parameters (e.g., read threshold voltages or read command sequences with different read threshold voltages) from the scenario in which the received read command was applied, generates a re-read command, and sends the re-read command to the media interface controller (7). The media interface controller issues a re-read command to the NVM chip based on the re-read command (8). The media interface controller also obtains the processing result of the re-read command from the NVM chip (9). The data read out by the re-read command is supplied to the ECC unit (10). If the ECC component fails to correct the error of the read data, the AI component re-initiates the process from step (6) to step (10). If the ECC block succeeds in correcting errors of the read data, a command for which the processing is completed is added to a command completion queue (11). By accessing the command completion queue, the host obtains command processing results (12).

In yet another embodiment according to the present application, a CPU core (not shown) of the control section recognizes an error correction result of the read data by the ECC section and provides a corresponding scene (optionally, including a read command parameter) where the read command is applied to the AI section, and the AI section generates a re-read command and transmits the re-read command to the media interface controller under the control of the CPU core (not shown) of the control section.

Optionally, the control means further comprises a rereading means (see fig. 2 and 7). The rereading component works in parallel with the AI component. By way of example, the AI component is employed to generate a re-read command in response to a first failure of the ECC component to correct an error of the read data, and the re-read command generated by the re-read component is employed in response to a subsequent failure of the ECC component to correct an error of the read data. As yet another example, the re-read command is generated with the re-read component in response to the ECC component failing for the first time to correct errors in the read data, and the re-read command generated with the AI component is re-used in response to the ECC component suggesting a re-read command to read data failing for the error correction. The re-read command indicates the read command parameters of the re-read command, and the method for generating the read command parameters is described with reference to fig. 8-17.

Optionally, the neural network of the AI component infers a scene category that best matches the current scene from the scene to which the received read command was applied, and selects a read command parameter and/or a read command sequence based on the best matching scene category.

In one example, the neural network of the AI component obtains a scene category that best matches the current scene based on the scene in which the read command is applied, generates a reread command or reread command sequence based on the scene category, and sends the reread command or reread command sequence to the nonvolatile memory via the media interface controller. In yet another example, the neural network of the AI component obtains a scene category that best matches the current scene from the scene in which the read command was applied, generates a reread command or reread command sequence from the scene in which the read command was applied and the read command parameters corresponding to the current read command with failure in error correction, and sends the reread command or reread command sequence to the nonvolatile memory via the media interface controller.

Still alternatively, if the AI component comprises a plurality of neural networks, each neural network serves one or more of a solid state storage device Logical Unit Number (LUN) or physical block. In response to failure of error correction of the read data by the ECC component, the current read command parameters and/or the scene in which the read command is applied are provided to the corresponding neural network in accordance with the LUN and/or the physical block indicated in the scene in which the read command is applied, to infer the read command parameters and/or the read command sequence appropriate to the scene in which the current read command is applied.

According to the embodiments of fig. 18 and 19, in the case of error correction failure of the ECC unit, the AI unit controls the re-reading process to be issued one or more times, so that the success rate of error correction of the read data of the re-reading command is improved, the interaction between the solid-state storage device and the host is reduced, and the processing delay of the read command is reduced.

The threshold setting method of the embodiment of the application can be applied to solid state storage equipment based on an NVM (non-volatile memory) chip, including but not limited to a solid state disk, a U disk, an SD card, a mobile phone, a tablet computer and other portable electronic equipment, and can also be applied to various electronic equipment which need to store information and use an NVM chip (such as a NAND flash memory, a phase change memory, an FeRAM, an MRAM and the like are common NVM).

While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application. It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A method of data recovery, comprising:

receiving a read access command sent by a host;

sending a read command to a nonvolatile memory according to the read access command;

receiving read data provided by the nonvolatile memory;

performing error correction on the read data;

if the error correction is successful, the corrected read data is sent to a host; training a neural network by utilizing the scene of the applied read command and the read command parameter indicated by the read command, wherein the classification of the scene of the applied read command is performed by training the neural network, and the corresponding relation between the classification of the scene and the read command parameter and/or the read command sequence is determined;

in response to error correction failure, the neural network deduces a read command parameter and/or a read command sequence corresponding to a scene to which the received read command is applied according to the scene, generates a reread command, and sends the reread command to the nonvolatile memory.

2. The data recovery method of claim 1, wherein the scene in which the read command is applied is an input of a neural network, and the read command parameter indicated by the read command is an output of the neural network.

3. The data recovery method according to claim 1 or 2, wherein parameters of a neural network are set in response to a command of the host, the parameters of the neural network being stored in the nonvolatile memory or provided by the host.

4. The data recovery method of claim 1 or 2, wherein a plurality of neural networks are trained, each of the neural networks serving one or more logical unit numbers or one or more physical blocks of a solid state storage device.

5. The data recovery method according to claim 1, wherein read data of the re-read command by the nonvolatile memory is received;

performing error correction on the read data of the re-read command;

if the error correction fails, repeatedly generating a reread command until the error correction is successful;

and if the error correction is successful, sending the read data of the corrected re-reading command to the host.

6. The data recovery method according to claim 1 or 2, wherein in response to a first failure of error correction of read data, a first reread command generated by the neural network is employed; and

In response to a subsequent failure of the error correction, generating a second read command, a read command parameter in the second read command indicating the second read command, and sending the second read command to the non-volatile memory.

7. The data recovery method according to claim 1 or 2, wherein the neural network infers a scene category that best matches a current scene from a scene to which the received read command is applied, and selects a read command parameter and/or a read command sequence according to the best matching scene category.

8. A solid state storage device comprising a control means for performing the data recovery method according to any one of claims 1-7 and a non-volatile memory chip.

9. The control component is characterized by comprising a command issuing queue, a medium interface controller, an error correction component, an artificial intelligence component and a command completion queue;

the command issuing queue is coupled with the medium interface controller, receives a read access command of a host and forwards the read access command to the medium interface controller;

the medium interface controller sends a read command to the nonvolatile memory and receives read data of the nonvolatile memory;

The error correction component is coupled with the media interface controller, and the error correction component performs error correction on the read data;

the command completion queue is coupled with the error correction component, and responds to successful error correction, the command completion queue receives error corrected data sent by the error correction component and sends the error corrected data to the host;

the artificial intelligence component is coupled with the error correction component, and trains a neural network by utilizing the scene in which the read command is applied and the read command parameters corresponding to the read command; classifying the applied scenes of the read command by training the neural network, and determining the corresponding relation between the categories of the scenes and the read command parameters and/or the read command sequences;

the artificial intelligence component responds to error correction failure, deduces a read command parameter and/or a read command sequence corresponding to a scene to which the received read command is applied according to the scene, generates a re-read command, and sends the re-read command to the nonvolatile memory.