CN109581771A - array substrate, array substrate manufacturing method and display device - Google Patents
array substrate, array substrate manufacturing method and display device Download PDFInfo
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- CN109581771A CN109581771A CN201811559365.2A CN201811559365A CN109581771A CN 109581771 A CN109581771 A CN 109581771A CN 201811559365 A CN201811559365 A CN 201811559365A CN 109581771 A CN109581771 A CN 109581771A
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- 239000010409 thin film Substances 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 238000004140 cleaning Methods 0.000 claims description 4
- 238000007689 inspection Methods 0.000 claims description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 25
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Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
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- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
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Abstract
The invention discloses an array substrate, an array substrate manufacturing method and a display device, wherein the array substrate comprises: the display device comprises a display area and a non-display area positioned on the periphery of the display area, wherein a transparent conducting layer is arranged in the display area, a virtual transparent conducting layer is arranged in the non-display area, and the virtual transparent conducting layer and the transparent conducting layer are arranged on the same layer; the shape of the virtual transparent conducting layer is matched with that of the transparent conducting layer.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of array substrates, the manufacturing method of array substrate and packet
Display device containing this array substrate.
Background technique
Here statement only provides background information related with the application, without inevitably constituting example technique.TFT-
LCD (Thin Film-Transistor Liquid Crystal Display, Thin Film Transistor-LCD) is liquid crystal
Show the main product in device.Liquid crystal display panel is the important component of liquid crystal display, and exemplary liquid crystal display panel includes two bases
Plate: color film (CF) substrate and array (Array) substrate, the surroundings of two substrates to box, are provided with by sealing frame between two substrates
The liquid crystal layer of liquid crystal material composition.
Usual liquid crystal display panel is divided into display area (AA) and is formed in the neighboring area of the periphery display area (AA), array
The pixel electrode and public electrode formed by transparency conducting layer is provided on substrate, in order to increase transmitance, present array substrate
On striated transparency conducting layer (ITO layer) width it is smaller and smaller.And transparency conducting layer is covered in display area (AA), battle array
The transparency conducting layer of striated is formed by photoetching process on column substrate, due to striated transparency conducting layer width very
It is narrow, after overexposure, development, during etching, the center of display area (AA) and the etching liquid of marginal position
Wear rate is different, leads to etching liquid density unevenness, eventually leads to the center and edge of display area (AA) after etching
The transparency conducting layer (ITO) of position is uneven (line width has nuance), bad so as to cause mura.
Summary of the invention
The main object of the present invention is to provide a kind of array substrate, realize transparency conducting layer line width uniformly and viewing area
The brightness uniformity in domain.
To achieve the above object, array substrate provided by the invention, including display area and be located at the display area outside
The non-display area enclosed, is provided with transparency conducting layer in the display area, and the non-display area is provided with virtual transparent lead
Electric layer, and the virtual transparency conducting layer and the transparency conducting layer same layer are arranged.
Optionally, the thickness of the virtual transparency conducting layer is equal to the thickness of the transparency conducting layer.
Optionally, the shape of the virtual transparency conducting layer and the shape of transparency conducting layer match.
Optionally, the non-display area is additionally provided with electrostatic protection ring, and the virtual transparency conducting layer is located at described aobvious
Show between region and the electrostatic protection ring.
Optionally, the virtual transparency conducting layer is connected to the electrostatic protection ring.
Optionally, the display area is additionally provided with grid line and data line；The non-display area is additionally provided with grid line
Lead and data lead, the grid line lead are connect with the grid line, and the data lead is connect with the data line.
Optionally, the virtual transparency conducting layer offers multiple avoid holes, the grid line lead and the data lead
It is located at the avoid holes.
Optionally, the virtual transparency conducting layer is provided with groove far from the side of the display area.
The present invention also proposes a kind of display device, a kind of array substrate, including display area and is located at the display area
The non-display area of periphery is provided with transparency conducting layer in the display area, which is characterized in that the non-display area setting
There is virtual transparency conducting layer, and the virtual transparency conducting layer and the transparency conducting layer same layer are arranged；It is described virtual transparent to lead
The thickness of electric layer is equal to the thickness of the transparency conducting layer；The marginal position of the transparency conducting layer with a thickness of L1, it is described
The central location of transparency conducting layer with a thickness of L2, wherein L1 > L2.
The present invention also proposes a kind of manufacturing method of array substrate, comprising: provides a substrate, the surface of the substrate has one
Viewing area and a non-display area, wherein the non-display area is located on the outside of the viewing area；
Thin film transistor (TFT) array is formed on the viewing area of the substrate, forms dummy TFT array in the base
The non-display area of plate；
Transparency conducting layer is through over cleaning, photoresist coating, exposure, development, etching, photoresist lift off and inspection, to be formed
Pattern for transparent conductive layer；
The present invention also proposes a kind of display device, including array substrate, the array substrate include display area and be located at institute
The non-display area of display area periphery is stated, transparency conducting layer, the non-display area setting are provided in the display area
There is virtual transparency conducting layer, and the virtual transparency conducting layer and the transparency conducting layer same layer are arranged.
Technical solution of the present invention is by being in same layer in non-display area setting and the transparency conducting layer 10 of display area
Virtual transparency conducting layer, in this way, in a lithographic process, since the non-display area of the marginal position periphery of display area is also set
It is equipped with transparency conducting layer, that is to say, that the edge of transparency conducting layer is located at edge of the non-display area without being located at display area
Position can guarantee that etching liquid is identical in the central location of display area and the wear rate of marginal position in this way, and etching liquid is dense
Degree uniformly so that transparency conducting layer the central location of display area and marginal position uniformly (line width indifference), can be with
The transparency conducting layer of the central location and marginal position that solve the problems, such as display area is non-uniform, reduces the undesirable generation of spot；
And the shape of virtual transparency conducting layer and transparency conducting layer are shaped to and matched, it is equivalent to the erosion of transparency conducting layer
It carves environment and becomes consistent with the etching environment of the central location of transparency conducting layer, to further ensure transparency conducting layer
It is internal identical with edge erosion liquid erosion wear rate, etching liquid even concentration, so that transparency conducting layer is in display area
(AA) central location and marginal position is uniform (line width indifference).
Detailed description of the invention
Technical solution in order to illustrate the embodiments of the present invention more clearly or in example technique, below will to embodiment or
Attached drawing needed in example technique description is briefly described, it should be apparent that, the accompanying drawings in the following description is only
It is some embodiments of the present invention, for those of ordinary skill in the art, without creative efforts, also
The structure that can be shown according to these attached drawings obtains other attached drawings.
Fig. 1 is the structural schematic diagram of array substrate preferred embodiment of the present invention；
Fig. 2 is the structural schematic diagram of array substrate driving circuit of the present invention；
Fig. 3 is the assembling schematic diagram of array substrate driving circuit and virtual transparency conducting layer of the present invention.
Drawing reference numeral explanation:
| Label | Title | Label | Title |
| 100 | Array substrate | 50 | Electrostatic protection ring |
| 10 | Transparency conducting layer | 70 | Grid line |
| 30 | Virtual transparency conducting layer | 71 | Grid line lead |
| 31 | Avoid holes | 90 | Data line |
| 33 | Groove | 91 | Data lead |
The embodiments will be further described with reference to the accompanying drawings for the realization, the function and the advantages of the object of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiment is only a part of the embodiments of the present invention, instead of all the embodiments.Base
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts it is all its
His embodiment, shall fall within the protection scope of the present invention.
It is to be appreciated that the directional instruction (such as up, down, left, right, before and after ...) of institute is only used in the embodiment of the present invention
In explaining in relative positional relationship, the motion conditions etc. under a certain particular pose (as shown in the picture) between each component, if should
When particular pose changes, then directionality instruction also correspondingly changes correspondingly.
In addition, the description for being related to " first ", " second " etc. in the present invention is used for description purposes only, and should not be understood as referring to
Show or imply its relative importance or implicitly indicates the quantity of indicated technical characteristic." first ", " are defined as a result,
Two " feature can explicitly or implicitly include at least one of the features.In addition, the technical solution between each embodiment can
It to be combined with each other, but must be based on can be realized by those of ordinary skill in the art, when the combination of technical solution occurs
Conflicting or cannot achieve when, will be understood that the combination of this technical solution is not present, also not the present invention claims protection model
Within enclosing.
The present invention proposes a kind of array substrate 100, as shown in Figure 1 to Figure 3, including display area and be located at the viewing area
The overseas non-display area enclosed is provided with transparency conducting layer 10 in the display area, and the non-display area is provided with virtually
Transparency conducting layer 30, and the virtual transparency conducting layer 30 and 10 same layer of transparency conducting layer are arranged, it is described virtual transparent to lead
The shape of electric layer 30 and the shape of transparency conducting layer 10 match.
It transparent is led by being in the virtual of same layer in the transparency conducting layer 10 of non-display area setting and display area AA
Electric layer 30, in this way, in a lithographic process, since the non-display area of the marginal position periphery of display area (AA) is additionally provided with
Bright conductive layer 10, that is to say, that the edge of transparency conducting layer 10 is located at side of the non-display area without being located at display area (AA)
Edge position can guarantee that etching liquid is identical as the wear rate of marginal position in the central location of display area (AA), carves in this way
Liquid even concentration is lost, so that transparency conducting layer 10 is in the central location of display area (AA) and the uniform (line width of marginal position
Indifference), it can solve the central location of display area AA and the non-uniform problem of transparency conducting layer 10 of marginal position, reduce
The undesirable generation of spot；And the shape of virtual transparency conducting layer 30 and transparency conducting layer 10 are shaped to and are matched, phase
When in the etching environment of transparency conducting layer 10 is become consistent with the etching environment of the central location of transparency conducting layer 10, thus
Inside and the edge erosion liquid erosion wear rate for further ensuring transparency conducting layer 10 are identical, etching liquid even concentration, into
And make transparency conducting layer 10 uniform (line width indifference) in the central location of display area (AA) and marginal position.
Specifically, as shown in Figure 1 to Figure 3, in the present embodiment, the thickness of the virtual transparency conducting layer 30 is equal to described
The thickness of transparency conducting layer 10.In the present embodiment, the thickness of virtual transparency conducting layer 30 and transparency conducting layer 10 is arranged
At identical, can make to avoid etching liquid due to the difference of the height of virtual transparency conducting layer 30 and transparency conducting layer 10
The inside of transparency conducting layer 10 and edge erosive velocity are inconsistent, in the specific application process, virtual 30 He of transparency conducting layer
Transparency conducting layer 10 is integrally formed, so as to eliminate the gap between virtual transparency conducting layer 30 and transparency conducting layer 10, from
And etching liquid may not flow into the gap between virtual transparency conducting layer 30 and transparency conducting layer 10, to further increase etching
Effect.In addition, it is necessary to explanation, transparency conducting layer 10 is ito thin film, and ito thin film is a kind of n-type semiconductor, tool
There are high conductivity, high visible light transmittance, high mechanical hardness and good chemical stability.
Specifically, as shown in Figure 1 to Figure 3, in the present embodiment, the non-display area is additionally provided with electrostatic protection ring
50, the virtual transparency conducting layer 30 is between the display area and the electrostatic protection ring 50.By virtual electrically conducting transparent
Layer 30 is arranged between display area and electrostatic protection ring 50, can not have to consider virtual transparency conducting layer 30 to array substrate
The influence of printed circuit board around 100 can be not required to so that the width of virtual transparency conducting layer 30 be arranged according to practical situation
The width of virtual transparency conducting layer 30 is arranged to fixed numerical value, so as to reduce the difficulty of production and assembly, is improved
Assembly efficiency.
More specifically, as shown in Figure 1 to Figure 3, in the present embodiment, the virtual transparency conducting layer 30 is connected to described quiet
Electric protective ring 50.On the one hand, by being arranged to virtual transparency conducting layer 30 to be connected to electrostatic protection ring 50, can increase virtual
The width of transparency conducting layer 30, i.e., so that the edge of virtual transparency conducting layer 30 and the edge of the viewing area of transparency conducting layer 10
Distance increases, to more be intended to become the etching environment of transparency conducting layer 10 and the central location of transparency conducting layer 10
Etching environment is consistent, to further ensure inside and the edge erosion liquid erosion wear rate phase of transparency conducting layer 10
Together, etching liquid even concentration, so that transparency conducting layer 10 is uniform in the central location of display area (AA) and marginal position
(line width indifference)；Still further aspect, electrostatic protection ring 50 can also lose virtual transparency conducting layer 30 and play positioning action, thus
The precision that assembly can be improved reduces the difficulty of assembly.
It should be noted that as shown in Figure 1 to Figure 3, in the present embodiment, the display area is additionally provided with 70 He of grid line
Data line 90；The non-display area is additionally provided with grid line lead 71 and data lead 91, the grid line lead 71 with it is described
Grid line 70 connects, and the data lead 91 is connect with the data line 90.It is defeated to liquid crystal display panel by grid line 70 and data line 90
Enter signal and voltage, so that liquid crystal molecule rotation is controlled, so that the display of control liquid crystal interview.In addition it is also necessary to illustrate
, for FFS technology, the transparency conducting layer 10 in array substrate 100 be can according to need as pixel electrode or common electrical
Pole, when pixel electrode is fringe-like structures, then the virtual transparency conducting layer 30 is arranged with the pixel electrode same layer, works as public affairs
Common-battery extremely fringe-like structures when, then virtual transparency conducting layer 30 i.e. and the public electrode same layer be arranged.
In the present embodiment, array substrate 100 is provided with printed circuit board, and more grid line leads are distributed in non-display area
71, every described 71 one end of grid line lead connects the grid line 70, and the other end connects gate electrode, and gate electrode is in the array substrate
100 the first binding region for being covered with grid flip chip package board passes through grid flip chip package board and gate driving electricity
Road connection；More radical evidences are also distributed in data electrode side in the region of the not set grid line lead 71 of the non-display area
Lead 91, every described 91 one end of data lead connect the data line 90, and the other end connects data electrode, and data electrode is in institute
State the second binding region for being covered with data flip chip package board of array substrate 100 by data flip chip package board with
Data drive circuit and printed circuit board connection；The not set grid line lead 71 of the non-display area described in gate electrode side
Also be distributed with more control signal connecting lines on region, the control signal connecting line be used for by the printed circuit board with it is described
Gate driving circuit is electrically connected, to carry out signal transmission；Wherein in the present embodiment, gate driving circuit and grid flip are thin
Film package board respectively at least there are two, data drive circuit and data flip chip package board also respectively at least there are two, due to
Printed circuit board is set to data electrode side, therefore, in the present embodiment, pastes grid flip chip package board at least two
Between first binding region and at least one first binding region for pasting grid flip chip package board is pasted at least one
It covers and the control signal connecting line is distributed between the second binding region of data flip chip package board；It is excellent in the present embodiment
Choosing, quasi- transparency conducting layer 10 is set to position corresponding with the control signal connecting line, and virtual transparency conducting layer 30
It is electrically connected with the control signal connecting line.Thus virtual transparency conducting layer 30 will be with the current potential phase of control signal connecting line
Together, but not the load of control signal connecting line is influenced, and virtual transparency conducting layer 30 and grid line lead 71 are absolutely not overlapping,
Will not have an impact to grid line lead 71, not will increase the load of grid line 70.
Optionally, the virtual transparency conducting layer 30 offers multiple avoid holes 31, the grid line lead 71 and the number
The avoid holes 31 are located at according to lead 91.So set, virtual transparency conducting layer 30 respectively with data lead 91 and grid line
Lead 71 is absolutely not overlapping, will not have an impact to data lead 91 and grid line lead 71, not will increase data line 90 and grid line
70 load, to will not influence adjusting of the driving circuit to liquid crystal display panel.
Optionally, the virtual transparency conducting layer 30 is provided with groove 33 far from the side of the display area.So set
It sets, extra etching liquid can be made to flow into groove 33, to ensure that the electrically conducting transparent of the marginal position positioned at viewing area
Layer 10 will not be etched by excessive etching liquid, be further ensured that transparency conducting layer 10 in the central location and side of display area (AA)
Edge position is uniformly (line width indifference).
The present invention also proposes that a kind of array substrate 100 includes display area and positioned at the non-display of the display area periphery
Region is provided with transparency conducting layer 10 in the display area, and the non-display area is provided with virtual transparency conducting layer 30, and
The virtual transparency conducting layer 30 is arranged with 10 same layer of transparency conducting layer；The thickness of the virtual transparency conducting layer 30 is equal to
The thickness of the transparency conducting layer 10；The marginal position of the transparency conducting layer 10 with a thickness of L1, the transparency conducting layer
10 central location with a thickness of L2, wherein L1 > L2.Due to being located at the etching liquid of display area marginal position to electrically conducting transparent
The etching speed of layer 10 is greater than the etching speed for being located at the etching liquid of display area central location to transparency conducting layer 10, so
In specific application process, by L1 setting in being greater than L2, even if the etching speed of the etching liquid of 10 edge of transparency conducting layer compared with
Fastly, the line width that can also reach transparency conducting layer 10 is consistent, and then generation the case where avoid brightness disproportionation.
The present invention also proposes a kind of manufacturing method of array substrate 100, comprising: provides a substrate, the surface tool of the substrate
There are a viewing area (AA) and a non-display area, wherein the non-display area is located on the outside of the viewing area；It is brilliant to form film
Body pipe array forms dummy TFT array in the non-display area of the substrate on the viewing area of the substrate；It is transparent
Conductive membrane layer is through over cleaning, photoresist coating, exposure, development, etching, photoresist lift off processing to form grid line and data
Line.In the specific application process, 1, substrate is provided, substrate surface has viewing area and non-display area, wherein non-display position
On the outside of viewing area；3, thin film transistor (TFT) array is formed on the viewing area of substrate, forms dummy TFT array in base
The non-display area of plate；4, transparency conducting layer 10 and virtual transparency conducting layer 30 are respectively arranged at display area and non-display area；
5, transparency conducting layer 10 is transparent to be formed through over cleaning, photoresist coating, exposure, development, etching, photoresist lift off and inspection
10 pattern of conductive layer；The pattern etch of transparency conducting layer 10 is matched at 10 pattern of transparency conducting layer.
Above-mentioned production stage is described in detail below: when manufacturing array substrate 100, firstly, providing array substrate
100, the surface of the array substrate 100 has the viewing area and the non-display area, and wherein the non-display area is located on the outside of viewing area.
Then, the thin film transistor (TFT) array is formed on the viewing area of the array substrate 100；Transparency conducting layer 10 is led with virtually transparent
Electric layer 30 forms one, the thickness of transparency conducting layer 10 and virtual transparency conducting layer 30 is arranged to it is identical, or directly be arranged
In same film, transparency conducting layer 10 and virtual transparency conducting layer 30 are then covered in display area and non-display area respectively
Domain then forms first layer metal film on substrate；The pattern of first layer metal film is defined with first piece of mask plate, is formed
Controlling grid scan line and gate electrode.Next, being sequentially depositing the first layer insulating, active layer, Ohmic contact on gate metal
Layer and second layer metal film；Using second piece of mask plate, i.e. first piece of gray tone mask plate first defines second layer metal film
Pattern, form source-drain electrode and data scan line；Secondly active layer isolated island and film transistor device conducting channel are formed.?
Second layer insulation film is formed above second layer metal.Finally, that is, second piece of gray tone mask plate is fixed using third block mask plate
Adopted second layer insulation film forms the pattern of second layer insulation film, so that portion of second layer metal and portion of second layer insulation
Layer is exposed, and other parts are then protected by light sensitive material.Deposited on herein layer of transparent conductive film and it is virtual thoroughly
Bright conductive film, the conductive film and virtual conductive film for then removing light sensitive material and adhering to thereon, eventually forms conduction
The pattern of film and virtual conductive film.
The present invention also proposes a kind of display device, which includes array substrate 100, the tool of the array substrate 100
Body structure is referring to above-described embodiment, since this display device uses whole technical solutions of above-mentioned all embodiments, until
Have the advantages that less all brought by the technical solution of above-described embodiment, this is no longer going to repeat them.The display device can be with
Are as follows: liquid crystal display panel, Electronic Paper, oled panel, mobile phone, tablet computer, television set, display, notebook etc. are any to be had
The products or components of display function.The display device includes display screen and liquid crystal display die set, which further includes backlight
Source, backlight are arranged with respect to liquid crystal display die set, and the liquid crystal display die set includes Liquid crystal module and reflecting layer, the liquid crystal group
Part includes the opaque area of transparent area and the neighbouring transparent area, and the reflecting layer is set to the backlight and the Liquid crystal module
Between, and the opaque area is blocked, the light portion of the backlight irradiating liquid crystal component passes through transparent area, another part quilt
Reflecting layer reflexes to backlight, and backlight is irradiated by the light refraction of reflection, and again to Liquid crystal module.By in optical filter and
Reflecting layer is set between backlight, and reflecting layer is made to block the opaque area of optical filter, when backlight shines, irradiates optical filter
When, the light for being irradiated to transparent area penetrates optical filter, be irradiated to opaque area light be incident on reflecting layer after return to backlight, originally
It cannot be re-used through the light in opaque area, be again introduced into transparent area after backlight reflects, it is opaque by blocking
The reflection of the reflectance coating in area improves the luminous flux of transparent area, and then improves the backlight illumination of liquid crystal display die set.In this way, can
To improve the light transmittance of liquid crystal display die set, and the display brightness of liquid crystal display die set is improved, it is user-friendly.It is understood that
, backlight is mounted in the cavity that one has reflection and reflective functions, or by the way that lens or reflection are arranged in backlight
Mirror, to realize the function of backlight refraction and reflection.And the optical filter can be colored filter, specifically, the colour is filtered
Mating plate can be the optical filter with RGB (RGB) arrangement of subpixels or RGBW (red, green, blue and white) arrangement of subpixels.Colour filter
Mating plate can make liquid crystal display die set display effect more preferable.
The above description is only a preferred embodiment of the present invention, is not intended to limit the scope of the invention, all at this
Under the inventive concept of invention, using equivalent structure transformation made by description of the invention and accompanying drawing content, or directly/use indirectly
It is included in other related technical areas in scope of patent protection of the invention.
Claims (10)
1. a kind of array substrate, the non-display area including display area and positioned at the display area periphery, the viewing area
Transparency conducting layer is provided in domain, which is characterized in that the non-display area is provided with virtual transparency conducting layer, and described virtual
Transparency conducting layer and the transparency conducting layer same layer are arranged；The shape of the virtual transparency conducting layer and the shape of transparency conducting layer
Match.
2. array substrate as described in claim 1, which is characterized in that the thickness of the virtual transparency conducting layer is equal to described
The thickness of bright conductive layer.
3. array substrate as claimed in claim 2, which is characterized in that the non-display area is additionally provided with electrostatic protection ring,
The virtual transparency conducting layer is between the display area and the electrostatic protection ring.
4. array substrate as claimed in claim 3, which is characterized in that it is anti-that the virtual transparency conducting layer is connected to the electrostatic
Retaining ring.
5. array substrate according to any one of claims 1 to 4, which is characterized in that the display area is additionally provided with
Grid line and data line；The non-display area is additionally provided with grid line lead and data lead, the grid line lead and the grid
Line connection, the data lead are connect with the data line.
6. array substrate according to claim 5, which is characterized in that the virtual transparency conducting layer offers multiple evacuation
Hole, the grid line lead and the data lead are located at the avoid holes.
7. array substrate according to claim 6, which is characterized in that the virtual transparency conducting layer is far from the viewing area
The side in domain is provided with groove.
8. a kind of array substrate, the non-display area including display area and positioned at the display area periphery, the viewing area
Transparency conducting layer is provided in domain, which is characterized in that the non-display area is provided with virtual transparency conducting layer, and described virtual
Transparency conducting layer and the transparency conducting layer same layer are arranged；The thickness of the virtual transparency conducting layer is equal to the transparency conducting layer
Thickness；The marginal position of the transparency conducting layer with a thickness of L1, the central location of the transparency conducting layer with a thickness of
L2, wherein L1 > L2.
9. a kind of manufacturing method of array substrate characterized by comprising provide a substrate, the surface of the substrate has one to show
Show Qu Yuyi non-display area, wherein the non-display area is located on the outside of the viewing area；
Thin film transistor (TFT) array is formed on the viewing area of the substrate, forms dummy TFT array in the substrate
Non-display area；
Transparency conducting layer is transparent to be formed through over cleaning, photoresist coating, exposure, development, etching, photoresist lift off and inspection
Conductive layer pattern.
10. a kind of display device, which is characterized in that including array substrate as described in any one of claim 1 to 7.
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| CN201811559365.2A CN109581771A (en) | 2018-12-19 | 2018-12-19 | array substrate, array substrate manufacturing method and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811559365.2A CN109581771A (en) | 2018-12-19 | 2018-12-19 | array substrate, array substrate manufacturing method and display device |
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| CN109581771A true CN109581771A (en) | 2019-04-05 |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0481819A (en) * | 1990-07-25 | 1992-03-16 | Hitachi Ltd | Liquid crystal display element |
| JPH0792477A (en) * | 1993-09-20 | 1995-04-07 | Sanyo Electric Co Ltd | Liquid crystal display device |
| CN101000440A (en) * | 2006-01-10 | 2007-07-18 | 统宝光电股份有限公司 | Display device for displaying images |
| CN201845768U (en) * | 2010-03-30 | 2011-05-25 | 深圳华映显示科技有限公司 | Electrostatic discharge protection structure |
| CN203365869U (en) * | 2013-08-12 | 2013-12-25 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN203643725U (en) * | 2013-12-02 | 2014-06-11 | 上海中航光电子有限公司 | Liquid crystal display device |
| CN106597765A (en) * | 2016-12-08 | 2017-04-26 | 深圳市华星光电技术有限公司 | Display device, display panel, and packaging method for display panel |
| CN108957885A (en) * | 2018-07-20 | 2018-12-07 | 深圳市华星光电技术有限公司 | Array substrate |
-
2018
- 2018-12-19 CN CN201811559365.2A patent/CN109581771A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0481819A (en) * | 1990-07-25 | 1992-03-16 | Hitachi Ltd | Liquid crystal display element |
| JPH0792477A (en) * | 1993-09-20 | 1995-04-07 | Sanyo Electric Co Ltd | Liquid crystal display device |
| CN101000440A (en) * | 2006-01-10 | 2007-07-18 | 统宝光电股份有限公司 | Display device for displaying images |
| CN201845768U (en) * | 2010-03-30 | 2011-05-25 | 深圳华映显示科技有限公司 | Electrostatic discharge protection structure |
| CN203365869U (en) * | 2013-08-12 | 2013-12-25 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN203643725U (en) * | 2013-12-02 | 2014-06-11 | 上海中航光电子有限公司 | Liquid crystal display device |
| CN106597765A (en) * | 2016-12-08 | 2017-04-26 | 深圳市华星光电技术有限公司 | Display device, display panel, and packaging method for display panel |
| CN108957885A (en) * | 2018-07-20 | 2018-12-07 | 深圳市华星光电技术有限公司 | Array substrate |
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Application publication date: 20190405 |