CN109581016A - A kind of random time equivalent sampling system - Google Patents
A kind of random time equivalent sampling system Download PDFInfo
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- CN109581016A CN109581016A CN201811321479.3A CN201811321479A CN109581016A CN 109581016 A CN109581016 A CN 109581016A CN 201811321479 A CN201811321479 A CN 201811321479A CN 109581016 A CN109581016 A CN 109581016A
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Abstract
The invention discloses a kind of random time equivalent sampling systems, it is cached after the sampled data that single acquisition obtains is carried out serioparallel exchange, measurement obtains the time interval between trigger signal and the first road Ge Sui clock followed by, obtained pulse signal obtains measured value by impulsive measurement module measurement after broadening, the starting memory location serial number of this sampled data is calculated according to the measured value, then Waveform Reconstructing RAM reading cache data, data streams read is first through parallel-serial conversion, then the corresponding storage unit serial number of each sampled point is calculated according to starting memory location serial number and equivalent sampling multiple, this sampled data is stored；When the batch of sampled data reaches equivalent sampling number, the data that Waveform Reconstructing RAM is stored are exported as equivalent sampling data.Compared to software realization mode, data rearrangement of the present invention is high-efficient, waveform resume speed is fast, to improve the wave-form refresh rate under oscillograph equivalent sampling mode.
Description
Technical field
The invention belongs to sampling technique fields, more specifically, are related to a kind of random time equivalent sampling system.
Background technique
Digital storage oscilloscope be test and analysis signal one of key instrument, information communication, high-energy physics and
Multiple industries such as medical electronics are all widely used.Digital storage oscilloscope main operational principle is that signal conditioning circuit will be defeated
Enter in Signal Regulation to analog-digital converter (ADC) optimal input range, ADC acquisition and quantization analog input signal, scene can compile
Journey logic gate array (Field-Programmable Gate Array, FPGA) controls memory according to trigger condition and accesses number
According to.It, can under digital storage oscilloscope real-time sampling mode due to being limited by ADC sample rate and nyquist sampling theorem
The signal bandwidth of observation is extremely limited, it usually needs observes high frequency periodic signal using random equivalent sampling technique.
Current random equivalent sampling technique exports random pulses using FPGA, by external circuit stretched pulse, simultaneously
FPGA caches stochastical sampling data, then rearranges combination to stochastical sampling data using upper computer software, it is final restore with
Display waveform.Fig. 1 is the flow chart of software reconfiguration waveform.As shown in Figure 1, when using software reconfiguration waveform, the every refreshing of oscillograph
One width waveform software requires to repeat starting acquisition, judges whether acquisition is completed, reads data many times.Due to being led
The limitation of device Bus Speed and arithmetic speed is controlled, especially in the biggish situation of equivalent sampling multiplying power, software needs to spend a large amount of
Time carries out Waveform Reconstructing, longer so as to cause dead time under oscillograph equivalent sampling mode, and wave-form refresh rate reduces, to letter
Number variation is insensitive, not very practical.
Summary of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of random time equivalent sampling systems, utilize
FPGA, which carries out data reconstruction, has the characteristics that data rearrangement is high-efficient, waveform resume speed is fast compared to software realization mode,
To improve the wave-form refresh rate under oscillograph equivalent sampling mode.
For achieving the above object, random time equivalent sampling system of the present invention includes ADC module, trigger signal generation
Module, serioparallel exchange module, data cache module, pulse output module, pulse broadening module, impulsive measurement module, starting are deposited
Storage unit computing module, parallel serial conversion module, Waveform Reconstructing RAM, wherein serioparallel exchange module, data cache module, pulse are defeated
Module, impulsive measurement module, starting memory location computing module, parallel serial conversion module, Waveform Reconstructing RAM are real in FPGA out
It is existing；
ADC module is given the sampling data transmitting collected to serial data and is converted for sampling to input signal
Module, while sampled data is sent to data cache module and pulse output module with road clock ADCLK；
Trigger signal generation module is compared with preset triggering level for receiving input signal, generates triggering letter
Number TRIG is sent to pulse output module；
Serioparallel exchange module carries out the reduction of speed that unstrings to sampled data, using the M circuit-switched data being converted to as parallel sampling number
Be sent to data cache module according to DATA, M indicates the reduction of speed multiplying power of unstringing of sampled data, value according to road clock ADCLK into
Row setting, needs to enable the clock of parallel sampling data DATA consistent with road clock ADCLK；
Data cache module receives parallel sampling data DATA and with road clock ADCLK, to simultaneously under with road clock ADCLK
Row sampled data DATA is cached, and triggering enable signal TRIG_EN is generated in caching and is sent to pulse output module；
Pulse output module includes 4 triggers D1, D2, D3, D4 and phase inverter I, for based on the received with Lu Shizhong
ADCLK and trigger signal TRIG, triggering enable signal TRIG_EN generate pulse signal T, and pulse signal T are sent to pulse
Broaden module；Wherein, inputted reference voltage Vcc as the end D of trigger D1 and set pin, using trigger signal TRIG as
The end CP of trigger D1 inputs, and will trigger enable signal TRIG_EN as the clearing of trigger D1 and inputs, the end Q of trigger D1
Output signal, will be with road clock ADCLK as trigger as the end the D input of trigger D2 and the end the CP input of trigger D4
The end CP of D2, D3 input, and input the end the Q output signal of trigger D2 as the end D of trigger D3, by the end Q of trigger D3
The inverted device I of output signal negate after as trigger D4 clearing input, using reference voltage Vcc as the end D of trigger D4
It is inputted with set pin, the output signal of trigger D4 is pulse signal T；
Pulse signal EXPEND_T after broadening is sent to by pulse broadening module for broadening to pulse signal T
Impulsive measurement module；
Obtained measured value count is sent to by impulsive measurement module for measuring to pulse signal EXPEND_T
Starting memory location computing module；
Starting memory location computing module is used to that this sampled data to be calculated according to the measured value count received
Starting memory location serial number S, and it is sent to Waveform Reconstructing RAM；The calculation formula of starting memory location serial number S is as follows:
Wherein, count_T and count_2T respectively indicates 1 sampling interval measured in advance by impulsive measurement module
The measured value of pulse signal after the corresponding broadening of T and 2 sampling interval 2T, X indicate equivalent sampling multiple；
It is X × N × d memory space that a size is preset in Waveform Reconstructing RAM, and wherein N indicates ADC module single
The sampling number of sampling, d indicate the data bit width of each sampled point, which is divided into X × N number of storage unit；Wave
Shape reconstructs RAM after receiving the starting memory location serial number S of this sampled data, to data cache module and parallel-serial conversion mould
Block sends sampled data and reads instruction, then receives the serial samples data that parallel serial conversion module is sent and is stored, n-th
Storage unit serial number A corresponding to sampled pointn=S+n × X, n=1,2 ..., N；Waveform Reconstructing RAM is by this sampled data
After storage, then reset signal is generated, is sent to data cache module, pulse output module, impulsive measurement module, originates and deposit
Storage unit computing module and parallel serial conversion module are acquired next time with starting；When the storage number of Waveform Reconstructing RAM reaches equivalent
Sample multiple X, that is, complete primary complete equivalent sampling, using the data stored in memory space as equivalent sampling data into
Row output；
Parallel serial conversion module is used to read this parallel sampling data DATA from data cache module, carries out and go here and there to turn
Serial samples data are sent to Waveform Reconstructing RAM after changing.
The sampled data that single acquisition obtains is carried out serioparallel exchange and is sent to by random time equivalent sampling system of the present invention
Data cache module in FPGA is cached, and obtains trigger signal and first followed by by pulse output module measurement
With the time interval between the clock of road, after the pulse signal exported is broadened by pulse broadening module again, by impulsive measurement
Module measurement obtains measured value, and the starting of this sampled data is calculated according to the measured value for starting memory location computing module
Storage unit serial number, then Waveform Reconstructing RAM reads data from data cache module, and data streams read is first through parallel-serial conversion, so
The corresponding storage unit serial number of each sampled point is calculated according to starting memory location serial number and equivalent sampling multiple afterwards, this is adopted
Sample data are stored；When the batch of sampled data reaches equivalent sampling number, data that Waveform Reconstructing RAM is stored as
Equivalent sampling data are exported.Compared to software realization mode, data rearrangement of the present invention is high-efficient, waveform resume speed is fast,
To improve the wave-form refresh rate under oscillograph equivalent sampling mode.
Detailed description of the invention
Fig. 1 is the flow chart of software reconfiguration waveform；
Fig. 2 is a kind of specific embodiment structure chart of random time equivalent sampling system of the present invention；
Fig. 3 is the structure chart of pulse output module in the present invention；
Fig. 4 is the schematic diagram based on diclinic capacitor charge and discharge stretch circuit in the present embodiment.
Specific embodiment
A specific embodiment of the invention is described with reference to the accompanying drawing, preferably so as to those skilled in the art
Understand the present invention.Requiring particular attention is that in the following description, when known function and the detailed description of design perhaps
When can desalinate main contents of the invention, these descriptions will be ignored herein.
Fig. 2 is a kind of specific embodiment structure chart of random time equivalent sampling system of the present invention.As shown in Fig. 2, this
Invention random time equivalent sampling system includes ADC module 1, trigger signal generation module 2, serioparallel exchange module 3, data buffer storage
Module 4, pulse output module 5, pulse broadening module 6, impulsive measurement module 7, starting memory location computing module 8 and string turn
Block 9, Waveform Reconstructing RAM10 are changed the mold, wherein serioparallel exchange module 3, data cache module 4, pulse output module 5, impulsive measurement
Module 7, starting memory location computing module 8, parallel serial conversion module 9, Waveform Reconstructing RAM10 realize in FPGA, lower mask body
Modules are described in detail.
ADC module 1 gives serial data and conversion module for sampling to input signal, by obtained sampling data transmitting
3, while sampled data is sent to data cache module 4 and pulse output module 5 with road clock ADCLK.
Trigger signal generation module 2 is compared with preset triggering level for receiving input signal, generates triggering letter
Number TRIG is sent to pulse output module 5.
Serioparallel exchange module 3 carries out the reduction of speed that unstrings to sampled data, using the M circuit-switched data being converted to as parallel sampling number
Data cache module 4 is sent to according to DATA.The purpose of serioparallel exchange is in order to carry out reduction of speed to sampled data, to adapt to FPGA's
Data rate requirement, it is clear that the rate of the parallel sampling data after reduction of speed is the 1/M of original sampling data, and M indicates sampled data
Reduction of speed multiplying power of unstringing, its value of M is configured according to road clock ADCLK, need to enable the clock of parallel sampling data DATA with
It is consistent with road clock ADCLK.In fact, being exactly the work clock of FPGA with road clock ADCLK.
Data cache module 4 receives parallel sampling data DATA and with road clock ADCLK, right under with road clock ADCLK
Parallel sampling data DATA is cached, and triggering enable signal TRIG_EN is generated in caching and is sent to pulse output module 5.
Unitary sampling data distribution equidistant position before and after trigger point when random equivalent samples, not due to trigger signal generation time
It is fixed, it is therefore desirable to the data before and after dynamic buffering trigger point, for the data cached Read-write Catrol process of simplification, in the present embodiment
Data cache module 4 is realized based on the asynchronous FIFO inside FPGA.The generating process for triggering enable signal TRIG_EN can be brief
It is described as follows:
In data cache module 4, a counter is set, the size of the counter only has the half of FIFO capacity, uses
It is counted in the data before trigger signal.When data buffer storage starts, FIFO starts storing data, and unison counter is opened
Begin to count, when the data in FIFO are not up to half, trigger signal TRIG_EN is invalid, even if at this moment there is trigger signal production
It is raw, also think that trigger signal is invalid.This is because unitary sampling data are imperfect if data do not arrive capacity half in FIFO
's.When counter counts are full, data reach half in expression FIFO, this season, trigger signal TRIG_EN was effective, triggering hereafter
Signal is effective trigger signal, can be used for controlling data buffer storage.When if trigger signal TRIG_EN is set to effective temporarily not
There is trigger signal arrival, then first half data need to carry out dynamic update in FIFO, being always maintained at data is capacity half,
Even first half data are the data before triggering.When trigger signal arrives, then continue to FIFO latter half memory space
Data are written, until FIFO is filled with.
Pulse output module 5 includes 4 triggers D1, D2, D3, D4 and phase inverter I, for based on the received with Lu Shizhong
ADCLK and trigger signal TRIG, triggering enable signal TRIG_EN generate pulse signal T, and pulse signal T are sent to pulse
Broaden module 6.The mentality of designing of pulse output module 5 is as follows in the present invention:
Since ADC module 1 always works under highest sample rate under equivalent sampling mode, it is assumed that highest sample rate is
1.25GHz, the data output mode of ADC module 1 are bilateral along Double Data Rate output, and data reduction of speed module carries out four times of drops
Speed.It is 312.5MHz with road clock frequency so after reduction of speed is handled, the corresponding clock cycle is then 3.2ns, trigger signal
Time interval Δ t between the first road Ge Sui clock followed by is within the scope of 0~3.2ns.Realize that random equivalent is adopted
How precise measurement trigger pulse reaches the time interval Δ t between subsequent first sampling pulse to the critical issue of sample, should
How collected data carry out depositing number according to chronological order after time interval directly determines triggering, to guarantee waveform
Correct reconstruct.And since Δ t is usually at ns grades hereinafter, need the ability precise measurement after external circuit broadens, to guarantee
Stretch circuit outside FPGA works in linear region, and the pulse signal being broadened cannot be too narrow, therefore the present invention uses
A sampling interval (3.2ns) is superimposed on the basis of the original time interval of delta t, so that being finally sent to stretch circuit
Signal pulsewidth is within the scope of 3.2~6.4ns.
Fig. 3 is the structure chart of pulse output module in the present invention.As shown in figure 3, using reference voltage Vcc as trigger D1
The end D and set pin input, using trigger signal TRIG as trigger D1 the end CP input, will triggering enable signal TRIG_EN
Clearing as trigger D1 inputs, D end input and trigger D4 of the end the Q output signal of trigger D1 as trigger D2
The input of the end CP, inputted with road clock ADCLK as the end CP of trigger D2, D3, by the end the Q output signal of trigger D2 work
It is inputted for the end D of trigger D3, the clearing after the inverted device I of the end Q output signal of trigger D3 is negated as trigger D4
Input is inputted reference voltage Vcc as the end D of trigger D4 and set pin, and the output signal of trigger D4 is pulse letter
Number T.
The specific work process of pulse output module 5 is as follows: after initialization acquisition, the end Q of trigger D1~D4 exports letter
It number is all logic level " 0 ", after system allows triggering, TRIG_EN output is high level, and trigger D1 is raised along triggering,
Its output level is become " 1 " from " 0 ", while trigger D4 can be also raised along triggering, output signal, i.e. pulse signal T's
Level becomes " 1 " from " 0 "；First triggering is received along rear in trigger D1, and trigger D2 detects first ADCLK clock edge
The then high level of latched flip flop D1 output, second ADCLK clock along when trigger D3 then latched flip flop D2 output height
Level, trigger D4 is cleared at this time, and the pulse signal T of trigger D4 output becomes " 0 " from " 1 ".
From the above description, it can be seen that being superimposed on time interval Δ t between a sampling in the present invention using trigger D2, D3
Every being in the pulse interval Δ T of final pulse signal T between 3.2~6.4ns.
Pulse signal EXPEND_T after broadening is sent to by pulse broadening module 6 for broadening to pulse signal T
Impulsive measurement module 7.The physical circuit and multiple of stretcher of pulse broadening module 6 can be set as needed, in the present embodiment
Pulse broadens module 6 and uses the stretch circuit based on diclinic capacitor charge and discharge.Fig. 4 is in the present embodiment based on diclinic capacitor
The schematic diagram of charge and discharge stretch circuit.As shown in figure 4, based on diclinic capacitor charge and discharge pulse broadening electricity in the present embodiment
Road, when pulse signal T rising edge reaches, the constant-current source of low current charges to capacitor, vertical when pulse falling edge reaches
Stop to capacitor charging, while being discharged with the small current constant-current source directly proportional to charging constant-current source capacitor, due to electricity
Voltage is Δ U when holding impulse electricity, i.e. the capacitor charge and discharge time is determined by the electric current that constant-current source exports: Δ T/ Δ t=Ic/If=
K, wherein IfFor discharge current, IcFor charging current, K is pulse multiple of stretcher.Pulse after broadening can form impulsive measurement mould
The time gate of block 7.
Obtained measured value count is sent to by impulsive measurement module 7 for measuring to pulse signal EXPEND_T
Starting memory location computing module 7.
Starting memory location computing module 7 is used to that this sampled data to be calculated according to the measured value count received
Starting memory location serial number S, and be sent to Waveform Reconstructing RAM10.The calculation formula of starting memory location serial number S is as follows:
Wherein, count_T and count_2T is respectively indicated measure obtain 1 sampling in advance by impulsive measurement module 7 between
The measured value of pulse signal after the corresponding broadening of T and 2 sampling interval, X indicate equivalent sampling multiple.count_2T-
Count_T is theoretically equal to count_T, but since there are non-linear factors in pulse broadening module, can make to measurement result
At influence, keep actual value different from theoretical value, in order to reduce the influence to calculated result, denominator still uses count_ herein
2T-count_T。
It is X × N × d memory space that a size is preset in Waveform Reconstructing RAM10, and wherein N indicates ADC module 1
The sampling number of unitary sampling, d indicate the data bit width of each sampled point, and it is single which is divided into X × N number of storage
Member, it is clear that the size of each storage unit is d.Waveform Reconstructing RAM10 is in the starting memory location for receiving this sampled data
After serial number S, sampled data is sent to data cache module 4 and parallel serial conversion module 9 and reads instruction, then receives parallel-serial conversion mould
The serial samples data of the transmission of block 9 are simultaneously stored, storage unit serial number A corresponding to n-th of sampled pointn=S+n × X, n=
1,2,…,N。
Since each sampled data of ADC module 1 is a part in primary complete equivalent sampling, i.e., each waveform weight
The processing of structure RAM10 processing is partial data, therefore to obtain complete equivalent sampling waveform, need by multi collect,
Sampled point on repetition period signal waveform different location, i.e., be stitched together, restore original again by triggering, caching, sequence
Signal.Due to wanting multiple repairing weld, then every completion one acquisition is required to other relevant modes in addition to Waveform Reconstructing RAM10
Block is resetted, therefore Waveform Reconstructing RAM10 then generates reset signal, be sent to after storing this sampled data
Data cache module 4, pulse output module 5, impulsive measurement module 7, starting memory location computing module 7 and parallel serial conversion module
9 enter reset, are acquired next time with starting.When the storage number of Waveform Reconstructing RAM10 reaches equivalent sampling multiple X, that is, complete
Primary complete equivalent sampling, memory space is filled at this time, then using the data stored in memory space as equivalent sampling
Data are exported.
Parallel serial conversion module 9 is used to read this parallel sampling data DATA from data cache module 4, carries out and goes here and there
Serial samples data are sent to Waveform Reconstructing RAM10 after conversion.
Embodiment
Technical solution in order to better illustrate the present invention, it is equivalent to random time of the present invention using a specific embodiment
The detailed process of sampling system is described in detail.
It is 40 that equivalent sampling multiplying power, which is arranged, in the present embodiment.The single channel highest sample rate of ADC module 1 is 1.25GHz, i.e.,
The sample rate of ADC module 1 is 1.25GHz, and the data bit width of each sampled point is 8bit, exports the rate with road clock ADCLK
For 312.5MHz.Therefore, the number of parallel data is 4 after the progress of serioparallel exchange module 3 serioparallel exchange, that is, carries out 1/4 reduction of speed, number
Input data rate according to cache module 4 is 312.5MHz, and input data bit wide is 32bit.It is 64 that unitary sampling, which is arranged, to count,
The data volume of so each FIFO storage is 16 32bit data, the data points of corresponding 64 8bit.FIFO output data speed
Rate is determined that data bit width is similarly 32, corresponding 4 sampled points by several rates of depositing of data reconstruction RAM.
Pulse output module 5 generates pulse signal T, is broadened to obtain pulse signal EXPEND_ by pulse broadening module 6
T, impulsive measurement module 7 measure it to obtain measured value count feeding starting memory location computing module 7.Assuming that measured value
Count=1500.
To reduce the error generated when each calculating storaging unit serial number, when inputting one to impulsive measurement module 7 in advance
Clock period (3.2ns) and the corresponding pulse of two clock cycle (6.4ns), and using impulsive measurement module 7 obtain 3.2ns and
The corresponding count value of 6.4ns pulse width, is denoted as count_3.2ns=2000 and count_6.4ns=1000 respectively.Starting is deposited
Storage unit computing module 7 calculates starting memory location serial number S after receiving count value:
The size of memory space is 4 × 40 × d in data reconstruction RAM in the present embodiment.Waveform Reconstructing RAM10 is being received
After the starting memory location serial number S of this sampled data, sampled data is sent to data cache module 4 and parallel serial conversion module 9
Read instruction.FIFO exports a beat of data, and data are split as 4 points and are stored in data reconstruction RAM respectively by parallel serial conversion module 9.
Present sample point data can be obtained in the storage of memory space by starting memory location serial number and equivalent multiplying power in data reconstruction RAM
Unit number, calculation formula are as follows: An=S+n × X=80+n × 40, n=1,2 ..., N, i.e. storage unit serial number are followed successively by 80,
120,160,200,240…。
It should be understood that if subsequent be also calculated starting memory location serial number S=120, storage unit
Serial number is followed successively by 120,160,200 ..., although that is, starting memory location serial number it is different, double sampling data storage
The storage unit of data other points other than first point are the same, and can generate the covering of data.This is because arteries and veins
Rush signal T be by being generated with road clock ADCLK and trigger signal, and with road clock be by ADC sample rate (data rate) drop
What speed obtained.It is 4 times of reductions of speed in the present embodiment, i.e. M in the calculation formula of starting memory location serial number is 4, therefore is calculated
When this 4 values of starting memory location serial number S=40,80,120,160 arrived, every group of subsequent storage unit of data is phase
With, that is, data cover before is fallen.It has been investigated that sampling number is more due in the sampling of equivalent random time,
Therefore the appearance of above situation can't generate the equivalent sampling data finally obtained substantive influence.
Although the illustrative specific embodiment of the present invention is described above, in order to the technology of the art
Personnel understand the present invention, it should be apparent that the present invention is not limited to the range of specific embodiment, to the common skill of the art
For art personnel, if various change the attached claims limit and determine the spirit and scope of the present invention in, these
Variation is it will be apparent that all utilize the innovation and creation of present inventive concept in the column of protection.
Claims (1)
1. a kind of random time equivalent sampling system, it is characterised in that including ADC module, trigger signal generation module, go here and there and turn
It changes the mold block, data cache module, pulse output module, pulse broadening module, impulsive measurement module, starting memory location and calculates mould
Block, parallel serial conversion module, Waveform Reconstructing RAM, wherein serioparallel exchange module, data cache module, pulse output module, pulse are surveyed
Amount module, starting memory location computing module, parallel serial conversion module, Waveform Reconstructing RAM are realized in FPGA；
ADC module gives serial data and conversion module for sampling to input signal, by the sampling data transmitting collected,
Sampled data is sent to data cache module and pulse output module with road clock ADCLK simultaneously；
Trigger signal generation module is compared with preset triggering level for receiving input signal, generates trigger signal
TRIG is sent to pulse output module；
Serioparallel exchange module carries out the reduction of speed that unstrings to sampled data, using the M circuit-switched data being converted to as parallel sampling data
DATA is sent to data cache module, and M indicates that the reduction of speed multiplying power of unstringing of sampled data, value are carried out according to road clock ADCLK
Setting, needs to enable the clock of parallel sampling data DATA consistent with road clock ADCLK；
Data cache module receives parallel sampling data DATA and with road clock ADCLK, to adopting parallel under with road clock ADCLK
Sample data DATA is cached, and triggering enable signal TRIG_EN is generated in caching and is sent to pulse output module 5；
Random pulses output module includes 4 triggers D1, D2, D3, D4 and phase inverter I, for based on the received with Lu Shizhong
ADCLK and trigger signal TRIG, triggering enable signal TRIG_EN generate pulse signal T, and pulse signal T are sent to pulse
Broaden module；Wherein, inputted reference voltage Vcc as the end D of trigger D1 and set pin, using trigger signal TRIG as
The end CP of trigger D1 inputs, and will trigger enable signal TRIG_EN as the clearing of trigger D1 and inputs, the end Q of trigger D1
Output signal, will be with road clock ADCLK as trigger as the end the D input of trigger D2 and the end the CP input of trigger D4
The end CP of D2, D3 input, and input the end the Q output signal of trigger D2 as the end D of trigger D3, by the end Q of trigger D3
The inverted device I of output signal negate after as trigger D4 clearing input, using reference voltage Vcc as the end D of trigger D4
It is inputted with set pin, the output signal of trigger D4 is pulse signal T；
Pulse signal EXPEND_T after broadening is sent to pulse for broadening to pulse signal T by pulse broadening module
Measurement module；
Obtained measured value count is sent to starting for measuring to pulse signal EXPEND_T by impulsive measurement module
Storage unit computing module；
Starting memory location computing module is used to be calculated the starting of this sampled data according to the measured value count received
Storage unit serial number S, and it is sent to Waveform Reconstructing RAM；The calculation formula of starting memory location serial number S is as follows:
Wherein, count_T and count_2T respectively indicates the 1 sampling interval T and 2 measured in advance by impulsive measurement module
The measured value of pulse signal after the corresponding broadening of a sampling interval 2T, X indicate equivalent sampling multiple；
It is X × N × d memory space that a size is preset in Waveform Reconstructing RAM, and wherein N indicates ADC module unitary sampling
Sampling number, d indicates the data bit width of each sampled point, which is divided into X × N number of storage unit；Waveform weight
Structure RAM is sent out after receiving the starting memory location serial number S of this sampled data to data cache module and parallel serial conversion module
It send sampled data to read instruction, then receive the serial samples data that parallel serial conversion module is sent and is stored, n-th of sampling
The corresponding storage unit serial number A of pointn=S+n × X, n=1,2 ..., N；Waveform Reconstructing RAM is stored by this sampled data
After, then reset signal is generated, data cache module, pulse output module, impulsive measurement module, starting storage list are sent to
First computing module and parallel serial conversion module are acquired next time with starting；When the storage number of Waveform Reconstructing RAM reaches equivalent sampling
Multiple X completes primary complete equivalent sampling, carry out using the data stored in memory space as equivalent sampling data defeated
Out；
Parallel serial conversion module is used to read this parallel sampling data DATA from data cache module, after carrying out parallel-serial conversion
Serial samples data are sent to Waveform Reconstructing RAM.
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| CN110836993A (en) * | 2019-11-14 | 2020-02-25 | 电子科技大学 | FPGA-based random equivalent acquisition system |
| CN110941461A (en) * | 2019-11-26 | 2020-03-31 | 杭州皓智天诚信息科技有限公司 | Parameter configuration terminal of service processing software |
| CN115509167A (en) * | 2022-11-17 | 2022-12-23 | 安徽省国盛量子科技有限公司 | Parameter configuration method of pulse sequence, signal control and acquisition method and equipment |
| CN117420342A (en) * | 2023-11-08 | 2024-01-19 | 苏州联讯仪器股份有限公司 | Multichannel acquisition method, device, system, FPGA and sampling oscilloscope |
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| CN115509167B (en) * | 2022-11-17 | 2023-01-20 | 安徽省国盛量子科技有限公司 | Parameter configuration method of pulse sequence, signal control and acquisition method and equipment |
| CN117420342A (en) * | 2023-11-08 | 2024-01-19 | 苏州联讯仪器股份有限公司 | Multichannel acquisition method, device, system, FPGA and sampling oscilloscope |
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