CN109565242A - Series circuit, circuit board and calculating equipment - Google Patents
Series circuit, circuit board and calculating equipment Download PDFInfo
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- CN109565242A CN109565242A CN201880002433.7A CN201880002433A CN109565242A CN 109565242 A CN109565242 A CN 109565242A CN 201880002433 A CN201880002433 A CN 201880002433A CN 109565242 A CN109565242 A CN 109565242A
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- input terminal
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
- H02M1/007—Plural converter units in cascade
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The embodiment of the present disclosure discloses a kind of series circuit, circuit board and calculates equipment.The series circuit includes the chip of at least one set of N grades of series connection, each chip has main operating voltage input terminal, back work voltage input end and ground terminal, it further include N step voltage clamp circuit corresponding with the chip that described N grades is connected in series, wherein the first voltage input terminal of every voltage order one clamp circuit and second voltage input terminal are connected in parallel in the ground terminal and main operating voltage input terminal of chip at the same level, for stablizing the main operating voltage of every level-one chip；Wherein, N is the integer greater than 1.The embodiment of the present disclosure by adjusting dynamic current in real time, it is ensured that the operating voltage of every level-one chip is relatively stable in series circuit, improves the reliability of series circuit.
Description
Technical field
This disclosure relates to the power supply power supply technology of IC chip, more particularly to a kind of series circuit, circuit board and
Calculate equipment.
Background technique
Currently based on the calculating equipment of large scale integrated circuit using conventional parallel power supply structure there are the electric currents excessive, energy
The significant drawbacks such as service efficiency is low, and increase the cost of requirement and the production design of chip circuit design.With semiconductor
The working power voltage of the development of technique, integrated circuit (IC) chip is lower and lower, and operating current is increasing, in order to maximize
The transfer efficiency of power supply, the prior art begin to take the power supply mode of chip-in series, i.e. multiple groups core on printed circuit board (PCB)
Piece forms the voltage domain of plural serial stage by the way of being serially connected between power input and ground terminal.This series connection supplies
Electric framework can effectively reduce circuit bulk supply electric current, improve power supply conversion efficiency, and can reduce power supply converter section
The cost of parallel circuit device.
Outer power voltage VCC is converted to output voltage VDD to series connection by DC-DC power module by this series circuit
IC chip power supply, the internal resistance of each chip be not it is completely the same, it is each that the internal resistance difference of each chip will lead to supply
The case where operating voltage of chip is inconsistent, even burns so as to cause some chip cisco unity malfunctions appearance.It therefore, is guarantor
Demonstrate,proving concatenated chip can work normally, and a kind of existing embodiment is that concatenated chip is formed multiple groups chip to be powered
Group, by the way that multiple voltage output ends of a voltage clamp circuit are respectively connected between two groups of adjacent chipsets to be powered,
To stablize the main operating voltage between two groups of adjacent chipsets to be powered.In the existing embodiment, the voltage clamp
Position circuit controls voltage transformation module by programmable control module and exports multiple output voltages.But the inventor of the disclosure
It was found that the input voltage that this scheme not can guarantee between each series chip of chipset internal to be powered is in stationary value, thus
It cannot ensure that the working power of every level-one chip keeps stable, reduce the reliability of series circuit.
Summary of the invention
The embodiment of the present disclosure provides a kind of series circuit, circuit board and calculates equipment, to solve the problems of the prior art.
In a first aspect, the embodiment of the present disclosure proposes a kind of series circuit, comprising:
The chip of at least one set of N grades of series connection, each chip have main operating voltage input terminal, back work electricity
Press input terminal and ground terminal；
N step voltage clamp circuit corresponding with the chip that described N grades is connected in series, wherein every voltage order one clamp circuit
First voltage input terminal and second voltage input terminal are connected in parallel in the ground terminal and main operating voltage input terminal of chip at the same level, use
In the main operating voltage for stablizing every level-one chip；Wherein, N is the integer greater than 1.
In some embodiments, the voltage clamp circuit includes operational amplifier and metal-oxide-semiconductor, the operational amplifier
Normal phase input end be connected to first voltage input terminal via first resistor, via second resistance be connected to second voltage input
End, the inverting input terminal of the operational amplifier are connected to first voltage input terminal via a voltage-stabiliser tube, connect via 3rd resistor
It is connected to second voltage input terminal, the output end of the operational amplifier is connected to the inverting input terminal via first capacitor device；
The grid of the metal-oxide-semiconductor is connected to the output end of the operational amplifier, and source electrode is connected to the first voltage input terminal, drain electrode
It is connected to the second voltage input terminal.
In some embodiments, the both ends of the first capacitor device are connected in parallel RC series circuit, the RC series electrical
Road includes the 4th resistance and the second capacitor being connected in series.
In some embodiments, two feeder ears of the operational amplifier are respectively connected to the first external dc voltage
With the first voltage input terminal.
In some embodiments, first external dc voltage and the voltage difference of first voltage input terminal are one predetermined
Value.
In some embodiments, the series circuit further include: low voltage difference corresponding with the N step voltage clamp circuit
Second external dc voltage is converted to the first external dc voltage by linear voltage stabilization unit, the low pressure difference linearity voltage regulation unit.
Second aspect, the embodiment of the present disclosure propose a kind of series circuit, comprising:
The chip of at least one set of N grades of series connection, each chip have main operating voltage input terminal, back work electricity
Press input terminal and ground terminal；
N-1 step voltage clamp circuit corresponding with the chip that described N grades is connected in series, wherein every voltage order one clamp circuit
Voltage output end the main operating voltage input terminal being respectively connected between the chip of adjacent connection, every voltage order one pincers
The voltage input end of position circuit connects the first external dc voltage, for stablizing the main operating voltage of every level-one chip.
In some embodiments, the voltage clamp circuit includes application condition unit, PWM generation unit, metal-oxide-semiconductor drive
Moving cell, metal-oxide-semiconductor unit, the application condition unit are received respectively outside the output voltage and described first of the metal-oxide-semiconductor unit
Portion's DC voltage, and the application condition signal for exporting the output voltage and the first external dc voltage generates list to the PWM
Member, the PWM generation unit are based on the application condition signal and generate pwm signal, control metal-oxide-semiconductor driving unit driving institute
It states metal-oxide-semiconductor unit and exports the output voltage, wherein the output voltage is connected to the master between the chip of adjacent connection
Operating voltage input terminal.
In some embodiments, the voltage clamp circuit further includes at least one normalization circuit unit, for pair
It is input to output voltage described in the application condition unit and the first external dc voltage is normalized.
In some embodiments, the normalization circuit unit includes bleeder circuit unit, for described to being input to
Output voltage described in application condition unit and the first external dc voltage carry out voltage division processing.
The third aspect, the embodiment of the present disclosure propose that a kind of circuit board, the circuit board include such as first aspect or second party
Series circuit described in any embodiment of face.
Fourth aspect, the embodiment of the present disclosure propose a kind of calculating equipment, and the calculating equipment includes such as first aspect or the
Series circuit described in two aspect any embodiments.
The embodiment of the present disclosure is connected in parallel an electricity in the main operating voltage input terminal and ground terminal of concatenated every level-one chip
Clamp circuit is pressed, or the main operating voltage input terminal between adjacent every level-one chip connects a voltage clamp circuit, leads to
Cross adjustment dynamic current in real time, it is ensured that the operating voltage of every level-one chip is relatively stable in series circuit, improves series circuit
Reliability.
Detailed description of the invention
In order to illustrate more clearly of the embodiment of the present disclosure or technical solution in the prior art, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is this public affairs
The some embodiments opened to those skilled in the art without any creative labor, can be with
It obtains other drawings based on these drawings.
Fig. 1 is the structural schematic diagram for the series circuit that embodiment of the present disclosure first aspect provides；
Fig. 2 is the electricity of the voltage clamp circuit 40 of first embodiment in the series circuit of embodiment of the present disclosure first aspect
Road schematic diagram；
Fig. 3 is the electricity of the voltage clamp circuit 40 of second embodiment in the series circuit of embodiment of the present disclosure first aspect
Road schematic diagram；
Fig. 4 is the structural schematic diagram for the series circuit that embodiment of the present disclosure second aspect provides；
Fig. 5 is the circuit diagram of voltage clamp circuit 60 in the series circuit of embodiment of the present disclosure second aspect；
Fig. 6 is the structural schematic diagram for the circuit board 100 that the embodiment of the present disclosure third aspect provides；
Fig. 7 is the structural schematic diagram for the calculating equipment 200 that embodiment of the present disclosure fourth aspect provides.
Specific embodiment
The characteristics of in order to more fully hereinafter understand the embodiment of the present disclosure and technology contents, with reference to the accompanying drawing to this public affairs
The realization for opening embodiment is described in detail, appended attached drawing purposes of discussion only for reference, is not used to limit the embodiment of the present disclosure.
In technical description below, for convenience of explanation for the sake of, disclosed embodiment is fully understood with providing by multiple details.
However, one or more embodiments still can be implemented in the case where without these details.It in other cases, is simplification
Attached drawing, well known construction and device can simplify displaying.
Fig. 1 is the structural schematic diagram for the series circuit that embodiment of the present disclosure first aspect provides.As shown in Figure 1, the series connection
Circuit includes:
The chip 10 of at least one set of N grades of series connection, wherein each chip has main operating voltage input terminal (in such as figure
V1, V2 ..., shown by Vn), back work voltage input end (V1 ', V2 ' ..., Vn in such as figure ' is shown) and ground terminal (Vss),
Wherein, N, n are the integer greater than 1；
N step voltage clamp circuit 40 corresponding with the chip that described N grades is connected in series, wherein every voltage order one clamp circuit
First voltage input terminal and second voltage input terminal be connected in parallel in the ground terminal and main operating voltage input terminal of chip at the same level,
For stablizing the main operating voltage of every level-one chip.
In present embodiment, which can be one group of series chip group, or be also possible to two groups or two groups with
On series chip group, be connected in parallel between series chip group.By taking the power supply of hexad (i.e. N=6) chip-in series as an example, each
The main operating voltage of chip is generally 1.5V, and external power supply end VCC1 provides 12V DC voltage, and main DC-DC power source is by 12V DC
Voltage is converted to main operating voltage of the 9V as the 6th grade of (superlative degree) chip, it is assumed that the internal resistance of each chip is identical, each chip
Main operating voltage be 1/6*9V, then the voltage value for inputing to the main operating voltage input terminal of each chip successively successively decreases, i.e.,
9V, 7.5V, 6V, 4.5V, 3V, 1.5V can provide the main operating voltage of equilibrium of 1.5V in this way on each chip.
It, can not when series chip quantity increases but in fact, the internal resistance due to series chip is not fully identical
Guarantee that the main operating voltage on each chip is completely the same, so as to will lead to some chip cisco unity malfunctions or even burn
The case where occur.In order to solve this problem, the present embodiment is correspondingly arranged multilevel voltage for the chip of plural serial stage connection
Clamp circuit 1-N, every voltage order one clamp circuit are connected in the main operating voltage input terminal and ground terminal of every level-one chip in parallel,
Clamping action based on the voltage clamp circuit, so that the main operating voltage of every level-one chip is maintained at stable operating voltage
Value improves series circuit to ensure that the main stable operating voltage inputted on each chip in the series chip is balanced
Reliability.
In some alternative embodiments, the series circuit can also include:
Main DC-DC power source 20 (i.e. main DC-DC circuit in Fig. 1), wherein the voltage input end of the main DC-DC power source connects
External dc voltage VCC1 is met, the main operating voltage input terminal of highest chip N connects the voltage output of the main DC-DC power source
End, the ground terminal of every level-one chip are connected with the main operating voltage input terminal of next stage chip, the ground terminal of lowermost level chip 1
Vss connection ground GND, to be respectively that every level-one chip provides main work electricity via the main operating voltage input terminal of every level-one chip
Pressure；
N grades of auxiliary DC-DC power source 30 corresponding with the chip that described N grades is connected in series, wherein every level-one auxiliary DC-DC electricity
The voltage input end in source (i.e. auxiliary DC-DC circuit in Fig. 1) is connected to the external dc voltage VCC1, every level-one auxiliary
The ground terminal of DC-DC power source is respectively connected to the ground terminal of chip at the same level, and the voltage output end of every level-one auxiliary DC-DC power source connects
It is connected to the back work voltage input end of chip at the same level, to be respectively via the back work voltage input end of every level-one chip
Every level-one chip provides back work voltage.
In some alternative embodiments, which can also be correspondingly arranged for every voltage order one clamp circuit 40
Low pressure difference linearity voltage regulation unit (LDO) 50, LDO unit 50 receives the DC voltage of external dc voltage VCC2, turns through overvoltage
It is changed to every voltage order one clamp circuit 40 and operating voltage is provided.
Fig. 2 is the circuit diagram of voltage clamp circuit 40 in the series circuit of embodiment of the present disclosure first aspect.Such as Fig. 2
Shown, which includes: operational amplifier OP and metal-oxide-semiconductor M1, the normal phase input end warp of operational amplifier OP
First voltage input terminal Vn-1 is connected to by first resistor R1, is connected to second voltage input terminal Vn via second resistance R2, it should
The inverting input terminal of operational amplifier OP is connected to first voltage input terminal Vn-1 via a voltage-stabiliser tube D1, via 3rd resistor R3
It is connected to second voltage input terminal Vn, the output end of the operational amplifier is connected to the inverting input terminal via first capacitor C1；
The grid of the metal-oxide-semiconductor M1 is connected to the output end of operational amplifier OP, and source electrode is connected to first voltage input terminal Vn-1,
Drain electrode is connected to second voltage input terminal Vn.
In present embodiment, inverting input terminal, structure are connected to via first capacitor C1 by the output end of operational amplifier
At negative-feedback circuit.When the second voltage input terminal Vn and first voltage input terminal Vn-1 of the voltage clamp circuit are connected in parallel on respectively
The main operating voltage input terminal and ground terminal of chip N, when the voltage difference (Vn subtracts the difference that Vn-1 is obtained) at chip both ends is more than
When preset difference value (such as 1.5V), the inverting input terminal voltage of operational amplifier OP is higher than normal phase input end voltage, then exporting
The output voltage at end passes through the effect of first capacitor C1 and voltage-stabiliser tube D1, can be by the inverting input terminal voltage of operational amplifier OP
It tends towards stability；Also, the internal resistance of metal-oxide-semiconductor M1 can be 0~∞ (being short-circuited to open circuit), connect operational amplifier OP by its grid
Output voltage, internal resistance accordingly changes, so that (Vn subtracts Vn-1 and obtains the voltage difference at chip both ends when chip internal resistance increases
Difference) when being more than preset difference value (such as 1.5V), by changing the internal resistance of metal-oxide-semiconductor, can make voltage clamp circuit etc.
The resistance after internal resistance and chip internal resistance parallel connection is imitated, it is suitable with the internal resistance of other series chips, to realize every in series chip
The voltage clamping of a chip, it is ensured that the voltage of every grade of chip is relatively stable.Here it is illustrated by taking 40~N of voltage clamp circuit as an example
To the voltage clamping of 10~N of chip, for other chips 10~1,10~2 ..., the voltage clamping implementation of 10~N-1 with
10~N is consistent, is realized respectively by the voltage clamp circuit of each chip corresponding grade, for example, 10~1 corresponding voltage clamper electricity of chip
Road 40~1, details are not described herein.
In present embodiment, voltage clamp circuit implementation has abandoned existing Buck conversion circuit (Buck electricity
Road), and output voltage control is realized without programming outside additional piece, by adjusting dynamic current in real time, realize series electrical
The voltage clamping of every level-one chip in road, realization is relatively easy, and efficiency is relatively high, and cost is also accordingly reduced.
In some alternative embodiments, the resistance value of first resistor R1 and second resistance R2 can be several kilohms；The
The resistance value of three resistance R3 can be several hundred ohms.The capacitance of first capacitor C1 can be 0.22 μ f or so.
In some alternative embodiments, as shown in Fig. 2, two feeder ears of operational amplifier OP are respectively connected to
External dc voltage Vo and first voltage input terminal Vn-1.
In some alternative embodiments, the voltage difference of external dc voltage Vo and first voltage input terminal Vn-1
For a predetermined value.For example, the predetermined value can be 4.5V.
Fig. 3 is the circuit signal of the voltage clamp circuit 40 of second embodiment in the series circuit of disclosure first aspect
Figure.On circuit base shown in Fig. 2, the voltage clamp circuit 40 of the present embodiment, as shown in figure 3, the two of first capacitor C1
End can also be connected in parallel a RC series circuit, which includes the 4th resistance R4 and the second capacitor being connected in series
C2.In the embodiment, by the parallel connection RC series circuit on first capacitor C1, negative feedback loop medium-high frequency can be filtered out and made an uproar
Sound realizes the effect of filtering.
Fig. 4 is the structural schematic diagram for the series circuit that embodiment of the present disclosure second aspect provides.As shown in figure 4, the series connection
Circuit includes:
The chip 10 of at least one set of N grades of series connection, wherein each chip has main operating voltage input terminal (in such as figure
V1, V2 ..., shown by Vn), back work voltage input end (V1 ', V2 ' ..., Vn in such as figure ' is shown) and ground terminal (Vss),
Wherein, N, n are the integer greater than 1；
N-1 step voltage clamp circuit 60 corresponding with the chip that described N grades is connected in series, wherein every voltage order one clamper is electric
The voltage output end on road is respectively connected to the main operating voltage input terminal between the chip of adjacent connection, every voltage order one pincers
The voltage input end of position circuit connects external dc voltage VCC3, for stablizing the main operating voltage of every level-one chip.
In present embodiment, which can be one group of series chip group, or be also possible to two groups or two groups with
On series chip group, be connected in parallel between series chip group.By taking the power supply of hexad (i.e. N=6) chip-in series as an example, each
The main operating voltage of chip is generally 1.5V, and external power supply end VCC1 provides 12V DC voltage, and main DC-DC power source is by 12V DC
Voltage is converted to main operating voltage of the 9V as the 6th grade of (superlative degree) chip, it is assumed that the internal resistance of each chip is identical, each chip
Main operating voltage be 1/6*9V, then the voltage value for inputing to the main operating voltage input terminal of each chip successively successively decreases, i.e.,
9V, 7.5V, 6V, 4.5V, 3V, 1.5V can provide the main operating voltage of equilibrium of 1.5V in this way on each chip.
It, can not when series chip quantity increases but in fact, the internal resistance due to series chip is not fully identical
Guarantee that the main operating voltage on each chip is completely the same, so as to will lead to some chip cisco unity malfunctions or even burn
The case where occur.In order to solve this problem, the present embodiment is correspondingly arranged multilevel voltage for the chip of plural serial stage connection
Clamp circuit, the voltage output end of every voltage order one clamp circuit are respectively connected to the main work between the chip of adjacent connection
Make voltage input end, the clamping action based on the voltage clamp circuit, so that the main operating voltage of every level-one chip is maintained at steady
Fixed operating voltage value improves to ensure that the main stable operating voltage inputted on each chip in the series chip is balanced
The reliability of series circuit.
In some alternative embodiments, the series circuit can also include:
Main DC-DC power source 20, wherein the voltage input end of the main DC-DC power source connects external dc voltage VCC1, most
The main operating voltage input terminal of high end chip N connects the voltage output end of the main DC-DC power source, the ground terminal of every level-one chip
It is connected with the main operating voltage input terminal of next stage chip, the ground terminal Vss connection ground GND of lowermost level chip 1, thus via every
The main operating voltage input terminal of level-one chip is respectively that every level-one chip provides main operating voltage；
N grades of auxiliary DC-DC power source 30 corresponding with the chip that described N grades is connected in series, wherein every level-one auxiliary DC-DC electricity
The voltage input end in source is connected to the external dc voltage VCC1, and the ground terminal of every level-one auxiliary DC-DC power source is separately connected
To the ground terminal of chip at the same level, the voltage output end of every level-one auxiliary DC-DC power source is connected to the back work electricity of chip at the same level
Input terminal is pressed, to be respectively that every level-one chip provides back work electricity via the back work voltage input end of every level-one chip
Pressure.
Fig. 5 is the circuit diagram of voltage clamp circuit 60 in the series circuit of embodiment of the present disclosure second aspect.Such as Fig. 5
Shown, which includes: application condition unit 601, PWM generation unit 602, metal-oxide-semiconductor driving unit 603, MOS
Pipe unit 604 (i.e. metal-oxide-semiconductor 604 in Fig. 5).
Application condition unit 601 receives the output voltage Vout and external dc voltage of the metal-oxide-semiconductor unit 604 respectively
VCC3, and the application condition signal of the output voltage Vout and external dc voltage VCC3 is exported to the PWM generation unit
602, the PWM generation unit 602 is based on the application condition signal and generates pwm signal, controls the metal-oxide-semiconductor driving unit
The 603 driving metal-oxide-semiconductor units 604 adjust the output voltage Vout.Wherein, the output voltage of the voltage clamp circuit 60
Vout is connected to main operating voltage input terminal between the chip of adjacent connection.
In present embodiment, metal-oxide-semiconductor unit 604 has sourcing current (source) and sink current (sink) effect, works as voltage
The output voltage Vout of clamp circuit 60 is connected to the main operating voltage input terminal Vn-1 between the chip N and N-1 of adjacent connection,
The voltage Vn-1 of main operating voltage input terminal Vn-1 feeds back to application condition unit 601, through the external dc voltage with acquisition
VCC3 is compared, and when the voltage difference of VCC3 and Vn-1 is more than preset difference value, controls the MOS by PWM generation unit 602
Pipe driving unit 603 drives the metal-oxide-semiconductor unit 604 to execute sourcing current, to increase the output voltage Vout.Conversely, working as
When the voltage difference of VCC3 and Vn-1 is lower than preset difference value, the metal-oxide-semiconductor driving unit 603 is controlled by PWM generation unit 602 and is driven
It moves the metal-oxide-semiconductor unit 604 and executes sink current, to reduce the output voltage Vout.To by adjusting dynamic electric in real time
Stream can make the main operating voltage Vn-1 between the chip N and N-1 of adjacent connection keep stablizing.Here by taking Vn-1 as an example into
Gone explanation, for V1, V2 ..., the clamper principle of Vn-2 it is consistent with Vn-1, details are not described herein.In this way, by connecting step by step
Voltage clamp circuit 60 between adjacent chips, may be implemented the voltage clamping of each chip in series chip, it is ensured that every grade
The voltage of chip is relatively stable.
In present embodiment, voltage clamp circuit implementation realizes output voltage control without programming outside additional piece,
By adjusting dynamic current in real time, the voltage clamping of every level-one chip in series circuit is realized, realization is relatively easy, and efficiency is opposite
Higher, cost is also accordingly reduced.
In some alternative embodiments, which can also include normalization circuit unit 605-1
And 605-2.Wherein, normalization circuit unit 605-1 is used for the external dc voltage for being input to the application condition unit 601
VCC3 carries out sampling and normalized.Normalization circuit unit 605-2 is used for being input to the defeated of the application condition unit
Voltage Vout carries out sampling and normalized out.
In some alternative embodiments, normalization circuit unit 605-1 and 605-2 includes bleeder circuit unit,
For carrying out voltage division processing to the external dc voltage VCC3 and output voltage Vout that are input to the application condition unit 601.
Fig. 6 is the structural schematic diagram for the circuit board 100 that the embodiment of the present disclosure third aspect provides.As shown in fig. 6, the disclosure
The circuit board 100 of embodiment includes the series circuit of aforementioned any embodiment.
Fig. 7 is the structural schematic diagram for the calculating equipment 200 that embodiment of the present disclosure fourth aspect provides.As shown in fig. 7, this public affairs
The calculating equipment 200 for opening embodiment includes the series circuit of aforementioned any embodiment.
In present embodiment, calculates equipment and generally can be and be arbitrarily able to carry out the computer of calculating task or other terminals are set
It is standby, this is not limited in any way.
When in the disclosure, although term " first ", " second " etc. may be used in the disclosure to describe respectively
Element, but these elements should not be limited by these terms.These terms are only used to by an element and another element region
It does not open.For example, first element can be called second element, and similarly in the case where not changing the meaning of description, second
Element can be called first element, as long as " second yuan that " first element " occurred is unanimously renamed and occurred
Part " unanimously renames.First element and second element are all elements, but can not be identical element.
Word used in the disclosure is only used for description embodiment and is not used in limitation claim.Such as embodiment with
And used in the description of claim, unless context clearly illustrates, otherwise "one" (a) of singular, "one"
(an) and " described " (the) is intended to include equally plural form.Similarly, the term "and/or" as used in the disclosure
Refer to comprising one or more associated any and all possible combinations listed.In addition, when being used for the disclosure
When middle, term " includes " (comprise) and its modification " comprising " (comprises) and/or refer to including (comprising) etc. old
The presence of feature, entirety, step, operation, element and/or the component stated, but be not excluded for one or more other features,
Entirety, step, operation, element, component and/or these grouping presence or addition.
Various aspects, embodiment, realization or feature in described embodiment can be used alone or in any combination
Mode use.
Above-mentioned technical description can refer to attached drawing, these attached drawings form a part of this disclosure, and by description attached
The embodiment according to described embodiment is shown in figure.Although the description of these embodiments is enough in detail so that this field
Technical staff can be realized these embodiments, but these embodiments are non-limiting；Other implementations thus can be used
Example, and variation can also be made in the case where not departing from the range of described embodiment.For example, described in flow chart
Operation order be non-limiting, therefore in flow charts illustrate and according to flow chart description two or more behaviour
The sequence of work can be changed according to several embodiments.As another example, in several embodiments, it explains in flow charts
It releases and is optional or deletable according to one or more operations that flow chart describes.In addition, certain steps or
Function can be added in the disclosed embodiments or more than two sequence of steps are replaced.All these variations are considered
Included in the disclosed embodiments and claim.
In addition, using term to provide the thorough understanding of described embodiment in above-mentioned technical description.However, and being not required to
Will excessively detailed details to realize described embodiment.Therefore, the foregoing description of embodiment be in order to illustrate and describe and
It presents.The embodiment and example disclosed according to these embodiments presented in foregoing description is provided separately, with
Addition context simultaneously helps to understand described embodiment.Description above, which is not used in, accomplishes exhaustive or by described reality
Apply the precise forms that example is restricted to the disclosure.According to the above instruction, it is several modification, selection be applicable in and variation be feasible.?
In some cases, processing step well known is not described in avoid described embodiment is unnecessarily influenced.
Finally, it should be noted that the above various embodiments is only to illustrate the technical solution of the disclosure, rather than its limitations；To the greatest extent
Pipe is described in detail the disclosure referring to foregoing embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, each embodiment technology of the disclosure that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (12)
1. a kind of series circuit characterized by comprising
The chip of at least one set of N grades of series connection, each chip have main operating voltage input terminal, back work voltage defeated
Enter end and ground terminal；
N step voltage clamp circuit corresponding with the chip that described N grades is connected in series, wherein the first of every voltage order one clamp circuit
Voltage input end and second voltage input terminal are connected in parallel in the ground terminal and main operating voltage input terminal of chip at the same level, for steady
The main operating voltage of fixed every level-one chip；Wherein, N is the integer greater than 1.
2. series circuit according to claim 1, which is characterized in that the voltage clamp circuit include operational amplifier and
The normal phase input end of metal-oxide-semiconductor, the operational amplifier is connected to first voltage input terminal via first resistor, via second resistance
It is connected to second voltage input terminal, the inverting input terminal of the operational amplifier is connected to first voltage input via a voltage-stabiliser tube
End is connected to second voltage input terminal via 3rd resistor, and the output end of the operational amplifier is connected via first capacitor device
To the inverting input terminal；The grid of the metal-oxide-semiconductor is connected to the output end of the operational amplifier, and source electrode is connected to described
One voltage input end, drain electrode are connected to the second voltage input terminal.
3. series circuit according to claim 2, which is characterized in that the both ends of the first capacitor device are connected in parallel RC string
Join circuit, the RC series circuit includes the 4th resistance and the second capacitor being connected in series.
4. series circuit according to claim 2 or 3, which is characterized in that two feeder ears of the operational amplifier point
It is not connected to the first external dc voltage and the first voltage input terminal.
5. series circuit according to claim 4, which is characterized in that first external dc voltage and first voltage are defeated
The voltage difference for entering end is a predetermined value.
6. series circuit according to claim 5, which is characterized in that the series circuit further include: with the N step voltage
The corresponding low pressure difference linearity voltage regulation unit of clamp circuit, the low pressure difference linearity voltage regulation unit convert the second external dc voltage
For the first external dc voltage.
7. a kind of series circuit characterized by comprising
The chip of at least one set of N grades of series connection, each chip have main operating voltage input terminal, back work voltage defeated
Enter end and ground terminal；
N-1 step voltage clamp circuit corresponding with the chip that described N grades is connected in series, wherein the electricity of every voltage order one clamp circuit
Press the main operating voltage input terminal of output end being respectively connected between the chip of adjacent connection, every voltage order one clamper electricity
The voltage input end on road connects the first external dc voltage, for stablizing the main operating voltage of every level-one chip.
8. series circuit according to claim 7, it is characterised in that: the voltage clamp circuit includes application condition list
Member, PWM generation unit, metal-oxide-semiconductor driving unit, metal-oxide-semiconductor unit, the application condition unit receive the metal-oxide-semiconductor unit respectively
Output voltage and first external dc voltage, and export the error ratio of the output voltage and the first external dc voltage
The PWM generation unit is given compared with signal, the PWM generation unit is based on the application condition signal and generates pwm signal, controls institute
Stating metal-oxide-semiconductor driving unit drives the metal-oxide-semiconductor unit to export the output voltage, wherein the output voltage is connected to adjacent company
Main operating voltage input terminal between the chip connect.
9. series circuit according to claim 8, it is characterised in that: the voltage clamp circuit further includes that at least one is returned
One changes circuit unit, for being input to output voltage described in the application condition unit and the first external dc voltage is returned
One change processing.
10. series circuit according to claim 9, it is characterised in that: the normalization circuit unit includes bleeder circuit
Unit, for carrying out voltage division processing to being input to output voltage described in the application condition unit and the first external dc voltage.
11. a kind of circuit board, it is characterised in that: the circuit board includes the described in any item series circuits of claim 1-10.
12. a kind of calculating equipment, it is characterised in that: the calculating equipment includes the described in any item series electricals of claim 1-10
Road.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2018/112547 WO2020087247A1 (en) | 2018-10-30 | 2018-10-30 | Series circuit, circuit board and computing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109565242A true CN109565242A (en) | 2019-04-02 |
Family
ID=65872584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201880002433.7A Pending CN109565242A (en) | 2018-10-30 | 2018-10-30 | Series circuit, circuit board and calculating equipment |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109565242A (en) |
| WO (1) | WO2020087247A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111007300A (en) * | 2019-12-26 | 2020-04-14 | 深圳杰微芯片科技有限公司 | Method and device for detecting voltage of series circuit and storage medium |
| CN111857224A (en) * | 2020-07-31 | 2020-10-30 | 深圳君略科技有限公司 | Multistage chip series circuit and driving system |
| CN113258752A (en) * | 2021-06-07 | 2021-08-13 | 深圳市永联科技股份有限公司 | Dynamic control method and system of circuit signal and power module |
| CN113346468A (en) * | 2020-03-02 | 2021-09-03 | 蜜蜂计算(香港)股份有限公司 | Multistage series circuit power supply device and mining machine thereof |
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| CN101763134A (en) * | 2010-02-02 | 2010-06-30 | 浙江南瑞科技有限公司 | Parallel voltage stabilizing circuit |
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| CN107947566A (en) * | 2017-12-21 | 2018-04-20 | 北京比特大陆科技有限公司 | Series-fed circuit, method and computing device |
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| CN111007300A (en) * | 2019-12-26 | 2020-04-14 | 深圳杰微芯片科技有限公司 | Method and device for detecting voltage of series circuit and storage medium |
| CN113346468A (en) * | 2020-03-02 | 2021-09-03 | 蜜蜂计算(香港)股份有限公司 | Multistage series circuit power supply device and mining machine thereof |
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| CN113258752A (en) * | 2021-06-07 | 2021-08-13 | 深圳市永联科技股份有限公司 | Dynamic control method and system of circuit signal and power module |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020087247A1 (en) | 2020-05-07 |
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Application publication date: 20190402 |