CN109564893B - 半导体芯片 - Google Patents

半导体芯片 Download PDF

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CN109564893B
CN109564893B CN201780047180.0A CN201780047180A CN109564893B CN 109564893 B CN109564893 B CN 109564893B CN 201780047180 A CN201780047180 A CN 201780047180A CN 109564893 B CN109564893 B CN 109564893B
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nanowires
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CN109564893A (zh
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新保宏幸
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Socionext Inc
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Abstract

半导体芯片(1)具有第一块(100)和第二块(400)，第一块(100)包括具有纳米线FET的标准单元(110)，第二块(400)包括纳米线FET。在第一块和第二块(100、400)中，沿X方向延伸的纳米线(111、411)在Y方向上的布置中心间距是中心间距P1的整数倍，焊盘(112，412)在X方向上的布置中心间距是中心间距P2的整数倍。由此对采用了纳米线FET的半导体芯片提供对制造的容易化有效的版图结构。

Description

半导体芯片
技术领域
本公开涉及一种包括采用了纳米线FET(Field Effect Transistor，场效应晶体管)的标准单元的半导体芯片。
背景技术
已知：作为在半导体衬底上形成半导体集成电路的方法有标准单元方式。标准单元方式指的是以下方式，即事先将具有特定逻辑功能的基本单元(例如反相器、锁存器、触发器、全加器等)作为标准单元准备好，然后将多个标准单元布置在半导体衬底上，再用布线将这些标准单元连接起来，这样来设计LSI芯片的一种方式。
LSI的基本构成要素即晶体管通过缩小栅极长度(scaling，按比例缩小)而实现了集成度的提高、工作电压的降低以及工作速度的提高。但是，近年来，出现的问题是过度地按比例缩小会引起截止电流和功耗显著增大。为了解决该问题，人们已开始积极对立体构造晶体管进行研究，即将晶体管构造从现有的平面型变为立体型。作为立体构造晶体管之一，纳米线FET备受瞩目。
非专利文献1、2中公开了纳米线FET的制造方法之例。
非专利文献1：S.Bangsaruntip，et al.“High performance and highly uniformgate-all-around silicon nanowire MOSFETs with wire size dependent scaling”，Electron Devices Meeting(IEDM)，2009IEEE International
非专利文献2：Isaac Laucer，et al.“Si Nanowire CMOS Fabricated withMinimal Deviation fromRMG Fin FET Technology Showing Record Performance”，2015Symposium on VLSI Technology Digest of Technical Papers
发明内容
-发明要解决的技术问题-
到目前为止，还没有人对采用了纳米线FET的标准单元的构造、采用了纳米线FET的半导体集成电路的版图(layout)做具体的研究。
本公开对采用了纳米线FET的半导体芯片提供对制造的容易化有效的版图结构。
-用以解决技术问题的技术方案-
本公开的第一方面为一种半导体芯片，其具有第一块和第二块，所述第一块包括具有纳米线FET(Field Effect Transistor，场效应晶体管)的标准单元，所述第二块包括纳米线FET，所述第一块和所述第二块所包括的纳米线FET分别具有：沿第一方向延伸的一条或并排设置的多条纳米线；一对焊盘，一对所述焊盘分别设在所述纳米线的所述第一方向上的两端且下表面位于比所述纳米线的下表面低的位置上，并与所述纳米线相连接；以及栅极电极，所述栅极电极沿与所述第一方向垂直的第二方向延伸，且被设为在所述纳米线的所述第一方向上的规定范围内包围所述纳米线的周围，在所述第一块和所述第二块中，所述纳米线在所述第二方向上的布置中心间距是规定的第一中心间距的整数倍，所述焊盘在所述第一方向上的布置中心间距是规定的第二中心间距的整数倍。
根据上述方面，半导体芯片具有第一块和第二块，第一块包括具有纳米线FET的标准单元，第二块包括纳米线FET。在第一块和第二块中，沿第一方向延伸的纳米线在栅极电极所延伸的方向即第二方向上的布置中心间距是规定的第一中心间距的整数倍，焊盘在第一方向上的布置中心间距是规定的第二中心间距的整数倍。利用上述结构，在半导体芯片中，纳米线和焊盘的布置的规律性就得到提高。因此，半导体芯片的制造就会变得容易，并且能够抑制制造偏差和提高成品率。
本发明的第二方面是一种半导体芯片，其具有第一块和第二块，所述第一块包括具有纳米线FET(Field Effect Transistor，场效应晶体管)的标准单元，所述第二块包括纳米线FET，所述第一块和所述第二块所包括的纳米线FET分别具有：沿第一方向延伸的一条或并排设置的多条纳米线；一对焊盘，一对所述焊盘分别设在所述纳米线的所述第一方向上的两端且下表面位于比所述纳米线的下表面低的位置上，并与所述纳米线相连接；以及栅极电极，所述栅极电极沿与所述第一方向垂直的第二方向延伸，且被设为在所述纳米线的所述第一方向上的规定范围内包围所述纳米线的周围，在所述第一块和所述第二块所包括的纳米线FET中的至少一个所述纳米线FET中，沿与所述第一方向和所述第二方向垂直的第三方向布置有多条所述纳米线，在所述第一块和所述第二块中，所述纳米线在所述第二方向上的布置中心间距是规定的第一中心间距的整数倍，并且，在所述第三方向上的布置中心间距是规定的纳米线堆叠中心间距的整数倍。
根据上述方面，半导体芯片具有第一块和第二块，第一块包括具有纳米线FET的标准单元，第二块包括纳米线FET。在第一块和第二块中，沿第一方向延伸的纳米线在栅极电极所延伸的方向即第二方向上的布置中心间距(pitch)是规定的第一中心间距的整数倍，在与第一方向和第二方向垂直的第三方向上的布置中心间距是规定的纳米线堆叠中心间距(stack pitch)的整数倍。利用上述结构，在半导体芯片中，纳米线的布置的规律性就得到提高。因此，半导体芯片的制造就会变得容易，并且能够抑制制造偏差和提高成品率。
-发明的效果-
根据本公开，在采用了纳米线FET的半导体集成电路装置中，纳米线和焊盘的布置的规则性得到提高，因此制造偏差被抑制，能够提高成品率。
附图说明
图1是示意性俯视图，示出实施方式所涉及的半导体芯片的版图结构例。
图2是俯视图，示出具有纳米线FET的标准单元的版图结构例。
图3是图1的版图结构的示意性剖视图。
图4是图1的版图结构的示意性剖视图。
图5是示出实现图1的版图结构的单元布置过程的图。
图6是图2的标准单元的结构的变形例。
图7是示意图，示出纳米线FET的基本构造。
图8是示意图，示出纳米线FET的基本构造。
具体实施方式
下面，参照附图对实施方式做说明。在以下实施方式中，半导体芯片包括多个标准单元，上述的多个标准单元中的至少一部分标准单元包括纳米线FET(Field EffectTransistor)。
图7是示意图，示出纳米线FET的基本构造例(也称为栅绕式(GAA：Gate AllAround)FET)。纳米线FET是使用了供电流流动的细线(纳米线)的FET。纳米线例如由硅形成。如图7所示，纳米线在衬底上沿着水平方向延伸，即平行于衬底延伸，其两端连接在成为纳米线FET的源极区和漏极区的构造物上。在本申请说明书中，将纳米线FET中连接在纳米线的两端上且成为纳米线FET的源极区和漏极区的构造物称为焊盘(pad)。图7中，在硅衬底上形成有STI(Shallow Trench Isolation，浅沟道隔离)，硅衬底在纳米线的下方(加了斜线的部分)露出。需要说明的是，实际存在加了斜线的部分被热氧化膜等覆盖的情况，但在图7中，为了简化而省略图示热氧化膜等。
纳米线的周围例如被由多晶硅形成的栅极电极围绕一圈，纳米线与栅极电极之间设置有氧化硅膜等绝缘膜。焊盘和栅极电极形成在衬底表面上。根据该构造，因为纳米线的沟道区的上部、两侧部以及下部全被栅极电极围起来，所以能够在沟道区产生均匀的电场，由此，FET的开关特性良好。
需要说明的是，焊盘中的至少连接有纳米线的部分成为源极区/漏极区，但有时候，连接有纳米线的部分之下的部分未必会成为源极区/漏极区。而且，有时候，纳米线的一部分(未被栅极电极围起来的部分)会成为源极区/漏极区。
也存在图8所示的情况，即在衬底的上表面上形成有BOX(Buried OXide，隐埋氧化物)，并在该BOX上形成有纳米线FET。
在图7和图8的构造中，两条纳米线沿与衬底面垂直的方向并排设置。换言之，纳米线堆叠成两层。需要说明的是，在与衬底面垂直的方向上，纳米线可以堆叠三层或三层以上，也可以堆叠一层。在同一半导体芯片上，可以混合安装纳米线层数不同的纳米线FET。在图7和图8中，SP是堆叠成多层的纳米线的中心间距离，即，在与衬底面垂直的方向上的纳米线的中心间距(纳米线堆叠中心间距)。在图7和图8中，最上侧的纳米线的上端与焊盘的上端高度齐平。不过，不需要使它们的高度齐平，焊盘的上端比最上侧的纳米线的上端高也无妨。
图1是示意性俯视图，示出实施方式所涉及的半导体芯片的版图结构例。在图1中，将附图横向定为X方向(相当于第一方向)，将附图纵向定为Y方向(相当于第二方向)。并且，在图1中，示出沿X方向延伸且以中心间距P1(相当于第一中心间距)并排布置的格栅线L1和沿Y方向延伸且以中心间距P2(相当于第二中心间距)并排布置的格栅线L2。不过，在实际的半导体芯片上，是看不到格栅线L1、L2的。在图1中，纳米线FET T1、T2的纳米线111、411沿X方向延伸且对齐格栅线L1布置。其他纳米线FET的纳米线也同样是沿X方向延伸且对齐格栅线L1布置。纳米线FET T1、T2的焊盘112、412沿Y方向分开形成且以与格栅线L2对齐的方式布置。其他纳米线FET的焊盘也同样是沿Y方向分开形成且以与格栅线L2对齐的方式布置。需要说明的是，在图1中，局部布线、导通孔(via)和金属布线等省略图示。
图1的半导体芯片1具有矮标准单元块100、高标准单元块200、存储块300、模拟块400和IO块500。矮标准单元块100具有单元高度(在Y方向上的尺寸)相对较矮的矮标准单元110。高标准单元块200具有单元高度相对较高的高标准单元210。在图1中，矮标准单元110的纳米线FET的纳米线分别在Y方向上并排设有三排，三个焊盘在Y方向上分开设置，并分别与各排纳米线相连接。高标准单元210的纳米线FET的纳米线分别在Y方向上并排设有五排，五个焊盘在Y方向上分开设置，并分别与各排纳米线相连接。矮标准单元110的单元高度是中心间距P1的8倍即(P1×8)，高标准单元210的单元高度是中心间距P1的12倍即(P1×12)。
存储块300具有存储单元310，并实现SRAM(Static Random Access Memory)和DRAM(Dynamic Random Access Memory)等的存储功能。存储单元310构成存储单元阵列。存储块300除了包括存储单元310以外，还包括灵敏放大器(sense amplifier)和解码器等***电路。模拟块400具有模拟单元410，模拟块400实现DAC(Digital Analog Converter)、ADC(Analog Digital Converter)、PLL(Phase Locked Loop)等的模拟功能。需要说明的是，在模拟块400中，有时会混合设置有模拟电路和数字电路。IO块500具有IO组件单元510，且向半导体芯片1的外部输出信号或从半导体芯片1的外部输入信号。IO块500包括电平移位器、ESD(Electro-Static Discharge)电路、输入输出缓冲器等电路。
在图1中，存储单元310的纳米线FET的纳米线分别沿Y方向并排设有两排，两个焊盘沿Y方向分开设置，并分别与各排纳米线相连接。模拟单元410的纳米线FET的纳米线分别沿Y方向并排设有四排，四个焊盘沿Y方向上分开设置，并分别与各排纳米线相连接。IO组件单元510的纳米线FET的纳米线分别沿Y方向并排设有十四排，十四个焊盘沿Y方向分开设置，并分别与各排纳米线相连接。存储单元310的单元高度是中心间距Pl的6倍即(Pl×6)，模拟单元410的单元高度是中心间距P1的10倍即(P1×10)，IO组件单元510的单元高度是中心间距P1的15倍即(P1×15)。
图2是俯视图，示出具有纳米线FET的标准单元的版图结构例。在图2中，还示出局部布线和金属布线。图2所示的标准单元利用纳米线FET构成具有输入A和输出Y的反相器。在P型半导体区PA设有P型纳米线FET P1，在N型半导体区NA设有N型纳米线FET N1。纳米线FET P1、N1分别具有沿X方向延伸的并排设置的多条纳米线11、12。此处，若纳米线11、12分别在Y方向上并排设有四排，在纵向即与衬底垂直的方向并排设有两排，则纳米线11、12分别合计为八条。纳米线11、12呈圆柱状，在衬底上沿着水平方向延伸，即平行于衬底延伸，且例如由硅形成。还设有与纳米线11相连接的一对焊盘21、22和与纳米线12相连接的一对焊盘23、24。P型杂质注入至焊盘21、22中的至少与纳米线11连接的部分中，该部分成为纳米线FET P1的源极区或漏极区。N型杂质注入至焊盘23、24中的至少与纳米线12连接的部分中，该部分成为纳米线FET N1的源极区或漏极区。
此处，焊盘21、22、23、24分别在Y方向上分开形成有四个。焊盘21、22的分开的四个部分分别连接在沿Y方向而设的四条纳米线11上。焊盘23、24的分开的四个部分分别连接在沿Y方向而设的四条纳米线12上。
在图2的标准单元中还布置有沿Y方向直线状延伸的栅极布线31。栅极布线31是将纳米线FET P1的栅极电极31p与纳米线N1的栅极电极31n形成为一体而得到的，栅极布线31被设为：在纳米线11、12的X方向上的规定范围内包围纳米线11、12。在图2的标准单元的单元框CF的侧边上分别布置有沿Y方向延伸的虚设栅极布线33a、33b。
在纳米线FET P1、N1的上层中，设有金属布线层M1。在金属布线层M1中，在单元框CF的上边上布置有供给电源电位的布线VDD，在单元框CF的下边上布置有供给接地电位的布线VSS。在金属布线层M1中还形成有布线41a～41d。布线41a形成为从布线VDD开始沿着Y方向朝下方延伸，且经局部布线(local wiring)45a与焊盘21相连接。布线4lb形成为从布线VSS开始沿着Y方向朝上方延伸，且经局部布线45b与焊盘23相连接。布线41c将焊盘22、24连接起来，且经局部布线45c与焊盘22相连接，经局部布线45d与焊盘24相连接。布线41d经局部布线45e与栅极布线31相连接。布线41c、41d分别与该标准单元所构成的反相器的输出Y、输入A相对应。
需要说明的是，此处，金属布线41a～41d与焊盘21、22、23、24和栅极布线31的连接方式是经局部布线45a、45b、45c、45d、45e和触点43进行的连接。不过，金属布线与焊盘和栅极布线的连接方式还可以不经触点而仅经局部布线进行的连接，也可以是不经局部布线而仅经触点进行的连接。
图3是图1的半导体芯片的A-A线的示意性剖视图，示出矮标准单元块100在X方向上的剖面结构。在图3中，111是纳米线，112是焊盘，113是栅极布线，114是虚设栅极布线。在图3的结构中，纳米线111在Z方向(与衬底面(XY平面)垂直的方向)上以纳米线堆叠中心间距SP堆叠成两层。因此，在晶体管T1中，沿X方向延伸的纳米线111在Y方向上并排布置有三排，在Z方向上并排布置有两排，合计设有六(＝3×2)条纳米线111。
图4是图1的半导体芯片的B-B线的示意性剖视图，示出模拟块400在X方向上的剖面结构。在图4中，411是纳米线，412是焊盘，413是栅极布线，414是虚设栅极布线。在图4的结构中，纳米线411在Z方向上以纳米线堆叠中心间距SP堆叠成三层。因此，在晶体管T2中，沿X方向延伸的纳米线411在Y方向上并排布置有四排，在Z方向上并排布置有三排，合计设有十二(＝4×3)条纳米线411。
如图3和图4所示，金属布线层M1中的布线141经触点143和局部布线145与焊盘112、412相连接。触点143与金属布线层M1中的布线141一起利用双嵌入工艺(Dualdamascene process)形成。需要说明的是，触点143和金属布线层M1中的布线141还可以各自分别形成。金属布线层M1中的布线141例如由Cu形成，在布线141的表面上形成有例如含有钽或氮化钽的阻挡金属(Barrier metal)148。局部布线145例如由钨形成，在局部布线145的表面上形成有例如含有钛或氮化钛的胶(glue)膜147。需要说明的是，局部布线145也可以由钴形成。在该情况下，可以不形成胶膜147。在焊盘112、412的表面上形成有硅化物膜(silicide film)149，该硅化物膜149例如由镍或钴等形成。
层间绝缘膜146a、146b例如是氧化硅膜。层间绝缘膜146c例如是如SiOC或多孔膜等低介电常数膜。需要说明的是，层间绝缘膜146c也可以具有两层或两层以上的叠层构造。
栅极布线113、413例如由多晶硅形成。需要说明的是，栅极布线113、413也可以由氮化钛等含金属的材料形成。栅极绝缘膜例如是氧化硅膜，且例如由热氧化法形成。需要说明的是，栅极绝缘膜也可以由铪、锆、镧、钇、铝、钛或钽的氧化物形成。
由图3和图4的剖视图可知，焊盘112、412的下表面位于比纳米线111、411的下表面低的位置上。纳米线111、411的上表面的高度与焊盘112、412的上表面相同。需要说明的是，纳米线111、411的上表面也可以位于比焊盘112、412的上表面低的位置上。
需要说明的是，虽未图示，但其他块即高标准单元块200、存储块300和IO块500也具有与图3和图4相同的剖面结构。
图5是示出实现图1的半导体芯片1的版图结构的单元布置过程的图。在图5中，示出正在布置高标准单元块200的高标准单元210的状态。在图5中，示出沿X方向延伸且以中心间距P1布置的格栅线L1和沿Y方向延伸且以中心间距P3并排布置的格栅线L3。其中，P3＝P2。格栅线L1与图1所示的格栅线L1相同，但格栅线L3与图1所示的格栅线L2错开半个中心间距。在版图设计中，格栅线L1、L3例如显示到版图设计装置的画面上。
此处，例如矮标准单元110的单元宽度(在X方向上的尺寸)是中心间距P3的2倍，在Y方向上的尺寸即单元高度是中心间距P1的8倍。高标准单元210、存储单元310、模拟单元410和IO组件单元510也一样，它们的单元宽度是中心间距P3的整数倍，它们的单元高度是中心间距P1的整数倍。事先设计好矮标准单元110，使得：若矮标准单元110的外廓与格栅线L1、L3对齐，则沿X方向延伸的纳米线位于格栅线L1上且沿Y方向延伸的栅极位于格栅线L3上。焊盘布置在沿X方向与栅极错开半个中心间距(＝P3/2)的位置上。高标准单元210、存储单元310、模拟单元410和IO组件单元510也采用同样的设计。因此，进行版图设计的设计者通过使各单元的外廓与格栅线L1、L3对齐来布置各单元，就能够容易地设计出图1所示的版图结构。
此处，图1的半导体芯片1例如具有作为第一块的矮标准单元块100和作为第二块的模拟块400，其中，矮标准单元块100包括具有纳米线FET的矮标准单元110，模拟块400包括纳米线FET。在矮标准单元块100和模拟块400中，纳米线在Y方向上的布置中心间距是中心间距P1的整数倍，焊盘在X方向上的布置中心间距是中心间距P2的整数倍。利用上述结构，在半导体芯片1中，纳米线和焊盘的布置的规律性就得到提高。因此，半导体芯片1的制造就会变得容易，并且能够抑制制造偏差和提高成品率。
如图3和图4所示，在矮标准单元块100和模拟块400中，纳米线在Z方向上的布置中心间距是纳米线堆叠中心间距SP的整数倍。利用上述结构，在半导体芯片1中，纳米线的布置的规律性就得到提高。因此，半导体芯片1的制造就会变得容易，并且能够抑制制造偏差和提高成品率。
在矮标准单元块100和模拟块400中，构成栅极电极的栅极布线和虚设栅极布线在X方向上的布置中心间距是中心间距P3的整数倍。利用上述结构，在半导体芯片1中，包括虚设栅极布线的栅极布线的规则性就得到提高。因此，半导体芯片1的制造就会变得容易，并且能够抑制制造偏差和提高成品率。
需要说明的是，在包括高标准单元块200、存储块300和IO块500的半导体芯片1整体中，纳米线在Y方向上的布置中心间距是中心间距P1的整数倍，在Z方向上的布置中心间距是纳米线堆叠中心间距SP的整数倍。焊盘在X方向上的布置中心间距是中心间距P2的整数倍，栅极布线和虚设栅极布线在X方向上的布置中心间距是中心间距P3(＝P2)的整数倍。因此，半导体芯片1的制造就会变得容易，并且能够抑制制造偏差和提高成品率。
需要说明的是，图1等所示的纳米线FET的结构仅为一例，例如，纳米线在Y方向上的条数和在Z方向上的层数、焊盘的尺寸等并不限于此处所示的例子。需要说明的是，根据各个块中所需要的纳米线FET的驱动能力分别决定纳米线的条数即可。
并且，图1所示的标准单元110、210的单元高度不限于此。在图1中，示出两种标准单元的单元高度，但不限于此。例如，还可以在半导体芯片上布置由单元高度相等的标准单元构成的单一标准单元块。
需要说明的是，在以上说明中，纳米线呈圆柱状，但纳米线的形状并不限于此。例如，纳米线的剖面形状还可以是椭圆形、扁圆形，纳米线呈四棱柱状等棱柱状也无妨。
在以上说明中，在纳米线FET中，焊盘是相对于在Y方向上形成的多条纳米线分开形成的。不过，还存在焊盘相对于在Y方向上形成的多条纳米线形成为一体的情况。图6是图2的版图结构例的变形例。在图6中，焊盘21、22、23、24分别相对于设置在Y方向上的各自为四条的纳米线11、12形成为一体。
在以上说明中，栅极布线的中心间距与焊盘的中心间距相等，但并不限于此。而且，将栅极布线设为在整个P型半导体区和N型半导体区沿Y方向直线状延伸，但并不限于此。
-产业实用性-
本公开对采用了纳米线FET的半导体集成电路装置提供对制造的容易化有效的版图结构，故本公开对于提高半导体集成电路装置的性能很有用。
-符号说明-
1 半导体芯片
11、12 纳米线
21、22、23、24 焊盘
31 栅极布线
31p、31n 栅极电极
33a、33b 虚设栅极布线
100 矮标准单元块(第一块)
110 矮标准单元
111 纳米线
112 焊盘
113 栅极布线
114 虚设栅极布线
400 模拟块(第二块)
411 纳米线
412 焊盘
413 栅极布线
414 虚设栅极布线
T1、T2 纳米线FET
P1 第一中心间距
P2 第二中心间距
SP 纳米线堆叠中心间距

Claims (7)

1.一种半导体芯片，其特征在于，
所述半导体芯片具有第一块和第二块，
所述第一块包括具有纳米线FET即场效应晶体管的标准单元，所述第二块包括纳米线FET，
所述第一块和所述第二块所包括的纳米线FET分别具有：
沿第一方向延伸的一条或并排设置的多条纳米线；
一对焊盘，一对所述焊盘分别设在所述纳米线的所述第一方向上的两端且下表面位于比所述纳米线的下表面低的位置上，并与所述纳米线相连接；以及
栅极电极，所述栅极电极沿与所述第一方向垂直的第二方向延伸，且被设为在所述纳米线的所述第一方向上的规定范围内包围所述纳米线的周围，
在所述第一块和所述第二块中，
所述纳米线在所述第二方向上的布置中心间距是规定的第一中心间距的整数倍，
所述焊盘在所述第一方向上的布置中心间距是规定的第二中心间距的整数倍。
2.根据权利要求1所述的半导体芯片，其特征在于，
在所述第一块和所述第二块所包括的纳米线FET中的至少一个所述纳米线FET中，沿与所述第一方向和所述第二方向垂直的第三方向布置有多条所述纳米线，
在所述第一块和所述第二块中，
所述纳米线在所述第三方向上的布置中心间距是规定的纳米线堆叠中心间距的整数倍。
3.根据权利要求1所述的半导体芯片，其特征在于，
在所述第一块和所述第二块中，
构成所述栅极电极的栅极布线和虚设栅极布线在所述第一方向上的布置中心间距是所述第二中心间距的整数倍。
4.根据权利要求1所述的半导体芯片，其特征在于，
所述标准单元在所述第二方向上的尺寸是所述第一中心间距的整数倍。
5.一种半导体芯片，其特征在于，
所述半导体芯片具有第一块和第二块，
所述第一块包括具有纳米线FET即场效应晶体管的标准单元，所述第二块包括纳米线FET，
所述第一块和所述第二块所包括的纳米线FET分别具有：
沿第一方向延伸的一条或并排设置的多条纳米线；
一对焊盘，一对所述焊盘分别设在所述纳米线的所述第一方向上的两端且下表面位于比所述纳米线的下表面低的位置上，并与所述纳米线相连接；以及
栅极电极，所述栅极电极沿与所述第一方向垂直的第二方向延伸，且被设为在所述纳米线的所述第一方向上的规定范围内包围所述纳米线的周围，
在所述第一块和所述第二块所包括的纳米线FET中的至少一个所述纳米线FET中，沿与所述第一方向和所述第二方向垂直的第三方向布置有多条所述纳米线，
在所述第一块和所述第二块中，
所述纳米线在所述第二方向上的布置中心间距是规定的第一中心间距的整数倍，并且，在所述第三方向上的布置中心间距是规定的纳米线堆叠中心间距的整数倍，
所述焊盘在所述第一方向上的布置中心间距是规定的第二中心间距的整数倍。
6.根据权利要求5所述的半导体芯片，其特征在于，
在所述第一块和所述第二块中，
构成所述栅极电极的栅极布线和虚设栅极布线在所述第一方向上的布置中心间距是规定的第二中心间距的整数倍。
7.根据权利要求5所述的半导体芯片，其特征在于，
所述标准单元在所述第二方向上的尺寸是所述第一中心间距的整数倍。
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