CN109545925A - A kind of GaN base light emitting epitaxial wafer and preparation method thereof - Google Patents
A kind of GaN base light emitting epitaxial wafer and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
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Abstract
The invention discloses a kind of GaN base light emitting epitaxial wafers and preparation method thereof, belong to GaN base light emitting field.Buffer layer, undoped GaN layer, n-type doping GaN layer, low temperature stress release layer, shallow well layer, multiple quantum well layer, electronic barrier layer, p-type GaN layer and the p-type contact layer that LED epitaxial slice includes: substrate, is sequentially deposited over the substrate, the low temperature stress release layer is the periodic structure of the first InGaN sublayer and the first GaN sublayer alternating growth, the first InGaN sublayer with a thickness of 1~2nm, the first GaN sublayer with a thickness of 5~10nm, the quantity of the first InGaN sublayer or the first GaN sublayer is 10~30.
Description
Technical field
The present invention relates to GaN base light emitting field, in particular to a kind of GaN base light emitting epitaxial wafer and its system
Preparation Method.
Background technique
GaN (gallium nitride) base LED (Light Emitting Diode, light emitting diode) generally comprises epitaxial wafer and outside
Prolong the electrode of on piece preparation.Epitaxial wafer generally includes: substrate and the GaN base epitaxial layer grown on substrate, epitaxial layer include
The buffer layer of stacked above one another, undoped GaN layer, N-type GaN layer, low temperature stress release layer, MQW (Multiple Quantum
Well, multiple quantum wells) layer, electronic barrier layer, p-type GaN layer and contact layer.When there is electric current to inject GaN base LED, N-type GaN layer
Etc. the electronics of N-type regions and the hole of the p type island regions such as p-type GaN layer enter MQW active area and compound, issue visible light.Wherein, low
Warm stress release layer can be the GaN layer of low-temperature epitaxy.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems: when substrate is blue precious
There are biggish lattice mismatches, and epitaxial layer to be made to accumulate a large amount of stress when stone lining bottom, between GaN and Sapphire Substrate, has one
The component of stress is released in low-temperature epitaxy low temperature stress release layer causes threading dislocation formation V-type hole (V-Pits).In V-type hole
Between threading dislocation center will become the leakage channel of carrier, and then capture least a portion of carrier and form non-radiative recombination
Center causes the luminous efficiency of LED to decline.
Summary of the invention
The embodiment of the invention provides a kind of GaN base light emitting epitaxial wafers and preparation method thereof, can be realized stress
It can effectively stop carrier to enter V-type while release again to cheat to form non-radiative recombination center.The technical solution is as follows:
In a first aspect, providing a kind of GaN base light emitting epitaxial wafer, the LED epitaxial slice includes: lining
Bottom, the buffer layer being sequentially deposited over the substrate, undoped GaN layer, n-type doping GaN layer, low temperature stress release layer, shallow well
Layer, multiple quantum well layer, electronic barrier layer, p-type GaN layer and p-type contact layer, the low temperature stress release layer are the first InGaN
The periodic structure of sublayer and the first GaN sublayer alternating growth, the first InGaN sublayer with a thickness of 1~2nm, described
One GaN sublayer with a thickness of 5~10nm, the quantity of the first InGaN sublayer or the first GaN sublayer is 10~30.
Optionally, the first InGaN sublayer is InaGa1-aN layers, 0 < a < 0.5.
Optionally, the low temperature stress release layer with a thickness of 100~120nm.
Optionally, the shallow well layer is the periodic structure of the 2nd InGaN sublayer and the 2nd GaN sublayer alternating growth, institute
State the 2nd InGaN sublayer with a thickness of 1nm, the 2nd GaN sublayer with a thickness of 10nm, the 2nd InGaN sublayer or institute
The quantity for stating the 2nd GaN sublayer is 5~10.
Optionally, the multiple quantum well layer includes the first composite layer, and first composite layer is the 3rd InGaN sublayer and the
The periodic structure of three GaN sublayer alternating growths, the 3rd InGaN sublayer with a thickness of 2~4nm, the 3rd GaN sublayer
With a thickness of 8~20nm.
Optionally, the multiple quantum well layer further includes the second composite layer, and it is compound that second composite layer is located at described first
Between layer and the electronic barrier layer, second composite layer is the week of the 4th InGaN sublayer and the 4th GaN sublayer alternating growth
Phase property structure, the 4th InGaN sublayer with a thickness of 2~4nm, the thickness of the 3rd GaN sublayer is greater than the 4th GaN
The thickness of sublayer, the ratio of the thickness of the thickness and the 4th GaN sublayer of the 3rd GaN sublayer are 1.2~1.7:1, institute
The alternating growth amount of cycles for stating the 3rd InGaN sublayer and the 3rd GaN sublayer is n1, the 4th InGaN sublayer and institute
Stating the 4th GaN sublayer alternating growth amount of cycles is n2,5 < n1+n2< 15, n1≥n2。
Optionally, the 3rd InGaN sublayer is InxGa1-xN layers, the 4th InGaN sublayer is InyGa1-yN layers, x/y
=0.5~0.8,0 < y < 1.
Optionally, the 3rd GaN sublayer and the 4th GaN sublayer are Si doping GaN sublayer, the 3rd GaN
Si doping concentration in sublayer is less than the Si doping concentration in the 4th GaN sublayer, the Si doping in the 3rd GaN sublayer
The ratio of Si doping concentration in concentration and the 4th GaN sublayer is 1:1.05~1.3, the Si in the 4th GaN sublayer
Doping concentration is 1016~1017cm-3。
Optionally, the electronic barrier layer include first segment of the stacked above one another on the multiple quantum well layer, second segment and
Third section, the first segment, the second segment and the third section are AlGaN sublayer and the 5th InGaN sublayer alternating growth
Periodic structure, the thickness of the first segment, the second segment and the third section sequentially increases, and the AlGaN sublayer is
AlcGa1-cN sublayer, the 5th InGaN sublayer are IndGa1-dN sublayer, 0.1 < c < 0.5,0.1 < d < 0.6.
Second aspect provides a kind of preparation method of GaN base light emitting epitaxial wafer, which comprises
Substrate is provided；
It is sequentially deposited buffer layer, undoped GaN layer, n-type doping GaN layer, low temperature stress release layer, shallow over the substrate
Well layer, multiple quantum well layer, electronic barrier layer, p-type GaN layer and p-type contact layer, the low temperature stress release layer are first
The periodic structure of InGaN sublayer and the first GaN sublayer alternating growth, the first InGaN sublayer with a thickness of 1~2nm, institute
State the first GaN sublayer with a thickness of 5~10nm, the quantity of the first InGaN sublayer or the first GaN sublayer is 10~
30。
Technical solution provided in an embodiment of the present invention has the benefit that be grown by low temperature stress release layer
The stress of outer layer growth accumulation is discharged in journey, the growth temperature of low temperature stress release layer is lower, and the surface of the first GaN sublayer is former
Transport factor is lower, keeps its horizontal extension ability poor, easily causes threading dislocation and forms V-type hole, and works as low temperature stress release
When layer is the first InGaN sublayer and the periodic structure of the first GaN sublayer alternating growth, release outer layer growth accumulation will be promoted
A large amount of stress and V-type cheat formation in low temperature stress release layer, the opening in the V-type hole of formation is towards multiple quantum well layer
And it can be become larger in subsequent outer layer growth split shed size；And when the first InGaN sublayer is with a thickness of 1~2nm, first
GaN sublayer with a thickness of 5~10nm when, when the quantity of the first InGaN sublayer or the first GaN sublayer is 10~30,
Low temperature stress release layer has certain thickness, can guarantee V-type openings of sizes of the hole in multiple quantum well layer in a certain range,
And when openings of sizes of the V-type hole in multiple quantum well layer is in a certain range, the threading dislocation center positioned at V-type hole center is to V
Quantum Well barrier height on the inclined surface in diffusion length and the V-type hole of type pit edge is in a state more balanced, makes
Must realize can effectively stop carrier to enter V-type again while stress release cheats to form non-radiative recombination center, outer using this
The internal quantum efficiency for prolonging LED made from piece is preferable, thus improves the luminous efficiency of LED.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is the schematic diagram in V-type hole provided in an embodiment of the present invention；
Fig. 2 is a kind of structural schematic diagram of GaN base light emitting epitaxial wafer provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of multiple quantum well layer provided in an embodiment of the present invention；
Fig. 4 is the fractional transmission electron-microscope scanning figure of GaN base light emitting epitaxial wafer provided in an embodiment of the present invention；
Fig. 5 is the structural schematic diagram of electronic barrier layer provided in an embodiment of the present invention；
Fig. 6 and Fig. 7 is a kind of process of the preparation method of GaN base light emitting epitaxial wafer provided in an embodiment of the present invention
Figure.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
Technical solution provided in an embodiment of the present invention for ease of understanding introduces V-type hole first.V-type is cheated outside GaN base
Prolong in the growth course of layer, is formed when growth temperature is lower.In low temperature, such as 750~850 DEG C, GaN horizontal extension ability becomes
It is weak, threading dislocation can be caused and form V-type hole.Generally, the growth temperature of low temperature stress release layer is much low at 800 DEG C or so
In 1000 DEG C of epitaxial layer bottom (including buffer layer, undoped GaN layer, n-type doping GaN layer) or more of growth temperature.Therefore, low
The introducing of warm stress release layer will form V-type hole.The direction of growth of the opening direction in V-type hole towards epitaxial layer.With the life of mqw layer
Long, V-type hole will pass through entire multiple quantum well layer, and the openings of sizes in V-type hole have to the internal quantum efficiency of mqw layer it is extremely important
Influence.Quantum Well QW referring to Fig. 1, when the opening of V-type hole P is relatively small, on its inclined surface (in multiple quantum well layer 7)
With higher potential barrier Δ E, it can effectively be passivated the non-radiative center D of threading dislocation；But when the opening of V-type hole P is smaller, position
Diffusion length Δ L in threading dislocation center D to the V-type hole edge P at the V-type hole center P can be relatively short, so that carrier C is more
It is easy captured into threading dislocation center D；On the contrary, when the opening of V-type hole P is relatively large, threading dislocation center D to V
The diffusion length Δ L that type cheats the edge P is relatively long, and carrier C can be inhibited to enter non-radiative recombination center, but its inclined surface
On Quantum Well QW barrier height Δ E reduce, cannot effectively stop carrier C enter V-type hole P.Therefore, pass through optimization V-type hole
Openings of sizes, keep the Quantum Well QW potential barrier on threading dislocation center D to the diffusion length Δ L and inclined surface at the V-type hole edge P high
Degree Δ E reaches equilibrium state, is extremely important to improve the luminous efficiency of light emitting diode.
Fig. 2 shows a kind of GaN base light emitting epitaxial wafers provided in an embodiment of the present invention.Referring to fig. 2, this shine two
Pole pipe epitaxial wafer includes: substrate 1 and the buffer layer being sequentially deposited on substrate 12, undoped GaN layer 3, n-type doping GaN layer
4, low temperature stress release layer 5, shallow well layer (also known as prime multiple quantum wells (Pre-MQW) layer) 6, multiple quantum well layer 7, electronic barrier layer
8, p-type GaN layer 9 and p-type contact layer 10.Wherein, low temperature stress release layer 5 is the first InGaN sublayer 51 and the first GaN sublayer 52
The periodic structure of alternating growth.First InGaN sublayer 51 with a thickness of 1~2nm, the first GaN sublayer 52 with a thickness of 5~
The quantity of 10nm, the first InGaN sublayer 51 or the first GaN sublayer 52 is 10~30.
Based on foregoing teachings it is found that the excessive or too small luminous efficiency for being all unfavorable for LED that is open in V-type hole.The present invention is real
Example is applied by controlling the thickness of low temperature stress release layer and adjust the opening that V-type is cheated in Quantum Well in multiple quantum well layer and is big
It is small, so as to improve the luminous efficiency of LED.The embodiment of the present invention discharges epitaxial layer by low temperature stress release layer during the growth process
The stress of accumulation is grown, the growth temperature of low temperature stress release layer is lower, and the surface atom mobility of the first GaN sublayer is lower,
Keep its horizontal extension ability poor, easily causes threading dislocation and form V-type hole, and when low temperature stress release layer is the first InGaN
When the periodic structure of sublayer and the first GaN sublayer alternating growth, by promote release outer layer growth accumulation a large amount of stress, with
And V-type cheats the formation in low temperature stress release layer, the opening in the V-type hole of formation is towards multiple quantum well layer and in subsequent extension
Layer growth split shed size can become larger；And when the first InGaN sublayer is with a thickness of 1~2nm, the thickness of the first GaN sublayer
When for 5~10nm, when the quantity of the first InGaN sublayer or the first GaN sublayer is 10~30, low temperature stress release layer has certain
Thickness, can guarantee openings of sizes of the V-type hole in multiple quantum well layer in a certain range, and when V-type is cheated in multiple quantum well layer
In openings of sizes in a certain range, positioned at V-type hole center threading dislocation center to V-type pit edge diffusion length and V
Quantum Well barrier height on the inclined surface in type hole is in a state more balanced, so that while realizing stress release again
It can effectively stop carrier to enter V-type to cheat to form non-radiative recombination center, be imitated using the interior quantum of LED made from the epitaxial wafer
Rate is preferable, thus improves the luminous efficiency of LED.
It should be noted that the growth that the embodiment of the present invention does not limit the first InGaN sublayer 51 and the first GaN sublayer 52 is suitable
Sequence can first grow the first GaN sublayer 52 of 51 regrowth of the first InGaN sublayer in a periodic structure, can also first growth regulation
The first InGaN sublayer 51 of one GaN sublayer, 52 regrowth.
Illustratively, substrate 1 is Sapphire Substrate.Buffer layer 2 can be AlN layers, the thickness of buffer layer 2 can be 15~
50nm；The thickness of undoped GaN layer 3 can be 1~4 μm；The thickness of n-type doping GaN layer 4 can be 1~5 μm.
Illustratively, the first InGaN sublayer 51 with a thickness of 2nm, the first GaN sublayer 52 with a thickness of 5nm.
Illustratively, the first InGaN sublayer 51 is InaGa1-aN layers, 0 < a < 0.5.In this way, the first InGaN sublayer and first
In constituent content can preferably match substrate in a certain range in the periodic structure of GaN sublayer alternating growth, such as blue precious
Stone lining bottom, the lattice constant with GaN base epitaxial layer, the stress that preferably improvement epitaxial wafer bottom accumulates during the growth process are released
It puts.
Illustratively, low temperature stress release layer 5 with a thickness of 100~120nm.When low temperature stress release layer 5 with a thickness of
When 100~120nm, the luminous efficiency using LED made from the epitaxial wafer is preferable.
Illustratively, shallow well layer 6 is the periodic structure of the 2nd InGaN sublayer 61 and 62 alternating growth of the 2nd GaN sublayer.
2nd InGaN sublayer 61 with a thickness of 1nm, the 2nd GaN sublayer 62 with a thickness of 10nm.2nd InGaN sublayer 61 or the 2nd GaN
The quantity of sublayer 62 is 5~10.
Shallow well layer 6 is used to prepare for the growth of multiple quantum well layer 7, and is conducive to V-type hole and extends in multiple quantum well layer 7.
Illustratively, the 2nd InGaN sublayer 61 is InbGa1-bN layers, 0 <b < 0.5.
Illustratively, referring to Fig. 3, multiple quantum well layer 7 includes the first composite layer 71.First composite layer 71 is the 3rd InGaN
The periodic structure of sublayer 71a and the 3rd GaN sublayer 71b alternating growth.3rd InGaN sublayer 71a with a thickness of 2~4nm,
Three GaN sublayer 71b with a thickness of 8~20nm.
Illustratively, referring to Fig. 3, multiple quantum well layer 7 further includes the second composite layer 72, and it is multiple that the second composite layer 72 is located at first
It closes between layer 71 and electronic barrier layer 8.Second composite layer 72 replaces life with the 4th GaN sublayer 72b for the 4th InGaN sublayer 72a
Long periodic structure.4th InGaN sublayer 72a with a thickness of 2~4nm.The thickness of 3rd GaN sublayer 71b is greater than the 4th GaN
The thickness of sublayer 72b, the ratio of the thickness of the thickness and the 4th GaN sublayer 72b of the 3rd GaN sublayer 71b are 1.2~1.7:1.The
The alternating growth amount of cycles of three InGaN sublayer 71a and the 3rd GaN sublayer 71b are n1, the 4th InGaN sublayer 72a and the 4th
GaN sublayer 72b alternating growth amount of cycles is n2,5 < n1+n2< 15, n1≥n2。
Wherein, InGaN material is built as Quantum Well, GaN material as quantum.It should be noted that the embodiment of the present invention
The succession of Quantum Well and quantum base is not limited, in a periodic structure, can first grow Quantum Well regrowth quantum base,
It can first grown quantum base regrowth Quantum Well.It is compound to be greater than second by the thickness of the 3rd GaN sublayer in the first composite layer
The thickness of the 4th GaN sublayer in layer, i.e. barrier layer thickness in leading portion multiple quantum well layer is partially thick, the base in back segment multiple quantum well layer
Thickness degree is partially thin, and it is excessive to be able to suppress opening of the V-type hole in multiple quantum well layer, meanwhile, the barrier layer in back segment multiple quantum well layer
The partially thick migration rate that can also delay electronics, keeps distribution of the electrons and holes in Quantum Well more uniform, to improve LED's
Luminous efficiency.
Illustratively, the 3rd InGaN sublayer 71a is InxGa1-xN layers, the 4th InGaN sublayer 72a is InyGa1-yN layers, x/y
=0.5~0.8,0 < y < 1.
It is less than back segment multiple quantum well layer In constituent content, leading portion volume by the In constituent content in leading portion multiple quantum well layer
In component can be open to avoid V-Pits in the quantum trap growth initial stage excessive less in sub- well layer Quantum Well, avoid with extension
The opening in the growth V-type hole of layer becomes larger, and V-type, which cheats the conference that was open, drops the Quantum Well barrier height on its inclined surface
It is low, cause carrier to be easier to be pierced dislocation and capture to form non-radiative recombination center, declines the internal quantum efficiency of LED.
It referring to Fig. 1, is matched by aforementioned low temperature stress release layer 5, shallow well layer 6 and multiple quantum well layer 7, V-type cheats P
It is formed in low temperature stress release layer 5, and is through to multiple quantum well layer 7 always.Fig. 4 is GaN base provided in an embodiment of the present invention hair
The fractional transmission electron-microscope scanning figure of optical diode epitaxial wafer, from fig. 4, it can be seen that passing through aforementioned low temperature stress release layer 5, shallow well
Layer 6 and multiple quantum well layer 7 match, and the openings of sizes that V-type can be cheated to P controls between 200~300nm, and LED's is interior
Quantum efficiency is best.
Illustratively, the 3rd GaN sublayer 71b and the 4th GaN sublayer 72b is Si doping GaN sublayer.3rd GaN sublayer
Si doping concentration in 71b is less than the Si doping concentration in the 4th GaN sublayer 72b.Si doping in 3rd GaN sublayer 71b is dense
Degree and the ratio of the Si doping concentration in the 4th GaN sublayer 72b are 1:1.05~1.3.Si doping in 4th GaN sublayer 72b
Concentration is 1016~1017cm-3。
Concentration is mixed less than the Si in back segment multiple quantum well layer GaN barrier layer by the Si in leading portion multiple quantum well layer GaN barrier layer
Concentration is mixed, due to the In in back segment multiple quantum well layeryGa1-yThe In component of N Quantum Well is more, so that in back segment multiple quantum well layer
Lattice mismatch between trap base is larger, and there are biggish stress for Quantum Well, will lead to In in back segment multiple quantum well layeryGa1-yN/
Microcell phenomenon of phase separation occurs for GaN interface undulation, and the Si of the GaN barrier layer in back segment multiple quantum well layer mixes increase and can inhibit
The fluctuation of In component in Quantum Well can change the surface energy that trap in growth course builds interface, so as to improve Quantum Well interface quality.
Illustratively, referring to Fig. 5, electronic barrier layer 8 includes first segment 81 of the stacked above one another on multiple quantum well layer 7, the
Two section 82 and third section 83.First segment 81, second segment 82 and third section 83 are AlGaN sublayer 8a and the 5th InGaN sublayer 8b
The periodic structure of alternating growth.The thickness of first segment 81, second segment 82 and third section 83 sequentially increases, and AlGaN sublayer 8a is
AlcGa1-cN sublayer.5th InGaN sublayer 8b is IndGa1-dN sublayer, 0.1 < c < 0.5,0.1 < d < 0.6.
By setting the incremental three-stage structure of thickness for electronic barrier layer, it can gradually reinforce the migration of GaN surface atom
Rate, the merging in enhancing V-type hole, reduces the density in V-type hole, is conducive to the merging that subsequent p-type GaN layer cheats V-type and fills and leads up, and obtains brilliant
The preferable p-type GaN layer of weight.
It should be noted that the embodiment of the present invention does not limit AlGaN sublayer 8a and the growth of the 5th InGaN sublayer 8b is suitable
Sequence can first grow the 5th InGaN sublayer 8b of AlGaN sublayer 8a regrowth in a periodic structure, can also first growth regulation five
InGaN sublayer 8b regrowth AlGaN sublayer 8a.
Illustratively, multiple quantum well layer 7 is low temperature multiple quantum well layer；In electronic barrier layer 8, first segment 81 is low-temperature zone,
Second segment 82 is middle-temperature section, and third section 83 is high temperature section.
By the first segment of the relatively relatively low electronic barrier layer of growth temperature first after multiple quantum well layer is grown, favorably
In the protection to quantum well structure, if electronic barrier layer initial stage of growth temperature drift may be to low temperature quantum well structure
It damages, and temperature increment growth can then improve this phenomenon.Also, increase in three sections of thickness of electronic barrier layer most thick
Shi Wendu is also highest, can further strengthen GaN surface atom mobility, and the merging in enhancing V-type hole reduces the close of V-type hole
Degree, is conducive to the merging that subsequent p-type GaN layer cheats V-type and fills and leads up, and obtains the preferable p-type GaN layer of crystal quality.
Illustratively, the overall thickness of electronic barrier layer 8 is 10~100nm.First segment 81, second segment 82 and third section 83
Thickness sequentially increases with the 10%~60% of the overall thickness of electronic barrier layer 8 for amplitude.
Illustratively, first segment 81 with a thickness of 3~15nm, second segment 82 with a thickness of 4.5~30nm, third section 83
AlGaN sublayer 8a with a thickness of 6~40nm, and in every section is identical as the thickness of the 5th InGaN sublayer 8b.
Illustratively, the thickness of p-type GaN layer 9 can be 100nm~200nm；P-type contact layer 10 can be GaN or
InGaN layer, thickness can be 5~300nm.
Fig. 6 shows a kind of preparation method of GaN base light emitting epitaxial wafer provided in an embodiment of the present invention.Referring to figure
6, this method process includes the following steps.
Step 101 provides substrate.
Illustratively, substrate can be Sapphire Substrate.
Step 102 is sequentially deposited buffer layer, undoped GaN layer, n-type doping GaN layer, low temperature stress release on substrate
Layer, shallow well layer, multiple quantum well layer, electronic barrier layer, p-type GaN layer and p-type contact layer.
Wherein, low temperature stress release layer is the periodic structure of the first InGaN sublayer and the first GaN sublayer alternating growth,
First InGaN sublayer with a thickness of 1~2nm, the first GaN sublayer with a thickness of 5~10nm, the first InGaN sublayer or the first GaN
The quantity of sublayer is 10~30.
The embodiment of the present invention discharges the stress of outer layer growth accumulation by low temperature stress release layer during the growth process, low
The growth temperature of warm stress release layer is lower, and the surface atom mobility of the first GaN sublayer is lower, make its horizontal extension ability compared with
Difference easily causes threading dislocation and forms V-type hole, and when low temperature stress release layer is that the first InGaN sublayer and the first GaN sublayer are handed over
For growth periodic structure when, a large amount of stress of release outer layer growth accumulation and V-type will be promoted to cheat and release in low temperature stress
The formation in layer is put, the opening in the V-type hole of formation is towards multiple quantum well layer and in subsequent outer layer growth split shed size meeting
It becomes larger；And when the first InGaN sublayer is with a thickness of 1~2nm, the first GaN sublayer with a thickness of 5~10nm when, first
When the quantity of InGaN sublayer or the first GaN sublayer is 10~30, low temperature stress release layer has certain thickness, can guarantee V
Openings of sizes of the type hole in multiple quantum well layer works as openings of sizes of the V-type hole in multiple quantum well layer one in a certain range
When determining range, on the threading dislocation center to the inclined surface in diffusion length and the V-type hole of V-type pit edge at V-type hole center
Quantum Well barrier height is in a state more balanced, can effectively stop current-carrying again while so that realizing stress release
Son enters V-type and cheats to form non-radiative recombination center, and the internal quantum efficiency using LED made from the epitaxial wafer is preferable, thus improves
The luminous efficiency of LED.
Fig. 7 shows a kind of preparation method of GaN base light emitting epitaxial wafer provided in an embodiment of the present invention.Referring to figure
7, this method process includes the following steps.
Step 201 provides substrate.
Illustratively, substrate can be (0001) crystal orientation Sapphire Substrate (Al2O3)。
Step 202, on substrate buffer layer.
Wherein, buffer layer can be AlN buffer layer.It can use PVD (Physical Vapor Deposition, physics
Vapor deposition) method, for example (,) magnetically controlled sputter method, growing AIN buffer layer.The growth temperature of AlN buffer layer is 400~700 DEG C,
Sputtering power is 3000~5000W, and pressure is 1~10torr, with a thickness of 15~50nm.
Step 203 makes annealing treatment buffer layer.
Step 203 includes: that (Metal-organic Chemical Vapor Deposition, metal are organic in MOCVD
Compound chemical gaseous phase deposition) buffer layer is made annealing treatment in equipment.Specifically, the substrate of AlN buffer layer will be deposited with
It is placed on the substrate pallet in the reaction chamber of MOCVD device, and substrate pallet is heated and driven substrate pallet rotate.
Illustratively, substrate pallet can be graphite pallet.When substrate pallet rotates, substrate will be rotated with substrate pallet.
Wherein, annealing temperature is at 1000 DEG C~1200 DEG C, and pressure range is 200Torr~500Torr, and the time was at 5 minutes
~10 minutes.
Specifically, other epitaxial layers are then grown by MOCVD method.In MOCVD method, high pure nitrogen can be used
Or hydrogen is as carrier gas, and ammonia is as nitrogen source, trimethyl gallium or trimethyl second as gallium source, and trimethyl indium is as indium source, and three
For aluminium methyl as silicon source, N type dopant selects silane, and P-type dopant selects two luxuriant magnesium.
It should be noted that the temperature and pressure controlled in following growth courses actually refers to the reaction of MOCVD device
Intracavitary temperature and pressure.
Step 204 deposits undoped GaN layer on the buffer layer.
Illustratively, the growth temperature of undoped GaN layer be 1000 DEG C~1100 DEG C, growth thickness 1 to 4 micron it
Between, growth pressure is in 100Torr between 300Torr.
Step 205, the deposited n-type doped gan layer in undoped GaN layer.
Illustratively, the thickness of N-type GaN layer is between 1~5 micron, and growth temperature is at 1000 DEG C~1200 DEG C, growth pressure
Power is in 100Torr between 300Torr, and Si doping concentration is 1 × 1018cm-3~1 × 1019cm-3Between.
Step 206, the deposit low temperature stress release layer in n-type doping GaN layer.
Wherein, low temperature stress release layer is the periodic structure of the first InGaN sublayer and the first GaN sublayer alternating growth.
First InGaN sublayer with a thickness of 1~2nm, the first GaN sublayer with a thickness of 5~10nm, the first InGaN sublayer or the first GaN
The quantity of sublayer is 10~30.
Illustratively, the growth temperature of low temperature stress release layer flood is at 750 DEG C~900 DEG C, pressure 100Torr~
300Torr。
Illustratively, the first InGaN sublayer 51 is InaGa1-aN layers, 0 < a < 0.5.In this way, the first InGaN sublayer and first
In constituent content can preferably match substrate in a certain range in the periodic structure of GaN sublayer alternating growth, such as blue precious
Stone lining bottom, the lattice constant with GaN base epitaxial layer, the stress that preferably improvement epitaxial wafer bottom accumulates during the growth process are released
It puts.
Illustratively, low temperature stress release layer 5 with a thickness of 100~120nm.When low temperature stress release layer 5 with a thickness of
When 100~120nm, the luminous efficiency using LED made from the epitaxial wafer is preferable.
Step 207 deposits shallow well layer on low temperature stress release layer.
Illustratively, shallow well layer is the periodic structure of the 2nd InGaN sublayer and the 2nd GaN sublayer alternating growth.Second
InGaN sublayer with a thickness of 1nm, the 2nd GaN sublayer with a thickness of 10nm.The quantity of 2nd InGaN sublayer or the 2nd GaN sublayer
Be 5~10, i.e., shallow well layer include 5~10 periods the 2nd InGaN sublayer and the 2nd GaN sublayer.
Illustratively, the 2nd InGaN sublayer is InbGa1-bN layers, 0 <b < 0.5.
Illustratively, the range of the growth temperature of the 2nd InGaN sublayer is between 780 DEG C~850 DEG C in shallow well layer, pressure model
It is trapped among 100Torr~300Torr；The growth temperature of 2nd GaN sublayer at 810 DEG C~940 DEG C, growth pressure 100Torr~
300Torr。
Step 208 deposits multiple quantum well layer on shallow well layer.
Illustratively, multiple quantum well layer includes the first composite layer.First composite layer is the 3rd InGaN sublayer and the 3rd GaN
The periodic structure of sublayer alternating growth.3rd InGaN sublayer with a thickness of 2~4nm, the 3rd GaN sublayer with a thickness of 8~
20nm。
Illustratively, multiple quantum well layer further includes the second composite layer, and the second composite layer is located at the first composite layer and electronics hinders
Between barrier.Second composite layer is the periodic structure of the 4th InGaN sublayer and the 4th GaN sublayer alternating growth.4th InGaN
Sublayer with a thickness of 2~4nm.The thickness of 3rd GaN sublayer be greater than the 4th GaN sublayer thickness, the thickness of the 3rd GaN sublayer with
The ratio of the thickness of 4th GaN sublayer is 1.2~1.7:1.The alternating growth period of 3rd InGaN sublayer and the 3rd GaN sublayer
Quantity is n1, and the 4th InGaN sublayer and the 4th GaN sublayer alternating growth amount of cycles are n2,5 < n1+n2< 15, n1≥n2。
Wherein, InGaN material is built as Quantum Well, GaN material as quantum.Pass through the 3rd GaN in the first composite layer
The thickness of sublayer is greater than the thickness of the 4th GaN sublayer in the second composite layer, i.e. barrier layer thickness in leading portion multiple quantum well layer is inclined
Thickness, the barrier layer thickness in back segment multiple quantum well layer is partially thin, and it is excessive to be able to suppress opening of the V-type hole in multiple quantum well layer, meanwhile,
The partially thick migration rate that can also delay electronics of barrier layer in back segment multiple quantum well layer, makes distribution of the electrons and holes in Quantum Well
It is more uniform, to improve the luminous efficiency of LED.
Illustratively, the growth temperature of the 3rd InGaN sublayer and the 4th InGaN sublayer is 750 DEG C~820 DEG C, growth pressure
Power is 100Torr~300Torr.The growth temperature of 3rd InGaN sublayer and the 3rd GaN sublayer is 830 DEG C -930 DEG C, growth pressure
Power is 100Torr~300Torr.
Illustratively, the 3rd InGaN sublayer is InxGa1-xN layers, the 4th InGaN sublayer is InyGa1-yN layers, x/y=0.5
~0.8,0 < y < 1.
It is less than back segment multiple quantum well layer In constituent content, leading portion volume by the In constituent content in leading portion multiple quantum well layer
In component can be open to avoid V-Pits in the quantum trap growth initial stage excessive less in sub- well layer Quantum Well, avoid with extension
The opening in the growth V-type hole of layer becomes larger, and V-type, which cheats the conference that was open, drops the Quantum Well barrier height on its inclined surface
It is low, cause carrier to be easier to be pierced dislocation and capture to form non-radiative recombination center, declines the internal quantum efficiency of LED.
It is matched by aforementioned low temperature stress release layer, shallow well layer and multiple quantum well layer, the opening that V-type can be cheated
Size controls between 200~300nm, and the internal quantum efficiency of LED is best.
Illustratively, the 3rd GaN sublayer and the 4th GaN sublayer are Si doping GaN sublayer.Si in 3rd GaN sublayer
Doping concentration is less than the Si doping concentration in the 4th GaN sublayer.Si doping concentration and the 4th GaN sublayer in 3rd GaN sublayer
In Si doping concentration ratio be 1:1.05~1.3.Si doping concentration in 4th GaN sublayer is 1016~1017cm-3。
Concentration is mixed less than the Si in back segment multiple quantum well layer GaN barrier layer by the Si in leading portion multiple quantum well layer GaN barrier layer
Concentration is mixed, due to the In in back segment multiple quantum well layeryGa1-yThe In component of N Quantum Well is more, so that in back segment multiple quantum well layer
Lattice mismatch between trap base is larger, and there are biggish stress for Quantum Well, will lead to In in back segment multiple quantum well layeryGa1-yN/
Microcell phenomenon of phase separation occurs for GaN interface undulation, and the Si of the GaN barrier layer in back segment multiple quantum well layer mixes increase and can inhibit
The fluctuation of In component in Quantum Well can change the surface energy that trap in growth course builds interface, so as to improve Quantum Well interface quality.
Step 209 grows electronic barrier layer on multiple quantum well layer.
Illustratively, electronic barrier layer includes first segment, second segment 82 and third of the stacked above one another on multiple quantum well layer
Section.First segment, second segment and third section are the periodic structure of AlGaN sublayer Yu the 5th InGaN sublayer alternating growth.First
The thickness of section, second segment and third section sequentially increases, and AlGaN sublayer is AlcGa1-cN sublayer.5th InGaN sublayer is IndGa1- dN sublayer, 0.1 < c < 0.5,0.1 < d < 0.6.
By setting the incremental three-stage structure of thickness for electronic barrier layer, it can gradually reinforce the migration of GaN surface atom
Rate, the merging in enhancing V-type hole, reduces the density in V-type hole, is conducive to the merging that subsequent p-type GaN layer cheats V-type and fills and leads up, and obtains brilliant
The preferable p-type GaN layer of weight.
Illustratively, multiple quantum well layer is low temperature multiple quantum well layer；In electronic barrier layer, first segment is low-temperature zone, second
Section is middle-temperature section, and third section is high temperature section.Specifically, in electronic barrier layer first segment, second segment and third section growth temperature
Degree is 850 DEG C~1050 DEG C, and the growth temperature of first segment, second segment and third section is sequentially increased with 10~50 DEG C for amplitude.
By the first segment of the relatively relatively low electronic barrier layer of growth temperature first after multiple quantum well layer is grown, favorably
In the protection to quantum well structure, if electronic barrier layer initial stage of growth temperature drift may be to low temperature quantum well structure
It damages, and temperature increment growth can then improve this phenomenon.Also, increase in three sections of thickness of electronic barrier layer most thick
Shi Wendu is also highest, can further strengthen GaN surface atom mobility, and the merging in enhancing V-type hole reduces the close of V-type hole
Degree, is conducive to the merging that subsequent p-type GaN layer cheats V-type and fills and leads up, and obtains the preferable p-type GaN layer of crystal quality.
Illustratively, the growth pressure of electronic barrier layer is 100Torr~500Torr.
Illustratively, the overall thickness of electronic barrier layer is 10~100nm.The thickness of first segment, second segment and third section with
10%~60% sequentially increases for amplitude.For example, the thickness of second segment increases the 10% of first segment thickness than the thickness of first segment
~60%.
Step 210 deposits p-type GaN layer on electronic barrier layer.
Illustratively, the growth temperature of p-type GaN layer be 750 DEG C~1080 DEG C, growth pressure be 200torr~
600torr, the thickness of p-type GaN layer can be 100nm~200nm.
Step 211 deposits p-type contact layer in p-type GaN layer.
Illustratively, p-type contact layer is GaN or InGaN layer, with a thickness of 5nm between 300nm, growth temperature area
Between be 850 DEG C~1050 DEG C, growth pressure section be 100Torr~600Torr.
Illustratively, after the growth of p-type contact layer, the reaction cavity temperature of MOCVD device is reduced, in nitrogen atmosphere
Middle annealing, annealing temperature section are 650 DEG C~850 DEG C, make annealing treatment 5 to 15 minutes, are down to room temperature, it is raw to complete extension
It is long.
The embodiment of the present invention discharges the stress of outer layer growth accumulation by low temperature stress release layer during the growth process, low
The growth temperature of warm stress release layer is lower, and the surface atom mobility of the first GaN sublayer is lower, make its horizontal extension ability compared with
Difference easily causes threading dislocation and forms V-type hole, and when low temperature stress release layer is that the first InGaN sublayer and the first GaN sublayer are handed over
For growth periodic structure when, a large amount of stress of release outer layer growth accumulation and V-type will be promoted to cheat and release in low temperature stress
The formation in layer is put, the opening in the V-type hole of formation is towards multiple quantum well layer and in subsequent outer layer growth split shed size meeting
It becomes larger；And when the first InGaN sublayer is with a thickness of 1~2nm, the first GaN sublayer with a thickness of 5~10nm when, first
When the quantity of InGaN sublayer or the first GaN sublayer is 10~30, low temperature stress release layer has certain thickness, can guarantee V
Openings of sizes of the type hole in multiple quantum well layer works as openings of sizes of the V-type hole in multiple quantum well layer one in a certain range
When determining range, on the threading dislocation center to the inclined surface in diffusion length and the V-type hole of V-type pit edge at V-type hole center
Quantum Well barrier height is in a state more balanced, can effectively stop current-carrying again while so that realizing stress release
Son enters V-type and cheats to form non-radiative recombination center, and the internal quantum efficiency using LED made from the epitaxial wafer is preferable, thus improves
The luminous efficiency of LED.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of GaN base light emitting epitaxial wafer, which is characterized in that the LED epitaxial slice includes: substrate, in institute
State the buffer layer being sequentially deposited on substrate, undoped GaN layer, n-type doping GaN layer, low temperature stress release layer, shallow well layer, volume
Sub- well layer, electronic barrier layer, p-type GaN layer and p-type contact layer, the low temperature stress release layer be the first InGaN sublayer with
The periodic structure of first GaN sublayer alternating growth, the first InGaN sublayer with a thickness of 1~2nm, the first GaN
Layer with a thickness of 5~10nm, the quantity of the first InGaN sublayer or the first GaN sublayer is 10~30.
2. epitaxial wafer according to claim 1, which is characterized in that the first InGaN sublayer is InaGa1-aN layers, 0 < a <
0.5。
3. epitaxial wafer according to claim 1, which is characterized in that the low temperature stress release layer with a thickness of 100~
120nm。
4. epitaxial wafer according to claim 1, which is characterized in that the shallow well layer is the 2nd InGaN sublayer and the 2nd GaN
The periodic structure of sublayer alternating growth, the 2nd InGaN sublayer with a thickness of 1nm, the 2nd GaN sublayer with a thickness of
The quantity of 10nm, the 2nd InGaN sublayer or the 2nd GaN sublayer is 5~10.
5. epitaxial wafer according to claim 1, which is characterized in that the multiple quantum well layer includes the first composite layer, described
First composite layer is the periodic structure of the 3rd InGaN sublayer and the 3rd GaN sublayer alternating growth, the 3rd InGaN sublayer
With a thickness of 2~4nm, the 3rd GaN sublayer with a thickness of 8~20nm.
6. epitaxial wafer according to claim 5, which is characterized in that the multiple quantum well layer further includes the second composite layer, institute
The second composite layer is stated between first composite layer and the electronic barrier layer, second composite layer is the 4th InGaN
The periodic structure of sublayer and the 4th GaN sublayer alternating growth, the 4th InGaN sublayer with a thickness of 2~4nm, described
The thickness of three GaN sublayers is greater than the thickness of the 4th GaN sublayer, the thickness and the 4th GaN of the 3rd GaN sublayer
The ratio of the thickness of layer is 1.2~1.7:1, the alternating growth periodicity of the 3rd InGaN sublayer and the 3rd GaN sublayer
Amount is n1, and the 4th InGaN sublayer and the 4th GaN sublayer alternating growth amount of cycles are n2,5 < n1+n2< 15, n1≥
n2。
7. epitaxial wafer according to claim 6, which is characterized in that the 3rd InGaN sublayer is InxGa1-xIt is N layers, described
4th InGaN sublayer is InyGa1-yN layers, x/y=0.5~0.8,0 < y < 1.
8. epitaxial wafer according to claim 6, which is characterized in that the 3rd GaN sublayer and the 4th GaN sublayer are equal
GaN sublayer is adulterated for Si, it is dense that the Si doping concentration in the 3rd GaN sublayer is less than the Si doping in the 4th GaN sublayer
It spends, the ratio of the Si doping concentration in Si doping concentration and the 4th GaN sublayer in the 3rd GaN sublayer is 1:1.05
~1.3, the Si doping concentration in the 4th GaN sublayer is 1016~1017cm-3。
9. epitaxial wafer according to claim 1, which is characterized in that the electronic barrier layer includes stacked above one another described more
First segment, second segment and third section on quantum well layer, the first segment, the second segment and the third section are AlGaN
The periodic structure of sublayer and the 5th InGaN sublayer alternating growth, the thickness of the first segment, the second segment and the third section
Sequentially increase, the AlGaN sublayer is AlcGa1-cN sublayer, the 5th InGaN sublayer are IndGa1-dN sublayer, 0.1 < c <
0.5,0.1 < d < 0.6.
10. a kind of preparation method of GaN base light emitting epitaxial wafer, which is characterized in that the described method includes:
Substrate is provided；
It is sequentially deposited buffer layer, undoped GaN layer, n-type doping GaN layer, low temperature stress release layer, shallow well over the substrate
Layer, multiple quantum well layer, electronic barrier layer, p-type GaN layer and p-type contact layer, the low temperature stress release layer are the first InGaN
The periodic structure of sublayer and the first GaN sublayer alternating growth, the first InGaN sublayer with a thickness of 1~2nm, described
One GaN sublayer with a thickness of 5~10nm, the quantity of the first InGaN sublayer or the first GaN sublayer is 10~30.
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