CN109534283A - A kind of micro electro mechanical device preparation method and device - Google Patents
A kind of micro electro mechanical device preparation method and device Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 170
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- 229910052710 silicon Inorganic materials 0.000 claims description 38
- 239000010703 silicon Substances 0.000 claims description 38
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00134—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising flexible or deformable structures
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00198—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising elements which are movable in relation to each other, e.g. comprising slidable or rotatable elements
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
- B81C1/00238—Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
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Abstract
The present invention discloses a kind of micro electro mechanical device preparation method and device, comprising: prepares alignment mark at the first wafer substrate back side；It is alignment reference with the alignment mark, prepares conductive channel at first wafer substrate back side；First wafer substrate is overturn, is alignment reference with the alignment mark, using the technique of alignment of back-to-front, prepares electrode window through ray and deflectable element in first wafer substrate front；First wafer substrate is overturn, is alignment reference with the alignment mark, the cause electrode control circuit being electrically connected with the conductive channel is prepared at first wafer substrate back side.Scheme provided by the invention improves the processing for carrying out wafer two sides in the prior art, and there are biggish alignment errors, the technical issues of reducing yield rate, also bring hidden danger to the q&r of device.Alignment precision can be effectively improved, yield rate and device quality are improved.
Description
Technical field
The present invention relates to semiconductor process technique field more particularly to a kind of micro electro mechanical device preparation method and devices.
Background technique
With the complication of semiconductor devices, semiconductor technology is also increasingly sophisticated, for the size of control device, part work
Skill generally requires to be processed at the back side of wafer and front.For example, the sensor structure comprising moving element.
, often there is biggish alignment error, reduce yield rate in the processing that wafer two sides is carried out using existing technique,
Also hidden danger is brought to the q&r of device.
Summary of the invention
The present invention improves progress wafer two in the prior art by providing a kind of micro electro mechanical device preparation method and device
The processing in face, there are biggish alignment errors, reduce yield rate, and the technology of hidden danger is also brought to the q&r of device
Problem.
On the one hand, the present invention provides a kind of micro electro mechanical device preparation methods, comprising:
Alignment mark is prepared at the first wafer substrate back side；
It is alignment reference with the alignment mark, prepares conductive channel at first wafer substrate back side；
First wafer substrate is overturn, is alignment reference with the alignment mark, using the alignment skill of back-to-front
Art prepares electrode window through ray and deflectable element in first wafer substrate front；
First wafer substrate is overturn, is alignment reference with the alignment mark, at first wafer substrate back side
Prepare the cause electrode control circuit being electrically connected with the conductive channel.
Optionally, described after the first wafer substrate back side prepares alignment mark, further includes: described to fiducial mark retaining
On the basis of note, first wafer substrate back side is polished directly.
Optionally, described to prepare alignment mark at the first wafer substrate back side, comprising: to be prepared at the first wafer substrate back side
The alignment mark that depth is 600 nanometers~1200 nanometers；It is described that first wafer substrate back side is polished directly, packet
Include: first wafer substrate back side be polished directly, after grinding and polishing the depth of the alignment mark be 300 nanometers~
1100 nanometers.
Optionally, overturning first wafer substrate, is alignment reference with the alignment mark, using the back side to just
The technique of alignment in face prepares electrode window through ray and deflectable element in first wafer substrate front, comprising: overturning described first
Wafer substrate is alignment reference with the alignment mark, using the technique of alignment of back-to-front, in first wafer substrate
The electrode window through ray is prepared in positive top silicon layer and buries oxide layer, the electrode window through ray is aligned with the conductive channel；By
Two wafer substrates are placed in the first wafer substrate front, and are bonded first wafer substrate and the second wafer substrate；With institute
Alignment mark is stated as alignment reference, using the technique of alignment of back-to-front, the second wafer substrate described in photoetching can described in preparation
Deflecting element.
Optionally, described that second wafer substrate is placed in the first wafer substrate front, comprising: by the second wafer substrate
The back side carries out thinned, inversion second wafer substrate, with the first wafer substrate described in the second wafer substrate front face
Second wafer substrate is placed in the first wafer substrate front by front, wherein second wafer substrate front is set
It is equipped with top silicon layer and/or buries oxide layer.
Optionally, the opening size of the electrode window through ray is less than the cross sectional dimensions of the conductive channel.
Optionally, described prepare at first wafer substrate back side is sent a telegraph with what the through silicon via conductive channel was electrically connected
Before the control circuit of pole, further includes: third wafer is placed in the deflectable element, and be bonded the third wafer with it is described
Second wafer substrate.
Optionally, described to send a telegraph pole control what the preparation of first wafer substrate back side was electrically connected with the conductive channel
After circuit, further includes: release being bonded for the third wafer and second wafer substrate.
Optionally, described to be referred to the alignment mark for alignment, at first wafer substrate back side, preparation is conductive leads to
Road, comprising: referred to the alignment mark for alignment, optical graving is at first wafer substrate back side for ring-shaped groove；To institute
It states ring-shaped groove and carries out dielectric filling；Ion implanting or doping diffusion are carried out to the through silicon via that the ring-shaped groove surrounds,
Form through silicon via conductive channel.
On the other hand, a kind of micro electro mechanical device preparation facilities is provided, comprising:
Alignment modules, for preparing alignment mark at the first wafer substrate back side；
Channel prepares module, for being alignment reference with the alignment mark, prepares at first wafer substrate back side
Conductive channel；
Deflectable element prepares module, is alignment reference with the alignment mark for overturning first wafer substrate,
Using the technique of alignment of back-to-front, electrode window through ray and deflectable element are prepared in first wafer substrate front；
Circuit prepares module, is alignment reference with the alignment mark, described for overturning first wafer substrate
The first wafer substrate back side prepares the cause electrode control circuit being electrically connected with the conductive channel.
The one or more technical solutions provided in the embodiment of the present invention, have at least the following technical effects or advantages:
1, method and device provided by the embodiments of the present application, after the first wafer substrate back side prepares alignment mark, first with
Alignment mark is alignment reference, prepares conductive channel at first wafer substrate back side；First wafer substrate is overturn again,
It is alignment reference with the alignment mark, using the technique of alignment of back-to-front, is prepared in first wafer substrate front
Electrode window through ray and deflectable element；First wafer substrate is finally overturn again, is alignment reference with the alignment mark, in institute
It states the first wafer substrate back side and prepares the cause electrode control circuit being electrically connected with the conductive channel.So that preparing electrode window
When mouth, deflectable element and cause electrode control circuit, alignment mark is not blocked, can effectively improve alignment precision, improves
Yield rate and device quality.
2, method and device provided by the embodiments of the present application, on the basis of retaining the alignment mark, first to described
After the one wafer substrate back side is polished directly, then with the alignment mark to be directed at reference, using the alignment of back-to-front
Technology prepares electrode window through ray and deflectable element in first wafer substrate front, does not block alignment mark not only, also make
It obtains flatness of the whole wafer in the wafer carrying platform of exposure sources to improve, further effectively improves alignment precision.
The above description is only an overview of the technical scheme of the present invention, in order to better understand the technical means of the present invention,
And it can be implemented in accordance with the contents of the specification, and in order to allow above and other objects of the present invention, feature and advantage can
It is clearer and more comprehensible, the followings are specific embodiments of the present invention.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is this hair
Bright some embodiments for those of ordinary skill in the art without creative efforts, can be with root
Other attached drawings are obtained according to these attached drawings.
Fig. 1 is the flow chart of micro electro mechanical device preparation method in the embodiment of the present invention；
Fig. 2 is the artwork one of micro electro mechanical device preparation method in the embodiment of the present invention；
Fig. 3 is the artwork two of micro electro mechanical device preparation method in the embodiment of the present invention；
Fig. 4 is the artwork three of micro electro mechanical device preparation method in the embodiment of the present invention；
Fig. 5 is the artwork four of micro electro mechanical device preparation method in the embodiment of the present invention；
Fig. 6 is the artwork five of micro electro mechanical device preparation method in the embodiment of the present invention；
Fig. 7 is the device schematic diagram of micro electro mechanical device preparation method preparation in the embodiment of the present invention；
Fig. 8 is the schematic diagram of micro electro mechanical device preparation facilities in the embodiment of the present invention.
Specific embodiment
The embodiment of the present application is improved and is carried out in the prior art by providing a kind of micro electro mechanical device preparation method and device
The processing on wafer two sides, there are biggish alignment errors, reduce yield rate, also bring hidden danger to the q&r of device
The technical issues of.Alignment precision can be effectively improved, yield rate and device quality are improved.
Technical solution in the embodiment of the present application, general thought are as follows:
It is first alignment reference with alignment mark after the first wafer substrate back side prepares alignment mark, it is brilliant described first
Circle substrate back prepares through silicon via conductive channel；First wafer substrate is overturn again, is alignment reference with the alignment mark,
Using the technique of alignment of back-to-front, electrode window through ray and deflectable element are prepared in first wafer substrate front；Finally
Overturn first wafer substrate again, with the alignment mark be alignment reference, first wafer substrate back side preparation with
The cause electrode control circuit of the through silicon via conductive channel electrical connection.So that in preparation electrode window through ray, deflectable element and sending a telegraph
When the control circuit of pole, alignment mark is not blocked, can effectively improve alignment precision, improves yield rate and device quality.
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without creative efforts, shall fall within the protection scope of the present invention.
Embodiment one
In the present embodiment, a kind of micro electro mechanical device preparation method is provided, as shown in Figure 1, comprising:
Step S101 prepares alignment mark at the first wafer substrate back side；
Step S102 is alignment reference with the alignment mark, prepares conductive channel at first wafer substrate back side；
Step S103 overturns first wafer substrate, is alignment reference with the alignment mark, using back-to-front
Technique of alignment, prepare electrode window through ray and deflectable element in first wafer substrate front；
Step S104 overturns first wafer substrate, is alignment reference with the alignment mark, in first wafer
Substrate back prepares the cause electrode control circuit being electrically connected with the conductive channel.
It should be noted that method provided in this embodiment can be applied to any dual-surface stereo device with deflectable element
Part.Using method provided in this embodiment, when preparing through silicon via conductive channel and causing electrode control circuit, it is ensured that alignment
Label is not blocked, and in the technique of alignment using back-to-front, prepares electrode window through ray and when deflectable element, can also be with
Guarantee that alignment mark is not blocked, alignment precision can be significantly improved.
Preparation method provided by the embodiments of the present application is introduced below with reference to Fig. 1-7, wherein Fig. 2-7 mentions for the present embodiment
The flow chart of the micro electro mechanical device preparation method by the arrangement of technique sequencing supplied:
Firstly, executing step S101, alignment mark 4 is prepared at 1 back side of the first wafer substrate.
As shown in Fig. 2, the front of first wafer substrate 1 is provided with buries oxide layer 2 (BOX) and top silicon layer 3, first crystalline substance
The back side of circle substrate 1 is exposed.
In the embodiment of the present application, which can be SOI wafer, be also possible to glass, ceramics, SU-8
Etc..It can extend to any semiconductor base materials, extend also to any micro mechanical system or microelectronics to be processed
Rapidoprint required for system, this is not restricted.
In the embodiment of the present application, alignment mark can be completed by photoetching and plasma dry etch, can also be by light
It carves and color injection is completed.The shape of alignment mark is with no restriction.The depth of the alignment mark is 600 nanometers to 1200 nanometers.
Then, step S102 is executed, is alignment reference with the alignment mark 4, in 1 back side system of the first wafer substrate
Standby conductive channel.
Specifically, the method for conductive channel is prepared are as follows: first as shown in Fig. 2, being alignment reference with the alignment mark 4,
By coating photoresist 5, using deep reaction ion etching technique, etching stopping is just touching buries oxide layer 2, described
First wafer substrate, 1 back side optical graving is for ring-shaped groove 6；Then dielectric is carried out to the ring-shaped groove 6 as shown in Figure 3 to fill out
It fills, the part that ring-shaped groove insulation is surrounded is through silicon via 7；Ion note is carried out to the through silicon via 7 that the ring-shaped groove 6 surrounds again
Enter or adulterate diffusion, it is made to have electric conductivity, forms conductive channel.
In the embodiment of the present application, conductive channel is not limited to through silicon via 7, is also possible to metal throuth hole i.e. insulating materials and surround
Metallic conduction channel, i.e. the form and structure of the conductive channel be not discussed in detail herein there are many type.
Preferably, after being prepared for through silicon via conductive channel, on the basis of retaining alignment mark 4, to described
One wafer substrate, 1 back side is polished directly, i.e. progress fine mask processing, which must be by technology controlling and process, cannot
The alignment mark produced is damaged or polished.It needs to control in the alignment after fine gtinding processing, left
What is marked is deep-controlled between 300 nanometers to 1100 nanometers, specifically can be using grinding or CMP process technology come real
It is existing.
It is of course also possible to after preparing alignment mark 4, and preparation through silicon via conductive channel come it is brilliant to described first
Circle 1 back side of substrate is polished directly, and this is not restricted.But it is brilliant to described first again after being prepared for through silicon via conductive channel
Circle 1 back side of substrate is polished directly, and avoids influence of the preparation through silicon via conductive channel to 1 back side of the first wafer substrate, more
Can guarantee it is subsequent overturning wafer after the back side it is smooth, more conducively raising alignment precision.
Next, execute step S103, first wafer substrate 1 is overturn on wafer adapting table 12, with the alignment
Label 4 is alignment reference, using the technique of alignment of back-to-front, in the 1 front preparation electrode window through ray of the first wafer substrate
(including actuating side protective layer window 10 and retarding electrode window 11) and deflectable element 17.
Specifically, it is first carried out not on the exposed backing bottom surface of the first wafer substrate 1 and through silicon via electrical connection
Cause the production of electrode control circuit 8.But it is changed to place at the backing bottom of the first wafer substrate 1 after fine gtinding to make downward
Standby electrode window through ray and deflectable element 17, are avoided that and electrode control circuit 8 are caused to block alignment mark 4, influence alignment precision.
In the specific implementation process, the technique of alignment of the back-to-front can be the alignment of the back-to-front of ASML
Technology.Or other technique of alignment.After having made through silicon via 7, the fine throwing at 1 back side of the first wafer substrate is not carried out
Light continues to make in the cause electrode control circuit that carries out on one side for having produced alignment mark 4, because without pole control electricity is sent a telegraph
Road blocking and stacking to alignment mark, and the exposed surface at the back side after also making to through silicon via 7 has carried out fine gtinding, so that whole
Flatness of a wafer in the wafer carrying platform of exposure sources improves, in this way, which the alignment precision of back-to-front is significantly
It improves, is increased to 0.02 micron, i.e., 20 nanometers from 0.15 micron original of alignment error.
Specifically, include: in the method for 1 front preparation electrode window through ray of the first wafer substrate and deflectable element 17
Firstly, as shown in figure 4, overturning first wafer substrate 1, is alignment reference with the alignment mark 4, using back
Face prepares the electrode in the positive top silicon layer 3 of first wafer substrate 1 and buries oxide layer 2 to positive technique of alignment
Window, the electrode window through ray are aligned with the through silicon via conductive channel.
It specifically, can be first in 1 front surface coated photoresist of the first wafer substrate, then by alignment mark 4 come from the back side
It produces using deep reaction ion etching technique and is embedded in the first wafer lining in the position for making electrode window through ray by lithography to front alignment
1 front of bottom, is right against the apex electrode window of through silicon via 7, which is located at buried oxide layer 2 and the top of the first wafer substrate 1
In layer silicon 3, the opening size of the electrode window through ray is less than the cross sectional dimensions of 7 conductive channel of through silicon via, so can block
Protect a part of area on the top of through silicon via 7.
Then, the second wafer substrate 14 is placed in 1 front of the first wafer substrate, and is bonded first wafer substrate
1 and second wafer substrate 14.Specifically, 14 back side of the second wafer substrate is first carried out to thinned, inversion the second wafer lining
Bottom 14, with 1 front of the first wafer substrate described in 14 front face of the second wafer substrate by second wafer substrate 14
It is placed in 1 front of the first wafer substrate, wherein 14 front of the second wafer substrate is provided with top silicon layer and/or buries oxidation
Layer, the back side are exposed shape.
It subsequently, is alignment reference with the alignment mark 4, using the technique of alignment of back-to-front, the described in photoetching
Two wafer substrates 14 prepare the deflectable element 17.
Specifically, the preparation method of deflectable element 17 is as shown in figure 5, first carry out photoetching and depth to the second photoresist 15
Reactive ion etching produces the hinge 18 of deflectable element 17 or the groove of corbeling, and prepares deflectable element
17 movable cavity 19, the hinge 18 are top silicon layer and/or buries oxide layer.Later, by finished second wafer substrate 14
The back side upward, groove and hinge 18 or pillar be aligned downward with the first wafer substrate 1 after permanent be bonded.This bonding technology
After, the first wafer substrate 1 and the second wafer substrate 14, two wafers by processing are combined into an entirety.First
It is the electrode window through ray of the through silicon via in 1 buried oxide layer of the first wafer substrate and top silicon layer above the through silicon via of wafer substrate 1, then
The above is the thinned backing bottom (the backing bottom of second wafer substrate 14 can also completely remove) of the second wafer substrate 14, buries
Oxide layer and top silicon layer.Groove, hinge 18 or the pillar made in 14 structure of the second wafer substrate is deflectable element 17
Placement cavity 19 and its hinge or pillar.Downward according to such back side for placing i.e. the first wafer substrate 1, the second wafer lining
The lithographic process steps and deep reaction ion etching processing step after etching position 16 carries out upward, are continued in the back side at bottom 14,
Movable original part 17 can be produced.
Subsequently, step S104 is executed, first wafer substrate 1 is overturn, is alignment reference with the alignment mark 4,
The cause electrode control circuit 8 being electrically connected with the conductive channel is prepared at 1 back side of the first wafer substrate.
Preferably, as shown in fig. 6, preparation is electrically connected with the through silicon via conductive channel at 1 back side of the first wafer substrate
Before causing electrode control circuit 8, first third wafer 20 can be placed in the deflectable element 17, and it is brilliant to be bonded the third
Circle 20 and second wafer substrate 14, that is, carry out protective interim bonding, to protect deflectable element 17 to add subsequent
It is injury-free in work technique.The entirety of three wafers after being bonded twice is inverted later, i.e., by the first wafer substrate 1
Upward, the third wafer 20 being temporarily bonded for protecting moving element 17 downward, forms the dielectric layer 9 where circuit, is being situated between at the back side
Carry out sending a telegraph the manufacture craft of pole control circuit 8 on matter layer 9.The cause electrode control circuit 8 and the first wafer substrate 1 after the completion
On through silicon via 7 between have good electric interconnection, which can control or incude deflectable element 17
Movement.
Subsequently, then being bonded for the third wafer 20 and second wafer substrate 14 is released.It completes shown in Fig. 7 micro-
The production of electromechanical device.
Specifically, the present embodiment by the back side be aligned required for refer to back side alignment mark where material, into
Row surface treatment, fine grinding/polishing improve the flatness of backside of wafer, and control fine gtinding/polishing degree, protect
The alignment mark in backpiece face guarantees that the optics discrimination degree of its lines is unaffected.And setting preparation section, to avoid the back side pair
Fiducial mark note is stacked and is covered under the multilayer material where causing electrode control circuit, to improve pair of back-to-front
Quasi- precision finally improves the alignment precision between electrode window through ray and deflectable element.
In the process flow of the prior art, every alignment for carrying out a back-to-front, with the stepping exposure bench of ASML
For, alignment error will not be less than 0.15 micron.And after the method for using the present embodiment, equally exposed with the stepping of ASML
For board, every alignment for carrying out a back-to-front, alignment error promotion has been arrived will not be more high-precision less than 0.02 micron
Degree is horizontal.
Based on the same inventive concept, present invention also provides the corresponding device of the method for embodiment one, detailed in Example two.
Embodiment two
The present embodiment provides a kind of micro electro mechanical device preparation facilities, as shown in Figure 8, comprising:
Alignment modules 801, for preparing alignment mark at the first wafer substrate back side；
Channel prepares module 802, for being alignment reference with the alignment mark, in the first wafer substrate back side system
Standby conductive channel；
Deflectable element prepares module 803, is alignment ginseng with the alignment mark for overturning first wafer substrate
It examines, using the technique of alignment of back-to-front, prepares electrode window through ray and deflectable element in first wafer substrate front；
Circuit prepares module 804, is alignment reference with the alignment mark for overturning first wafer substrate,
First wafer substrate back side prepares the cause electrode control circuit being electrically connected with the conductive channel.
By the device that the embodiment of the present invention two is introduced, filled used by the method to implement the embodiment of the present invention one
It sets, so based on the method that the embodiment of the present invention one is introduced, the affiliated personnel in this field can understand the specific structure of the device
And deformation, so details are not described herein.Device used by the method for all embodiment of the present invention one belongs to the present invention and is intended to
The range of protection.
The technical solution provided in the embodiment of the present application, has at least the following technical effects or advantages:
1, method and device provided by the embodiments of the present application, after the first wafer substrate back side prepares alignment mark, first with
Alignment mark is alignment reference, prepares conductive channel at first wafer substrate back side；First wafer substrate is overturn again,
It is alignment reference with the alignment mark, using the technique of alignment of back-to-front, is prepared in first wafer substrate front
Electrode window through ray and deflectable element；First wafer substrate is finally overturn again, is alignment reference with the alignment mark, in institute
It states the first wafer substrate back side and prepares the cause electrode control circuit being electrically connected with the conductive channel.So that preparing electrode window
When mouth, deflectable element and cause electrode control circuit, alignment mark is not blocked, can effectively improve alignment precision, improves
Yield rate and device quality.
2, method and device provided by the embodiments of the present application, on the basis of retaining the alignment mark, first to described
After the one wafer substrate back side is polished directly, then with the alignment mark to be directed at reference, using the alignment of back-to-front
Technology prepares electrode window through ray and deflectable element in first wafer substrate front, does not block alignment mark not only, also make
It obtains flatness of the whole wafer in the wafer carrying platform of exposure sources to improve, further effectively improves alignment precision.
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, those skilled in the art can carry out various modification and variations without departing from this hair to the embodiment of the present invention
The spirit and scope of bright embodiment.In this way, if these modifications and variations of the embodiment of the present invention belong to the claims in the present invention
And its within the scope of equivalent technologies, then the present invention is also intended to include these modifications and variations.
Claims (10)
1. a kind of micro electro mechanical device preparation method characterized by comprising
Alignment mark is prepared at the first wafer substrate back side；
It is alignment reference with the alignment mark, prepares conductive channel at first wafer substrate back side；
First wafer substrate is overturn, is alignment reference with the alignment mark, using the technique of alignment of back-to-front,
First wafer substrate front prepares electrode window through ray and deflectable element；
First wafer substrate is overturn, is alignment reference with the alignment mark, is prepared at first wafer substrate back side
The cause electrode control circuit being electrically connected with the conductive channel.
2. the method as described in claim 1, which is characterized in that it is described the first wafer substrate back side prepare alignment mark it
Afterwards, further includes:
On the basis of retaining the alignment mark, first wafer substrate back side is polished directly.
3. method according to claim 2, which is characterized in that
It is described to prepare alignment mark at the first wafer substrate back side, comprising: at the first wafer substrate back side, preparation depth is received for 600
Rice~1200 nanometers of alignment mark；
It is described that first wafer substrate back side is polished directly, comprising: first wafer substrate back side is ground
Grinding and polishing light, the depth of the alignment mark is 300 nanometers~1100 nanometers after grinding and polishing.
4. the method as described in claim 1, which is characterized in that overturning first wafer substrate, with described to fiducial mark
It is denoted as alignment reference, using the technique of alignment of back-to-front, the preparation electrode window through ray and can in first wafer substrate front
Deflecting element, comprising:
First wafer substrate is overturn, is alignment reference with the alignment mark, using the technique of alignment of back-to-front,
The electrode window through ray is prepared in the positive top silicon layer of first wafer substrate and buries oxide layer, the electrode window through ray is led with described
Electric channel alignment；
Second wafer substrate is placed in the first wafer substrate front, and is bonded first wafer substrate and the second wafer lining
Bottom；
It is alignment reference with the alignment mark, using the technique of alignment of back-to-front, the second wafer substrate described in photoetching, system
The standby deflectable element.
5. method as claimed in claim 4, which is characterized in that described that second wafer substrate is placed in first wafer substrate
Front, comprising:
The second wafer substrate back side is carried out thinned, is inverted second wafer substrate, is connect with second wafer substrate front
It touches first wafer substrate front and second wafer substrate is placed in the first wafer substrate front, wherein is described
Second wafer substrate front is provided with top silicon layer and/or buries oxide layer.
6. method as claimed in claim 4, which is characterized in that the opening size of the electrode window through ray is less than the conductive channel
Cross sectional dimensions.
7. the method as described in claim 1, which is characterized in that described in the preparation of first wafer substrate back side and the silicon
Before the cause electrode control circuit of hole conductive channel electrical connection, further includes:
Third wafer is placed in the deflectable element, and is bonded the third wafer and second wafer substrate.
8. the method as described in claim 1, which is characterized in that described prepare at first wafer substrate back side is led with described
After the cause electrode control circuit of electric channel electrical connection, further includes:
Release being bonded for the third wafer and second wafer substrate.
9. the method as described in claim 1, which is characterized in that described with the alignment mark is alignment reference, described the
The one wafer substrate back side prepares conductive channel, comprising:
It is alignment reference with the alignment mark, at first wafer substrate back side, optical graving is for ring-shaped groove；
Dielectric filling is carried out to the ring-shaped groove；
Ion implanting or doping diffusion are carried out to the through silicon via that the ring-shaped groove surrounds, form through silicon via conductive channel.
10. a kind of micro electro mechanical device preparation facilities characterized by comprising
Alignment modules, for preparing alignment mark at the first wafer substrate back side；
Channel prepares module, for being alignment reference with the alignment mark, prepares at first wafer substrate back side conductive
Channel；
Deflectable element prepares module, for overturning first wafer substrate, is alignment reference with the alignment mark, uses
The technique of alignment of back-to-front prepares electrode window through ray and deflectable element in first wafer substrate front；
Circuit prepares module, is alignment reference with the alignment mark, described first for overturning first wafer substrate
The wafer substrate back side prepares the cause electrode control circuit being electrically connected with the conductive channel.
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