CN109524316A - A kind of semiconductor chip packaging method and semiconductor chip packaging load plate - Google Patents
A kind of semiconductor chip packaging method and semiconductor chip packaging load plate Download PDFInfo
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- CN109524316A CN109524316A CN201811251596.7A CN201811251596A CN109524316A CN 109524316 A CN109524316 A CN 109524316A CN 201811251596 A CN201811251596 A CN 201811251596A CN 109524316 A CN109524316 A CN 109524316A
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- adhesive layer
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 239000012790 adhesive layer Substances 0.000 claims abstract description 46
- 239000010410 layer Substances 0.000 claims description 38
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 238000001514 detection method Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 4
- 239000003292 glue Substances 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000009738 saturating Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001684 chronic effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67259—Position monitoring, e.g. misposition detection or presence detection
- H01L21/67265—Position monitoring, e.g. misposition detection or presence detection of substrates stored in a container, a magazine, a carrier, a boat or the like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
- H01L21/67333—Trays for chips
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
This application discloses a kind of semiconductor chip packaging method and semiconductor chip packaging load plates, the packaging method includes: the multiple chips for providing and being set on the transparent region of load plate, wherein, the first end of multiple chips is connect with the transparent region by transparent adhesive layer；Offset detector detects the physical location of each chip through the transparent region and the transparent adhesive layer, and further judges the physical location and predeterminated position with the presence or absence of offset.By the above-mentioned means, the application can carry out chip offset detection before load plate removes.
Description
Technical field
This application involves technical field of semiconductors, more particularly to a kind of semiconductor chip packaging method and semiconductor chip
Load plate is used in encapsulation.
Background technique
Semiconductor packages refers to using membrane technology and subtle processing technology, by chip and other element in frame or substrate
Upper layout pastes fixed and connection, draws connecting terminal and is fixed by the encapsulation of plasticity isolation material, constitutes independent whole knot
The technique of structure.Existing semiconductor packages includes multiple packing forms, such as fan-out-type wafer-level packaging (FOWLP) etc..
An important link is chip recombination, the i.e. rubberizing on metal load plate in entire semiconductor packages process
Band will be tested good chip and be re-pasted on metal load plate, then carries out pressing and forming, and metal load plate and glue are finally removed
Band carries out offset detection to chip.
Present inventor has found that the step of detection chip offset is generally in metal at present in chronic study procedure
It is carried out after load plate removing, which extends the packaging technology time, increases production cost.
Summary of the invention
The application is mainly solving the technical problems that provide a kind of semiconductor chip packaging method and semiconductor chip packaging
With load plate, chip offset detection can be carried out before load plate removes.
In order to solve the above technical problems, the technical solution that the application uses is: providing a kind of semiconductor chip packaging
Method, the packaging method include: the multiple chips for providing and being set on the transparent region of load plate, wherein multiple chips
First end connect with the transparent region by transparent adhesive layer；Offset detector is through the transparent region and described
Transparent adhesive layer detects the physical location of each chip, and further judges whether the physical location deposits with predeterminated position
It is deviating.
Wherein, the offset detector detects each core through the transparent region and the transparent adhesive layer
The physical location of piece, comprising: the load plate is provided with multiple chip-sides downward, the offset detector is in institute
The physical location of each chip is detected through the transparent region and the transparent adhesive layer in the other side for stating load plate.
Wherein, described that the multiple chips being set on the transparent region of load plate are provided, wherein the first of multiple chips
End is fixedly connected with the transparent region by transparent adhesive layer, comprising: provides the load plate and multiple chips, the load
Disk includes the transparent region；The transparent adhesive layer is formed in the transparent region side；Using transfer device by multiple institutes
The first end for stating chip pastes the transparent adhesive layer.
Wherein, described that one end of multiple chips is pasted into the transparent adhesive layer using transfer device, later, institute
State packaging method further include: the load plate is provided with multiple chip-sides and forms encapsulated layer, and the encapsulated layer covers
Multiple chips.
Wherein, the packaging method further include: if offset is not present in the physical location of all chips and predeterminated position,
Then the load plate, the transparent adhesive layer are removed, the first end of all chips is exposed；In all chips
The first end forms metal wiring layer again.
Wherein, the offer load plate includes: that the load plate is placed on the predetermined of external microscope carrier using positioning identifier
On position, wherein the load plate further includes the nontransparent region that the transparent region periphery is arranged in, and the positioning identifier is located at
The nontransparent region.
In order to solve the above technical problems, another technical solution that the application uses is: providing a kind of semiconductor chip envelope
Dress load plate, the load plate includes: transparent region, and the transparent region is for attaching transparent adhesive layer, and the first of multiple chips
End is fixed by the transparent adhesive layer and the transparent region.
Wherein, the load plate further includes nontransparent region, and the nontransparent region setting is peripheral in the transparent region, and
The nontransparent region is provided with positioning identifier.
Wherein, the nontransparent region is additionally provided with limiting section, and the limiting section is used for the load plate and external microscope carrier
Relative position is fixed.
Wherein, the external microscope carrier is provided with square groove, and the nontransparent area periphery of the load plate includes multiple mutual
The arc portion of connection and flat part, the flat part are defined as the limiting section, the side wall of the flat part and the square groove
It supports.
The beneficial effect of the application is: being in contrast to the prior art, load plate provided herein includes clear area
Domain, and the multiple chips being located on the transparent region of load plate are connected by transparent adhesive layer, offset detector can penetrate
Transparent region and transparent adhesive layer detect the physical location of each chip, and further judge the physical location and preset
Position is with the presence or absence of offset.When being detected in packaging method provided herein to the offset of chip, carried without removing
Disk and transparent adhesive layer reduce production cost so as to reduce the time of packaging technology.
Detailed description of the invention
In order to more clearly explain the technical solutions in the embodiments of the present application, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the drawings in the following description are only some examples of the present application, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.Wherein:
Fig. 1 is the flow diagram of one embodiment of the application semiconductor chip packaging method；
Fig. 2 is the structural schematic diagram of one embodiment of the application semiconductor chip packaging load plate；
Fig. 3 is the structural schematic diagram that an embodiment is fixed in load plate and external microscope carrier relative position in Fig. 2；
Fig. 4 is the flow diagram of the corresponding embodiment of step S101- step S102 in Fig. 1；
Fig. 5 is the structural schematic diagram of the corresponding embodiment of step S202- step S206 in Fig. 4.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of embodiments of the present application, rather than whole embodiments.Based on this
Embodiment in application, those of ordinary skill in the art are obtained every other under the premise of not making creative labor
Embodiment shall fall in the protection scope of this application.
Referring to Fig. 1, Fig. 1 is the flow diagram of one embodiment of the application semiconductor chip packaging method, the encapsulation
Method includes:
S101: multiple chips for being set on the transparent region of load plate are provided, wherein the first end of multiple chips with it is transparent
Region is connected by transparent adhesive layer.
Specifically, referring to Fig. 2, Fig. 2 is the structural representation of one embodiment of the application semiconductor chip packaging load plate
Figure.Load plate 1 includes transparent region 10, and transparent region 10 passes through transparent for attaching transparent adhesive layer, the first end of multiple chips
Adhesive layer and transparent region 10 are fixed.The material of transparent region 10 can be transparent glass, transparent plastic etc., and transparent adhesive layer can
Be transparent double face glue, transparent glue or other there is viscosity and transparent substance.Transparent region 10 can be circle, can also
For other shapes, transparent adhesive layer can be paved with entire transparent region 10, also optionally covering part transparent region 10.
In addition, in the present embodiment, please continue to refer to Fig. 2, load plate 1 provided herein further includes nontransparent region
12, the nontransparent setting of region 12 is in 10 periphery of transparent region, and nontransparent region 12 is provided with positioning identifier 14.Nontransparent region
12 material can be metal or other lighttight materials, and transparent adhesive layer can not cover the nontransparent region 12, into
And it is more convenient when making subsequent removal transparent adhesive layer.Positioning identifier 14 provided herein, which can be, to be arranged non-
The hole 14 penetrated through on area pellucida domain 12 is also possible to other other positioning identifiers 14 for having significant difference with nontransparent region 12.
In addition, load plate 1 provided herein is typically placed on the predeterminated position of external microscope carrier, to avoid load plate 1 from existing
Position is moved in encapsulation process, and please continue to refer to Fig. 2, the nontransparent region 12 of load plate 1 provided herein is also set up
There is limiting section 120, limiting section 120 is used to fix load plate 1 and external microscope carrier relative position.Referring to Fig. 3, Fig. 3 is to carry in Fig. 2
The structural schematic diagram of an embodiment is fixed in disk and external microscope carrier relative position.External microscope carrier 2 is provided with square groove 20, load plate
1 12 periphery of nontransparent region includes multiple arc portions interconnected 122 and flat part 120, and flat part 120 is defined as limiting section
120, flat part 120 and the side wall of square groove 20 are supported.Certainly, in other embodiments, limiting section 120 can also be other shapes
Formula, for example, the side wall that limiting section 120 is the first protrusion perhaps the first recess portion square groove 20 be provided with the first protrusion or
The second recess portion or the second protrusion that first recess portion matches.
To sum up, 1 structure of load plate provided herein is simple, be easy to make and cost is relatively low, reusable, energy
It is enough widely applied to semiconductor packaging industry, substantially increases the product of production efficiency, the effective rate of utilization of chip and encapsulating products
Matter.
S102: offset detector detects the physical location of each chip through transparent region and transparent adhesive layer, and
Further judge physical location and predeterminated position with the presence or absence of offset.
Specifically, offset detector can be any in the prior art, not illustrate excessively herein, for example, partially
Move amount detecting device can be image measurer, image measurer generally comprise transmission system, camera system, lighting system and
Processing system.Transmission system, camera system and lighting system cooperate, to obtain the imaging of all chip physical locations, place
Reason system compares the physical location of chip and pre-stored predeterminated position, to obtain the offset of each chip；If
Offset is in threshold value, then can determine whether physical location and predeterminated position, there is no offsets, if offset can determine whether more than threshold value
Physical location and predeterminated position, which exist, to be deviated.The selection of specific threshold value can be arranged by actual demand.
In one embodiment, referring to Fig. 4, Fig. 4 is the corresponding embodiment party of step S101- step S102 in Fig. 1
The flow diagram of formula.Semiconductor chip packaging method provided herein specifically includes:
S201: providing load plate and multiple chips, load plate include transparent region.
Specifically, in one embodiment, load plate is provided in above-mentioned steps S201 includes: to be put load plate using positioning identifier
It sets on the predetermined position of external microscope carrier, wherein load plate further includes the nontransparent region that transparent region periphery is arranged in, positioning mark
Know and is located at nontransparent region.
In another embodiment, it includes: to provide disk and carry out to disk that multiple chips are provided in above-mentioned steps S201
It checks, disk is equipped with the chip of multiple matrix arrangements, and scribe line is equipped between chip, and disk includes the positive and back side, chip
Front is the front of disk, and the back side, that is, disk back side of chip, the front of chip is provided with pad；It is attached in the front of disk
Protective film, the back side of abrasive disk, until the thickness of disk reaches predetermined thickness.In general, wafer thickness need to be thinned to original
50% come；It is cut along scribe line, and removes the protective film of chip front side, and then obtain single chip.
S202: transparent adhesive layer 3 is formed in 10 side of transparent region.
Specifically, as shown in Figure 5 a, in the present embodiment, layer of transparent bonding can be attached in the transparent region 10 of load plate 1
Layer 3.When load plate 1 includes the nontransparent region 12 being disposed around around transparent region 10, transparent adhesive layer 3 can not cover non-
Area pellucida domain 12, so that being relatively easy to when subsequent removal transparent adhesive layer 3.
S203: the first end 50 of multiple chips 5 is pasted into transparent adhesive layer 3 using transfer device 4.
Specifically, as shown in Figure 5 b, transfer device 4 can be the upper mechanical arm and suction of existing chip bonding machine platform
Mouth, for suction nozzle for adsorbing chip 5, mechanical arm is used to move the position of suction nozzle, and then will be on the mobile predeterminated position of chip 5.Separately
Outside, in the present embodiment, the first end 50 of chip 5 is one end that chip 5 is provided with pad.
S204: load plate 1 is provided with multiple 5 sides of chip downward, offset detector 6 is saturating in the other side of load plate 1
It crosses transparent region 10 and transparent adhesive layer 3 detects the physical location of each chip 5.
Specifically, as shown in Figure 5 c, at this point, if offset detector 6 detects that the position of chip 5 shifts,
The position of the chip 5 to shift can then be corrected.It certainly, in the present embodiment, can also be constant in above-mentioned steps S204
The position of dynamic load disk 1, offset detector 6 can be provided with the actual bit that each chip 5 is detected in 5 side of chip from load plate 1
It sets.
In another embodiment, provided herein after above-mentioned steps S204 please continue to refer to Fig. 4 and Fig. 5
Semiconductor chip packaging method further include:
S205: load plate 1 is provided with multiple 5 sides of chip and forms encapsulated layer 7, and encapsulated layer 7 covers multiple chips 5.
Specifically, as fig 5d, the material of encapsulated layer 7 can be epoxy resin etc..During forming encapsulated layer, by
Solidifying in 3 caking property of transparent adhesive layer, plastic packaging material 7 on the stability of board, precision, 1 thermal expansion coefficient of load plate, load plate 1
The reasons such as thermal mismatching between convergent-divergent in the process, transparent adhesive layer 3 and load plate 1 all may cause the offset of chip 5.Chip 5
Offset influences whether the alignment of subsequent metal wiring technique again, in turn results in the offset of ball lower metal layer, influences product quality.
S206: load plate 1 is provided with multiple 5 sides of chip downward, offset detector 6 is saturating in the other side of load plate 1
It crosses transparent region 10 and transparent adhesive layer 3 detects the physical location of each chip 5.
Specifically, as depicted in fig. 5e.In the prior art, the double-sided adhesive of load plate and purple is generally done using metal material,
Since load plate and purple double-sided adhesive do not have perspectivity, need to carry out after chip pressing molding, load plate, double-sided adhesive remove partially
The detection of shifting amount.The detection of laggard line displacement amount is removed in load plate, double-sided adhesive to come with some shortcomings place, from attach chip, to formation
Encapsulated layer arrives the removing of carrier double-sided adhesive again, this whole flow process needs the used time 1~1.5 day, has been completed very in this period
Multiple batches of chip recombinates, and many chips in the batch completed in this way have occurred and that offset, this, which not only increases, is produced into
This, while also extending activity time.
And mode provided herein, before load plate 1 and transparent adhesive layer 3 remove, you can learn that the offset of chip 5
Amount, if offset detector 6 detect all chips 5 physical location and predeterminated position there is no offset, by load plate 1,
Transparent adhesive layer 3 is removed, and the first end 50 of all chips 5 is exposed；Metal is formed in the first end 50 of all chips 5 to be routed again
Layer.Conversely, deviated if offset detector 6 detects that the physical location of some chip 5 and predeterminated position exist, it is whole to this
Body encapsulating structure is without subsequent processing.Therefore, compared with prior art, packaging method provided herein improves production
Efficiency saves the cost in entire packaging process.
It should be noted that the above-mentioned mode for forming metal wiring layer again in the first end 50 of chip 5 can be existing skill
It is any in art, such as:
A, the first mask layer is formed in the first end of chip, and forms first in the position that the first mask layer corresponds to pad and opens
Mouthful；
B, form the first seed layer far from the surface of chip in the first mask layer, the material of the first seed layer be titanium, aluminium,
The one such or several mixture of copper, gold, silver, the technique for forming the first seed layer is sputtering technology or physical vapour deposition (PVD)
Technique；
C, the second mask layer is formed far from the surface of chip in the first seed layer, and forms second on the second mask layer and opens
Mouthful；
D, metal wiring layer again is formed in the second opening, the technique for forming metal wiring layer again can be electroplating technology
Deng；
E, the first seed layer of the second mask layer and metal again other than wiring layer is removed, for example, can be first with photoetching
Technique removes the second mask layer, the first seed layer exposed；Then it is gone using wet-etching technology or dry etch process
Except the first seed layer of part exposed, only retain the first seed layer below metal again wiring layer.
In addition, can also carry out the processes such as subsequent plant ball, this will not be detailed here after the above-mentioned metal of formation again wiring layer.
To sum up, being in contrast to the prior art, load plate provided herein includes transparent region, and is located at and carries
Multiple chips on the transparent region of disk are connected by transparent adhesive layer, and offset detector can through transparent region and thoroughly
Bright adhesive layer detects the physical location of each chip, and further judges that the physical location and predeterminated position whether there is
Offset.When being detected in packaging method provided herein to the offset of chip, without removing load plate and transparent adhesion
Layer reduces production cost so as to reduce the time of packaging technology.
The foregoing is merely presently filed embodiments, are not intended to limit the scope of the patents of the application, all to utilize this
Equivalent structure or equivalent flow shift made by application specification and accompanying drawing content, it is relevant to be applied directly or indirectly in other
Technical field similarly includes in the scope of patent protection of the application.
Claims (10)
1. a kind of semiconductor chip packaging method, which is characterized in that the packaging method includes:
Multiple chips for being set on the transparent region of load plate are provided, wherein the first end of multiple chips with it is described transparent
Region is connected by transparent adhesive layer；
Offset detector detects the physical location of each chip through the transparent region and the transparent adhesive layer,
And further judge the physical location and predeterminated position with the presence or absence of offset.
2. packaging method according to claim 1, which is characterized in that the offset detector penetrates the clear area
Domain and the transparent adhesive layer detect the physical location of each chip, comprising:
The load plate is provided with multiple chip-sides downward, the offset detector is in the other side of the load plate
The physical location of each chip is detected through the transparent region and the transparent adhesive layer.
3. packaging method according to claim 1, which is characterized in that the offer is set on the transparent region of load plate
Multiple chips, wherein the first end of multiple chips is fixedly connected with the transparent region by transparent adhesive layer, comprising:
The load plate and multiple chips are provided, the load plate includes the transparent region；
The transparent adhesive layer is formed in the transparent region side；
The first end of multiple chips is pasted into the transparent adhesive layer using transfer device.
4. packaging method according to claim 3, which is characterized in that it is described using transfer device by multiple chips
One end pastes the transparent adhesive layer, later, the packaging method further include:
The load plate is provided with multiple chip-sides and forms encapsulated layer, and the encapsulated layer covers multiple chips.
5. packaging method according to claim 4, which is characterized in that the packaging method further include:
If there is no offsets for the physical location of all chips and predeterminated position, by the load plate, the transparent adhesive layer
The first end of removing, all chips is exposed；
Metal wiring layer again is formed in the first end of all chips.
6. packaging method according to claim 3, which is characterized in that described to provide the load plate and include:
The load plate is placed on the predetermined position of external microscope carrier using positioning identifier, wherein the load plate further includes setting
In the nontransparent region of the transparent region periphery, the positioning identifier is located at the nontransparent region.
7. a kind of semiconductor chip packaging load plate, which is characterized in that the load plate includes:
Transparent region, the transparent region pass through the transparent adhesion for attaching transparent adhesive layer, the first end of multiple chips
Layer is fixed with the transparent region.
8. load plate according to claim 7, which is characterized in that the load plate further includes nontransparent region, described nontransparent
Region setting is in the transparent region periphery, and the nontransparent region is provided with positioning identifier.
9. load plate according to claim 8, which is characterized in that the nontransparent region is additionally provided with limiting section, the limit
Position portion is used to fix the load plate and external microscope carrier relative position.
10. load plate according to claim 9, which is characterized in that
The external microscope carrier is provided with square groove, and the nontransparent area periphery of the load plate includes multiple arc portions interconnected
With flat part, the flat part is defined as the limiting section, and the flat part and the side wall of the square groove are supported.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811251596.7A CN109524316B (en) | 2018-10-25 | 2018-10-25 | Semiconductor chip packaging method and carrying disc for semiconductor chip packaging |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811251596.7A CN109524316B (en) | 2018-10-25 | 2018-10-25 | Semiconductor chip packaging method and carrying disc for semiconductor chip packaging |
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| CN109524316A true CN109524316A (en) | 2019-03-26 |
| CN109524316B CN109524316B (en) | 2021-09-21 |
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