CN109524305B - Semiconductor device based on electrode self-alignment and manufacturing method thereof - Google Patents
Semiconductor device based on electrode self-alignment and manufacturing method thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66219—Diodes with a heterojunction, e.g. resonant tunneling diodes [RTD]
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Abstract
The invention discloses a semiconductor device based on electrode self-alignment and a manufacturing method thereof.A self-alignment electrode corresponding to a collector region is formed on one side of a second doping layer, which is far away from a substrate, and an epitaxial structure on the substrate is etched by taking the self-alignment electrode as a mask to obtain a table top corresponding to the collector region; since the self-aligned electrode is formed at the corresponding position of the collector region, which is equivalent to the preparation of the ohmic electrode at the collector region, the accurate requirement of aligning the opening of the passivation film corresponding to the collector region with the connecting electrode in the subsequent process is avoided, the alignment requirement can be completed only by designing the alignment contact of the connecting electrode and the self-aligned electrode, the process difficulty of the subsequent electrode structure manufacturing is reduced, and the stability of the manufacturing process is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a semiconductor device based on electrode self-alignment and a manufacturing method thereof.
Background
In the development process of a terahertz application system, one of the key points is the development of a terahertz solid-state source which works at room temperature, has a small volume, low power consumption and high output power. A Resonant Tunneling Diode (RTD) that oscillates terahertz waves by using a Negative Differential Resistance (NDR) generated by a quantum tunneling effect becomes one of hot spots for developing terahertz solid-state sources in a terahertz micro-system due to its characteristics of small volume, easy integration, high speed, low power consumption, a small number of devices for completing various logic functions, and the like.
The early development of terahertz sources based on resonant tunneling diodes is mainly based on GaAs system materials, but is limited by material characteristics, and the power of devices is only microwatt magnitude, so that the practical application of the terahertz sources is greatly limited; in comparison, the GaN system material has the characteristics of wide forbidden band adjustable range, high electronic saturation velocity, good thermal stability and the like, and theoretically, the GaN RTD can realize power output in the milliwatt level, so that the GaN RTD is one of effective ways for improving the terahertz source performance of the RTD.
Experimental research shows that the existing GaNRTD device adopting metal organic compound chemical vapor deposition or molecular beam epitaxy growth shows obvious I-V characteristic asymmetry under forward and reverse bias and NDR characteristic degradation phenomenon after multiple voltage scanning, and is mainly attributed to the strong polarization effect of a nitride material system heterostructure, the charge accumulation effect caused by high-density defects generated by immature material epitaxy technology and the like. The electrical performance and stability of the device are improved, except for optimizing the material epitaxy technology, the device can also be improved from the aspect of device process preparation, for example, the area of a collector region of the device is reduced, the intrinsic capacitance of the device can be reduced, the frequency-increasing characteristic can be improved, the number of defects in the collector region can be reduced, and the stability of the device can be improved by electric leakage. However, the smaller the size of the mesa of the collector region prepared by using a photoresist mask is, the higher the requirement on the alignment precision of the subsequent electrode pattern is, the process difficulty is increased, and the size reduction and the device yield are further limited, so that the search and optimization of the preparation process of the GaNRTD device are realized, the process difficulty is reduced while the mesa size of the collector region is reduced, and the significance in improving the performance and the reliability of the GaN RTD device and the corresponding terahertz oscillation source is realized.
Disclosure of Invention
In view of the above, the invention provides a semiconductor device based on electrode self-alignment and a manufacturing method thereof, which effectively solve the problem of large size of a corresponding mesa of a collector region, reduce the process difficulty of subsequently manufacturing an electrode structure, and improve the stability of the manufacturing process.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
a method for manufacturing a semiconductor device based on electrode self-alignment comprises the following steps:
providing a substrate structure, wherein the substrate structure comprises a substrate, and a first doping layer, an active layer and a second doping layer which are sequentially stacked on the substrate, the surface of one side, facing the first doping layer, of the substrate is divided into a junction region and a collector pad region, and the junction region comprises an emitter region and a collector region;
forming a self-aligned electrode on one side of the second doping layer, which is far away from the substrate, and corresponding to the collector region;
etching from one side of the second doped layer to the substrate direction by taking the self-aligned electrode as a mask until the first doped layer is exposed;
removing the first doped layer except the junction region;
depositing a passivation film to cover the exposed surface of the substrate structure on the second doped layer side;
removing portions of the passivation film corresponding to the emitter region and the self-aligned electrode;
and forming an emitter on the first doping layer corresponding to the emitter region, forming a collector pad on the passivation film corresponding to the collector pad region, and forming a connection electrode for connecting the self-aligned electrode and the collector pad.
Optionally, forming a self-aligned electrode at a side of the second doped layer facing away from the substrate and corresponding to the collector region, includes:
forming a first mask layer on one side of the second doping layer, which is far away from the substrate, wherein the region of the first mask layer, which corresponds to the collector region, is a hollow region;
forming a self-aligned conductive layer on one side of the first mask layer, which is far away from the substrate;
and removing the first mask layer, and simultaneously removing the part of the self-aligned conductive layer corresponding to the first mask layer to obtain the self-aligned electrode.
Optionally, the self-aligned electrode has a diameter of 0.75 μm to 3 μm, inclusive.
Optionally, removing a portion of the first doped layer outside the junction region includes:
forming a second mask layer on one side of the self-aligned electrode, which is far away from the substrate, wherein the part of the second mask layer, which corresponds to the junction area, is a hollow area;
and removing the second mask layer after etching the part of the first doping layer corresponding to the hollowed-out area of the second mask layer.
Optionally, removing portions of the passivation film corresponding to the emitter region and the self-aligned electrode includes:
forming a third mask layer on one side, away from the substrate, of the passivation film, wherein the area, corresponding to the emitter region and the self-aligned electrode, of the third mask layer is a hollow area;
and removing the third mask layer after etching the part of the passivation film corresponding to the hollow-out area of the third mask layer.
Optionally, forming an emitter on the first doping layer corresponding to the emitter region, forming a collector pad on the passivation film corresponding to the collector pad region, and forming a connection electrode connecting the self-aligned electrode and the collector pad, includes:
forming a fourth mask on one side of the passivation film, which is far away from the substrate, wherein the fourth mask is a hollow area corresponding to the emitter region, the self-aligned electrode and the collector pad region, and an area corresponding to a connecting channel between the self-aligned electrode and the collector pad region is a hollow area;
forming an electrode layer on one side of the fourth mask layer, which is far away from the substrate;
and stripping the fourth mask layer, removing the parts of the electrode layer corresponding to the fourth mask layer, forming an emitter on the first doping layer corresponding to the emitter region, forming a collector pad on the passivation film corresponding to the collector pad region, and forming a connecting electrode corresponding to the connecting channel and connecting the self-aligned electrode and the collector pad.
Optionally, the emitter region includes an opening facing the collector pad region, and the collector region is located within the opening of the emitter region.
Optionally, the length of the connection electrode is 10 μm to 20 μm, inclusive;
and the width of the electrode connecting line is 2-4 μm, inclusive.
Correspondingly, the invention also provides a semiconductor device based on electrode self-alignment, and the semiconductor device based on electrode self-alignment is manufactured by adopting the manufacturing method of the semiconductor device based on electrode self-alignment.
Optionally, the semiconductor device based on electrode self-alignment is a resonant tunneling diode.
Compared with the prior art, the technical scheme provided by the invention at least has the following advantages:
the invention has provided a semiconductor device based on electrode self-alignment and its preparation method, form a self-alignment electrode corresponding to collector area on one side of the second doped layer deviating from the substrate at first, and then regard self-alignment electrode as the mask to etch the epitaxial structure on the substrate, and get the corresponding mesa of collector area, because the bonding strength of self-alignment electrode and second doped layer is big and difficult to drop, so, achieve the purpose of reducing the size of the corresponding mesa of collector area through the size of the accurate control self-alignment electrode, solve the large problem of the corresponding mesa size of collector area effectively;
meanwhile, since the self-aligned electrode is formed at the corresponding position of the collector region, which is equivalent to the preparation of the ohmic electrode at the collector region, the accurate requirement of aligning the opening of the passivation film corresponding to the collector region with the connecting electrode in the subsequent process is avoided, the alignment requirement can be completed only by designing the connecting electrode to be in alignment contact with the self-aligned electrode, the process difficulty of the subsequent electrode structure manufacturing is reduced, and the stability of the manufacturing process is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing a semiconductor device based on electrode self-alignment according to an embodiment of the present disclosure;
fig. 2 is a flowchart of another method for manufacturing a semiconductor device based on electrode self-alignment according to an embodiment of the present disclosure;
FIGS. 3 a-3 m are top views of corresponding structures at various steps in FIG. 2;
FIGS. 4 a-4 m are cross-sectional views of the corresponding structures in the respective steps of FIG. 2.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background art, the GaN RTD devices currently grown by using metal organic chemical vapor deposition or molecular beam epitaxy exhibit significant I-V characteristic asymmetry under forward and reverse bias and NDR characteristic degradation after multiple voltage scans, mainly due to the strong polarization effect of the heterostructure of the nitride material system, and the charge accumulation effect caused by the high density defect generated by the immature material epitaxy technology. The electrical performance and stability of the device are improved, except for optimizing the material epitaxy technology, the device can also be improved from the aspect of device process preparation, for example, the area of a collector region of the device is reduced, the intrinsic capacitance of the device can be reduced, the frequency-increasing characteristic can be improved, the number of defects in the collector region can be reduced, and the stability of the device can be improved by electric leakage. However, the smaller the size of the mesa of the collector region prepared by using a photoresist mask is, the higher the requirement on the alignment precision of the subsequent electrode pattern is, the process difficulty is increased, and the size reduction and the device yield are further limited, so that the research and optimization of the preparation process of the GaN RTD device are explored, the process difficulty is reduced while the mesa size of the collector region is reduced, and the significance of improving the performance and the reliability of the GaNRTD device and the corresponding terahertz oscillation source is achieved.
Based on this, the embodiment of the application provides a semiconductor device based on electrode self-alignment and a manufacturing method thereof, which effectively solve the problem that the size of a corresponding table top of a collector region is large, reduce the process difficulty of subsequently manufacturing an electrode structure, and improve the stability of the manufacturing process. In order to achieve the above object, the technical solutions provided by the embodiments of the present application are described in detail below, specifically with reference to fig. 1 to 4 m.
Referring to fig. 1, a flowchart of a method for manufacturing a semiconductor device based on electrode self-alignment according to an embodiment of the present application is shown, where the method includes:
s1, providing a substrate structure, wherein the substrate structure comprises a substrate, and a first doping layer, an active layer and a second doping layer which are sequentially superposed on the substrate, wherein the surface of one side of the substrate, which faces the first doping layer, is divided into a junction region and a collector pad region, and the junction region comprises an emitter region and a collector region;
s2, forming a self-aligned electrode on the side, facing away from the substrate, of the second doped layer and corresponding to the collector region;
s3, etching from one side of the second doped layer to the substrate direction by taking the self-aligned electrode as a mask until the first doped layer is exposed;
s4, removing the part of the first doped layer except the junction region;
s5, depositing a passivation film to cover the exposed surface of the substrate structure on the second doped layer side;
s6, removing parts of the passivation film corresponding to the emitter region and the self-alignment electrode;
s7, forming an emitter on the first doped layer corresponding to the emitter region, forming a collector pad on the passivation film corresponding to the collector pad region, and forming a connection electrode connecting the self-aligned electrode and the collector pad.
It can be understood that, according to the technical scheme provided by the embodiment of the application, a self-aligned electrode corresponding to the collector region is formed on one side of the second doping layer away from the substrate, and then the epitaxial structure on the substrate is etched by taking the self-aligned electrode as a mask, so that a table top corresponding to the collector region is obtained, and as the self-aligned electrode and the second doping layer have high bonding strength and are not easy to fall off, the size of the corresponding table top of the collector region is reduced by accurately controlling the size of the self-aligned electrode, and the problem of large size of the corresponding table top of the collector region is effectively solved;
meanwhile, since the self-aligned electrode is formed at the corresponding position of the collector region, which is equivalent to the preparation of the ohmic electrode at the collector region, the accurate requirement of aligning the opening of the passivation film corresponding to the collector region with the connecting electrode in the subsequent process is avoided, the alignment requirement can be completed only by designing the connecting electrode to be in alignment contact with the self-aligned electrode, the process difficulty of the subsequent electrode structure manufacturing is reduced, and the stability of the manufacturing process is improved.
As shown in fig. 2, a flowchart of another method for manufacturing a semiconductor device based on electrode self-alignment according to an embodiment of the present application is provided, where the method includes:
s1, providing a substrate structure, wherein the substrate structure comprises a substrate, and a first doping layer, an active layer and a second doping layer which are sequentially superposed on the substrate, wherein the surface of one side of the substrate, which faces the first doping layer, is divided into a junction region and a collector pad region, and the junction region comprises an emitter region and a collector region;
s2, forming a self-aligned electrode on a side of the second doped layer facing away from the substrate and corresponding to the collector region, including: s21, forming a first mask layer on one side, away from the substrate, of the second doping layer, wherein the region, corresponding to the collector region, of the first mask layer is a hollow region; s22, forming a self-aligned conductive layer on the side, away from the substrate, of the first mask layer; and S23, removing the first mask layer, and simultaneously removing the part of the self-aligned conductive layer corresponding to the first mask layer to obtain the self-aligned electrode.
S3, etching from one side of the second doped layer to the substrate direction by taking the self-aligned electrode as a mask until the first doped layer is exposed;
s4, removing the first doped layer except the junction region, including: s41, forming a second mask layer on the side, away from the substrate, of the self-aligned electrode, wherein the part, corresponding to the junction region, of the second mask layer is a hollow area; and S42, removing the second mask layer after etching the part of the first doping layer corresponding to the hollowed-out area of the second mask layer.
S5, depositing a passivation film to cover the exposed surface of the substrate structure on the second doped layer side;
s6, removing portions of the passivation film corresponding to the emitter region and the self-aligned electrode, including: s61, forming a third mask layer on the side, away from the substrate, of the passivation film, wherein the area, corresponding to the emitter region and the self-aligned electrode, of the third mask layer is a hollow area; and S62, removing the third mask layer after etching the part of the passivation film corresponding to the hollow-out area of the third mask layer.
S7, forming an emitter on the first doped layer corresponding to the emitter region, forming a collector pad on the passivation film corresponding to the collector pad region, and forming a connection electrode connecting the self-aligned electrode and the collector pad, including: s71, forming a fourth mask on the side of the passivation film, which is far away from the substrate, wherein the fourth mask is a hollow area corresponding to the emitter region, the self-aligned electrode and the collector pad region, and a region corresponding to a connecting channel between the self-aligned electrode and the collector pad region is a hollow area; s72, forming an electrode layer on one side, away from the substrate, of the fourth mask layer; s73, stripping the fourth mask layer, and removing the corresponding part of the electrode layer and the fourth mask layer, forming an emitter on the first doping layer corresponding to the emitter region, a collector pad on the passivation film corresponding to the collector pad region, and a connection electrode connecting the self-aligned electrode and the collector pad at the position corresponding to the connection channel.
The technical solution provided by the embodiment of the present application is described in more detail below with reference to fig. 3a to fig. 3m in structure, and fig. 4a to fig. 4m in structure, where fig. 3a to fig. 3m are top views of structures corresponding to each step in fig. 2, and fig. 4a to fig. 4m are cross-sectional views of structures corresponding to each step in fig. 2. It should be noted that the semiconductor device provided in the embodiments of the present application may be a resonant tunneling diode, and the following describes the manufacturing process in detail by taking the resonant tunneling diode as an example.
As shown in fig. 3a and 4a, corresponding to step S1, a substrate structure is provided, the substrate structure includes a substrate 110, and a first doped layer 120, an active layer 130, and a second doped layer 140 sequentially stacked on the substrate 110, wherein a surface of the substrate 110 facing the first doped layer 120 divides a junction region including an emitter region 111 and a collector region 112 and a collector pad region 113.
In an embodiment of the present application, the substrate provided in the present application may be a sapphire substrate, a free-standing GaN native substrate, a silicon substrate, and the like, and the present application is not particularly limited.
In an embodiment of the present application, the first doped layer and the second doped layer provided in the present application may be made of GaN or AlGaN, and the thickness of the first doped layer and the second doped layer may range from 100nm to 500nm, inclusive. Wherein, the first doped layer and the second doped layer can be doped with n + with the doping concentration not less than 1 × 1019cm-3。
The active layer provided by the embodiment of the application can comprise an emitter isolation layer, an emitter barrier layer, a potential well layer, a collector barrier layer and a collector isolation layer which are sequentially stacked. The emitter isolation layer is made of the same material as the first doping layer, the collector isolation layer is made of the same material as the second doping layer, and the thickness ranges of the emitter isolation layer and the collector isolation layer can be 5nm-30nm, including the end point value. The emitter barrier layer and the collector barrier layer can be made of AlN or AlGaN, and the thickness of the emitter barrier layer and the collector barrier layer can be in the range of 1nm-8nm, inclusive. And the material of the well layer can be GaN or InGaN, and the thickness range can be 1nm-8nm, including the end point value.
In one embodiment, the active layer provided herein is a quantum active layer of a double barrier structure, and may have a thickness ranging from 13nm to 84nm, inclusive.
Referring to fig. 3b and 4b, corresponding to step S21, a first mask layer 151 is formed on the second doped layer 140 away from the substrate 110, and a region of the first mask layer 151 corresponding to the collector region is a hollow region.
In an embodiment of the present application, a photolithography process may be used to form the first mask layer. Before the first mask layer is formed, residual metal on the surface of the structure can be removed by soaking in a metal corrosive liquid, and then the surface of the structure is cleaned by organic ultrasonic and dried; thereafter, a first photoresist layer is spun on the surface of the second doped layer facing away from the substrate, and the thickness of the first photoresist layer can be 1.5-3 μm inclusive. And then exposing and developing the first photoresist layer through a mask plate to form hollow holes with the diameter of 0.75-3 μm (inclusive) at the corresponding collector region.
Referring to fig. 3c and 4c, a self-aligned conductive layer 161 is formed on the first mask layer 151 facing away from the substrate 110, corresponding to step S22.
In an embodiment of the present application, the self-aligned conductive layer may be formed by an electron beam evaporation process or a magnetron sputtering process, and the self-aligned conductive layer provided in the embodiment of the present application may be a stack of a plurality of metal layers, where a Ti layer (having a thickness in a range of 20nm to 30nm, inclusive), an Al layer (having a thickness in a range of 140nm to 180nm, inclusive), an Ni layer (having a thickness in a range of 30nm to 50nm, inclusive), and an Au layer (having a thickness in a range of not less than 200nm) may be sequentially included.
It can be understood that, since an electrode layer needs to be formed on the self-aligned electrode later, the thickness of the Au layer provided in the embodiment of the present application is designed to be not more than 300 nm.
Referring to fig. 3d and fig. 4d, corresponding to step S23, the first mask layer 151 is removed, and at the same time, the portion of the self-aligned conductive layer 161 corresponding to the first mask layer 151 is removed, so as to obtain the self-aligned electrode 160.
In one embodiment, the self-aligned electrode provided herein may have a diameter of 0.75 μm to 3 μm, inclusive.
Referring to fig. 3e and fig. 4e, in step S3, the self-aligned electrode 160 is used as a mask to etch from the second doped layer 140 toward the substrate 110 until the first doped layer 120 is exposed.
In an embodiment of the present application, a dry etching process may be used to etch to the first doped layer. And starting etching from the second doped layer by using the self-aligned electrode as a mask through an inductive coupling ion etching process until the first doped layer is exposed by etching, so as to obtain a table top corresponding to the collector region.
In an embodiment of the present application, the vertical distance from the surface of the active layer facing the substrate side of the etched first doped layer facing away from the surface of the substrate side may be 50nm to 100nm, inclusive.
Referring to fig. 3f and fig. 4f, in step S41, a second mask layer 152 is formed on the side of the self-aligned electrode 160 away from the substrate 110, and the second mask layer 152 is a hollow area except the junction area.
In an embodiment of the present application, a second mask layer may be formed by a photolithography process, wherein a second photoresist layer is spin-coated on a side of the self-aligned electrode away from the substrate, and the second photoresist layer covers an exposed surface of the first doped layer on the side away from the substrate, and covers a surface and peripheral side surfaces of the mesa; and then, exposing and developing the second photoresist layer to obtain a second mask layer of which the parts except the corresponding junction regions are hollow regions.
Referring to fig. 3g and 4g, in step S42, after etching the portion of the first doped layer 120 corresponding to the hollowed-out region of the second mask layer 152, the second mask layer 152 is removed.
In an embodiment of the present application, a dry etching process may be used to etch the first doping layer, wherein an inductively coupled ion etching process is used to etch the hollow region of the second mask layer, and the first doping layer is etched away to expose the substrate.
In conjunction with fig. 3h and 4h, corresponding to step S5, a passivation film 170 is deposited to cover the exposed surface of the substrate structure on the second doped layer 140 side.
In an embodiment of the present application, the passivation layer coverage area is specifically an exposed surface of the substrate facing the first doping layer, a side surface and a peripheral side surface of the etched first doping layer facing away from the substrate, and a side surface and a peripheral side surface of the mesa facing away from the substrate.
The passivation film provided by the embodiment of the application can be prepared by adopting the inductively coupled ion-chemical vapor deposition, the substrate structure is put into a vacuum cavity of equipment, and SiO with the growth size of more than 300nm can be grown at the temperature of below 100 DEG C2Or Si3N4The passivation film is made of a material so as to wrap the exposed surface of the substrate facing the first doping layer, the etched first doping layer, the side surface and the table top of the first doping layer, the side surface and the side surface of the table top are deviated from the substrate, and the active layer is protected.
The passivation layer of the embodiment of the application has larger thickness, and can reduce the influence of parasitic capacitance and electric leakage between the connecting electrode and the side wall of the table top.
As shown in fig. 3i and 4i, corresponding to step S61, a third mask layer 153 is formed on the passivation film 170 on the side away from the substrate 110, and the area of the third mask layer 153 corresponding to the emitter region and the self-aligned electrode is a hollow area.
In an embodiment of the present application, a third mask layer may be formed by using a photolithography process, where the third photoresist layer formed by the photolithography process has the same formation parameters as the first photoresist layer, and after the third photoresist layer is formed, the third photoresist layer is exposed and developed to obtain the third mask layer.
Referring to fig. 3j and 4j, in step S62, after etching the passivation film 170 corresponding to the portion of the third mask layer 153, the third mask layer 153 is removed.
In an embodiment of the present application, the passivation film may be etched by dry etching, wherein the passivation film is etched by using an inductively coupled ion etching or reactive ion etching machine, and the third mask layer is removed.
Referring to fig. 3k and 4k, corresponding to step S71, a fourth mask layer 154 is formed on the passivation layer 170 facing away from the substrate 110, where the fourth mask layer 154 corresponds to the emitter region, the self-aligned electrode 160 and the collector pad region as a hollow region, and corresponds to a region connecting the connection channel 154a between the self-aligned electrode 160 and the collector pad region as a hollow region.
In an embodiment of the present application, a fourth mask layer may be formed by using a photolithography process, where the fourth photoresist layer formed by the photolithography process has the same formation parameters as the first photoresist layer, and after the fourth photoresist layer is formed, the fourth photoresist layer is exposed and developed to obtain a third mask layer.
As shown in fig. 3l and fig. 4l, corresponding to step S72, an electrode layer 180 is formed on the side of the fourth mask layer 154 away from the substrate 110.
In an embodiment of the present application, the electrode layer provided in the present application may be formed by an electron beam evaporation or magnetron sputtering process, wherein the electrode layer provided in the embodiment of the present application may be a stack of a plurality of metal layers, and may sequentially include a Ti layer (having a thickness ranging from 20nm to 30nm, inclusive), an Al layer (having a thickness ranging from 140nm to 180nm, inclusive), a Ni layer (having a thickness ranging from 30nm to 50nm, inclusive), and an Au layer (having a thickness ranging from not less than 200 nm).
Referring to fig. 3m and 4m, after stripping the fourth mask layer 154 while removing a portion of the electrode layer 180 corresponding to the fourth mask layer 154, corresponding to step S73, an emitter 181 is formed in the first doped layer 120 corresponding to the emitter region, a collector pad 182 is formed in the passivation film 170 corresponding to the collector pad region, and a connection electrode 183 is formed in the passivation film 170 corresponding to the connection channel, and a collector 184 is formed from the self-aligned electrode 160 and a portion of the electrode layer thereon.
In an embodiment of the present application, the emitter region provided by the present application includes an opening toward the collector pad region, and the collector region is located within the opening of the emitter region. Wherein the length of the connecting electrode provided by the application is 10-20 μm, inclusive;
and the width of the electrode connecting line is 2-4 μm, including the end point value, the overall area size of the connecting electrode is designed to be proper, and the generation of parasitic capacitance can be reduced.
Correspondingly, the embodiment of the application also provides a semiconductor device based on electrode self-alignment, and the semiconductor device based on electrode self-alignment is manufactured by adopting the manufacturing method of the semiconductor device based on electrode self-alignment provided by any one of the embodiments.
In an embodiment of the present application, the semiconductor device based on electrode self-alignment is a resonant tunneling diode, which may be a nitride resonant tunneling diode.
Compared with the prior art, the technical scheme provided by the embodiment of the application has at least the following advantages:
the embodiment of the application provides a semiconductor device based on electrode self-alignment and a manufacturing method thereof, wherein a self-alignment electrode corresponding to a collector region is formed on one side, away from a substrate, of a second doping layer, and then the self-alignment electrode is used as a mask to etch an epitaxial structure on the substrate, so that a table top corresponding to the collector region is obtained;
meanwhile, since the self-aligned electrode is formed at the corresponding position of the collector region, which is equivalent to the preparation of the ohmic electrode at the collector region, the accurate requirement of aligning the opening of the passivation film corresponding to the collector region with the connecting electrode in the subsequent process is avoided, the alignment requirement can be completed only by designing the connecting electrode to be in alignment contact with the self-aligned electrode, the process difficulty of the subsequent electrode structure manufacturing is reduced, and the stability of the manufacturing process is improved.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A method for manufacturing a semiconductor device based on electrode self-alignment is characterized in that the semiconductor device is a GaN device and comprises the following steps:
providing a substrate structure, wherein the substrate structure comprises a substrate, and a first doping layer, an active layer and a second doping layer which are sequentially stacked on the substrate, the surface of one side, facing the first doping layer, of the substrate is divided into a junction region and a collector pad region, and the junction region comprises an emitter region and a collector region;
forming a self-aligned electrode on one side of the second doping layer, which is far away from the substrate, and corresponding to the collector region;
etching from one side of the second doped layer to the substrate direction by taking the self-aligned electrode as a mask until the first doped layer is exposed;
removing the first doped layer except the junction region;
depositing a passivation film to cover the exposed surface of the substrate structure on the second doped layer side;
removing portions of the passivation film corresponding to the emitter region and the self-aligned electrode;
forming an emitter on the first doping layer corresponding to the emitter region, forming a collector pad on the passivation film corresponding to the collector pad region, and forming a connection electrode connecting the self-aligned electrode and the collector pad;
forming a self-aligned electrode on one side of the second doping layer, which is far away from the substrate, and corresponding to the collector region, and including:
forming a first mask layer on one side of the second doping layer, which is far away from the substrate, wherein the region of the first mask layer, which corresponds to the collector region, is a hollow region;
forming a self-aligned conductive layer on one side of the first mask layer, which is far away from the substrate;
and removing the first mask layer, and simultaneously removing the part of the self-aligned conductive layer corresponding to the first mask layer to obtain the self-aligned electrode, wherein the diameter of the self-aligned electrode is 0.75-3 μm, including the endpoint value.
2. The method for fabricating a semiconductor device based on electrode self-alignment of claim 1, wherein removing the first doped layer except for the junction region comprises:
forming a second mask layer on one side of the self-aligned electrode, which is far away from the substrate, wherein the part of the second mask layer, which corresponds to the junction area, is a hollow area;
and removing the second mask layer after etching the part of the first doping layer corresponding to the hollowed-out area of the second mask layer.
3. The method of claim 1, wherein removing portions of the passivation film corresponding to the emitter region and the self-aligned electrode comprises:
forming a third mask layer on one side, away from the substrate, of the passivation film, wherein the area, corresponding to the emitter region and the self-aligned electrode, of the third mask layer is a hollow area;
and removing the third mask layer after etching the part of the passivation film corresponding to the hollow-out area of the third mask layer.
4. The method of claim 1, wherein forming an emitter on the first doped layer corresponding to the emitter region, forming a collector pad on the passivation film corresponding to the collector pad region, and forming a connection electrode connecting the self-aligned electrode and the collector pad comprises:
forming a fourth mask on one side of the passivation film, which is far away from the substrate, wherein the fourth mask is a hollow area corresponding to the emitter region, the self-aligned electrode and the collector pad region, and an area corresponding to a connecting channel between the self-aligned electrode and the collector pad region is a hollow area;
forming an electrode layer on one side of the fourth mask layer, which is far away from the substrate;
and stripping the fourth mask layer, removing the parts of the electrode layer corresponding to the fourth mask layer, forming an emitter on the first doping layer corresponding to the emitter region, forming a collector pad on the passivation film corresponding to the collector pad region, and forming a connecting electrode corresponding to the connecting channel and connecting the self-aligned electrode and the collector pad.
5. The method of claim 1, wherein the emitter region includes an opening toward the collector pad region, and the collector region is within the emitter region opening.
6. The method of claim 5, wherein the length of the connection electrode is 10 μm-20 μm, inclusive;
and the width of the electrode connecting line is 2-4 μm, inclusive.
7. A semiconductor device based on electrode self-alignment, characterized in that the semiconductor device based on electrode self-alignment is manufactured by the method for manufacturing a semiconductor device based on electrode self-alignment according to any one of claims 1 to 6.
8. The electrode self-alignment based semiconductor device of claim 7, wherein the electrode self-alignment based semiconductor device is a resonant tunneling diode.
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