CN109493893B - Clock generation circuit, charge pump circuit and memory - Google Patents
Clock generation circuit, charge pump circuit and memory Download PDFInfo
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- CN109493893B CN109493893B CN201710817910.2A CN201710817910A CN109493893B CN 109493893 B CN109493893 B CN 109493893B CN 201710817910 A CN201710817910 A CN 201710817910A CN 109493893 B CN109493893 B CN 109493893B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
Abstract
The present invention provides a clock generation circuit for generating a clock signal, the clock generation circuit comprises a first-stage oscillator and at least one second-stage oscillator which are connected in series, the first-stage oscillator comprises a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a control end of the second switch tube and a control end of the third switch tube, the first switch tube, the second switch tube and the fourth switch tube are sequentially connected in series, the first end of the first switch tube is connected with a power supply, the first end of the fourth switch tube is grounded, the control end of the first switch tube and the control end of the fourth switch tube are respectively connected with the output end of the last second-stage oscillator in the at least one second-stage oscillator, the control end of the second switch tube is connected with the supply end of a first preset voltage, the control end of the third switch tube is connected with the supply end of a second preset voltage, a connection point between the third switch tube and the second switch tube serves as the output end of the first-stage oscillator, the voltage of the output end of the first-stage oscillator is smaller than the. The invention can effectively reduce the power consumption of the circuit.
Description
Technical Field
The present invention relates to the field of memory technologies, and in particular, to a clock generation circuit, a charge pump circuit, and a memory.
Background
The charge pump circuit in FLASH (FLASH memory) requires a clock signal. Under the application requirement of low power consumption, reducing the power consumption of the clock generation circuit is also one of the methods for improving the performance of the FLASH product.
Fig. 1 is a schematic diagram of a conventional clock generation circuit. The clock generation circuit mainly charges and discharges the capacitances of the nodes a ', b' and c 'through current source tubes (P0'/P1 '/P2', N0 '/N1'/N2 ') to form clock signals, wherein the amplitudes of the three nodes a', b 'and c' are full swing, namely the amplitudes of the three nodes a ', b' and c 'are vdd' and 0.
The existing clock generation circuit also has the following defects: when the voltage of the nodes a ', b' and c 'reaches the voltage of the turning point of the next-stage oscillator, the power consumption is still needed to continuously charge the capacitance of the nodes to vdd' or discharge to 0. This results in additional wasted power consumption and low circuit performance.
Disclosure of Invention
In view of the foregoing problems, an embodiment of the present invention provides a clock generation circuit, a charge pump circuit and a memory, so as to solve the problems of power consumption waste and low circuit performance of the conventional clock generation circuit.
In order to solve the above problem, an embodiment of the present invention discloses a clock generation circuit, including a first-stage oscillator and at least one second-stage oscillator, where the first-stage oscillator and the at least one second-stage oscillator are connected in series, the first-stage oscillator includes a first switch tube, a second switch tube, a third switch tube, and a fourth switch tube, which are connected in series in sequence, where,
the first end of the first switch tube is connected with a power supply, the first end of the fourth switch tube is grounded, the control end of the first switch tube and the control end of the fourth switch tube are respectively connected with the output end of the last second-stage oscillator in the at least one second-stage oscillator, the control end of the second switching tube is connected with the supply end of the first preset voltage, the control end of the third switching tube is connected with the supply end of the second preset voltage, the connection point between the third switching tube and the second switching tube is used as the output end of the first-stage oscillator, the output end of the first-stage oscillator is connected with the input end of the second-stage oscillator, the voltage of the output end of the first-stage oscillator is less than the voltage of the power supply, and the voltage of the output end of the first-stage oscillator is greater than or equal to the overturning voltage of the second-stage oscillator connected with the output end of the first-stage oscillator.
Optionally, the first stage oscillator further comprises:
and one end of the capacitor module is connected with the first end of the first switch tube, and the other end of the capacitor module is connected with the second end of the fourth switch tube.
Optionally, the first switch tube includes a first PMOS tube, the second switch tube includes a second PMOS tube, the third switch tube includes a first NMOS tube, and the fourth switch tube includes a second NMOS tube.
Optionally, the second-stage oscillator includes a fifth switching tube and a sixth switching tube connected in series, the first end of the fifth switching tube is connected to the power supply, the first end of the sixth switching tube is grounded, the control end of the fifth switching tube and the control end of the sixth switching tube are connected to the output end of the pre-stage oscillator, and the second end of the fifth switching tube and the second end of the sixth switching tube serve as the output end of the second-stage oscillator.
Optionally, the fifth switching tube includes a third PMOS tube, and the sixth switching tube includes a third NMOS tube.
Optionally, the second-stage oscillator further comprises:
a first end of the seventh switching tube is connected with the power supply, a second end of the seventh switching tube is connected with a first end of the fifth switching tube, and a control end of the seventh switching tube receives an enable inverted signal;
and the first end of the eighth switching tube is grounded, the second end of the eighth switching tube is connected with the first end of the sixth switching tube, and the control end of the eighth switching tube receives an enabling signal.
Optionally, the seventh switching tube includes a fourth PMOS tube, and the eighth switching tube includes a fourth NMOS tube.
In order to solve the above problem, an embodiment of the present invention further discloses a charge pump circuit, including the clock generation circuit.
In order to solve the above problem, an embodiment of the present invention further discloses a memory, including the charge pump circuit.
The embodiment of the invention has the following advantages: the clock generating circuit comprises a first-stage oscillator and at least one second-stage oscillator, the first-stage oscillator and the at least one second-stage oscillator are connected in series, the first-stage oscillator comprises a first switching tube, a second switching tube, a third switching tube and a fourth switching tube which are sequentially connected in series, the first end of the first switching tube is connected with a power supply, the first end of the fourth switching tube is grounded, the control end of the first switching tube and the control end of the fourth switching tube are respectively connected with the output end of the last second-stage oscillator in the at least one second-stage oscillator, the control end of the second switching tube is connected with the supply end of a first preset voltage, the control end of the third switching tube is connected with the supply end of a second preset voltage, the connection point between the third switching tube and the second switching tube is used as the output end of the first-stage oscillator, the output end of the first-stage oscillator is connected with the input end of the second-stage oscillator, the voltage of the output end of the first-stage oscillator is smaller than the voltage of the power supply, and the voltage of the output end of the first-stage oscillator is larger than or equal to the overturning voltage of the second-stage oscillator connected with the output end of the first-stage oscillator. Therefore, the voltage of the output end of the first-stage oscillator is smaller than the voltage of the power supply by controlling the first preset voltage and the second preset voltage, and the voltage of the output end of the first-stage oscillator is larger than or equal to the overturning voltage of the second-stage oscillator connected with the output end of the first-stage oscillator. Because the voltage of the output end of the first-stage oscillator is less than the voltage of the power supply, and the voltage of the output end of the first-stage oscillator is more than or equal to the overturning voltage of the second-stage oscillator connected with the output end of the first-stage oscillator. After the output end voltage of the front-stage oscillator reaches the turnover voltage of the rear-stage oscillator, the output end voltage of the front-stage oscillator does not need to be boosted to the voltage of a power supply or reduced to zero voltage, and the output end voltage of the front-stage oscillator always oscillates near the turnover voltage of the rear-stage oscillator. Therefore, the power consumption is effectively saved, and the performance of the circuit is improved.
Drawings
FIG. 1 is a schematic diagram of a conventional clock generation circuit;
FIG. 2 is a block diagram of a clock generation circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an embodiment of a clock generation circuit according to the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 2, which shows a block diagram of an embodiment of a clock generation circuit 1 according to the present invention, the clock generation circuit 1 may include a first stage oscillator 10 and at least one second stage oscillator 20, the first stage oscillator 10 and the at least one second stage oscillator 20 are connected in series, the first stage oscillator 10 includes a first switch tube 11, a second switch tube 12, a third switch tube 13 and a fourth switch tube 14 connected in series, wherein a first end of the first switch tube 11 is connected to the power supply 2, a first end of the fourth switch tube 14 is grounded, a control end of the first switch tube 11 and a control end of the fourth switch tube 14 are respectively connected to an output end of a last second stage oscillator 20 of the at least one second stage oscillator 20, a control end of the second switch tube 12 is connected to a supply end of a first preset voltage Vp, a control end of the third switch tube 13 is connected to a supply end of a second preset voltage Vn, the connection point between the third switch tube 13 and the second switch tube 12 is used as the output end of the first-stage oscillator 10, the output end of the first-stage oscillator 10 is connected with the input end of a second-stage oscillator 20, the voltage of the output end of the first-stage oscillator 10 is smaller than the voltage of the power supply 2, and the voltage of the output end of the first-stage oscillator 10 is larger than or equal to the turning voltage of the second-stage oscillator 20 connected with the output end of the first-stage oscillator 10.
Since the voltage at the output terminal of the first stage oscillator 10 is smaller than the voltage of the power supply 2, and the voltage at the output terminal of the first stage oscillator 10 is greater than or equal to the inversion voltage of the second stage oscillator 20 connected to the output terminal of the first stage oscillator 10. After the output end voltage of the front-stage oscillator reaches the turnover voltage of the rear-stage oscillator, the output end voltage of the front-stage oscillator does not need to be boosted to the voltage of the power supply 2 or reduced to 0, and the output end voltage of the front-stage oscillator always oscillates near the turnover voltage of the rear-stage oscillator. Therefore, power consumption is effectively saved, and the performance of the clock generation circuit 1 is improved.
Specifically, the first preset voltage Vp and the second preset voltage Vn may be controlled such that the voltage of the output terminal of the first stage oscillator 10 is less than the voltage of the power supply 2, and the voltage of the output terminal of the first stage oscillator 10 is greater than or equal to the inversion voltage of the second stage oscillator 20 connected to the output terminal of the first stage oscillator 10.
Optionally, in an embodiment of the present invention, referring to fig. 3, the first stage oscillator 10 may further include: and one end of the capacitor module 15 is connected with the first end of the first switch tube 11, and the other end of the capacitor module 15 is connected with the second end of the fourth switch tube 14. The charging and discharging speed of the first-stage oscillator 10, that is, the frequency of the clock generation circuit 1, can be adjusted by adjusting the size of the capacitor module 15. In fig. 3, the capacitance module 15 may be a capacitor C.
Alternatively, in an embodiment of the present invention, referring to fig. 3, the first switch tube 11 may include a first PMOS tube P1, the second switch tube 12 may include a second PMOS tube P2, the third switch tube 13 may include a first NMOS tube N1, and the fourth switch tube 14 may include a second NMOS tube N2.
A source end of the first PMOS transistor P1 is connected to the power supply 2, a gate end of the first PMOS transistor P1 is connected to an output end of a last second-stage oscillator 20 in the at least one second-stage oscillator 20, a source end of the second PMOS transistor P2 is connected to a drain end of the first PMOS transistor P1, a gate end of the second PMOS transistor P2 is connected to a supply end of a first preset voltage Vp, a drain end of the first NMOS transistor N1 is connected to a drain end of the second PMOS transistor P2, a gate end of the first NMOS transistor N1 is connected to a supply end of a second preset voltage Vn, a drain end of the second NMOS transistor N2 is connected to a source end of the first NMOS transistor N1, a source end of the second NMOS transistor N2 is grounded, a gate end of the second NMOS transistor N2 is connected to an output end of the last second-stage oscillator 20 in the at least one second-stage oscillator 20, and a drain end of the second NMOS transistor N2 and a drain end of the first NMOS transistor N1 are used as an output end of the first-stage oscillator 20.
Alternatively, in an embodiment of the present invention, the second-stage oscillator 20 may include a fifth switching tube 21 and a sixth switching tube 22 connected in series, a first end of the fifth switching tube 21 is connected to the power supply 2, a first end of the sixth switching tube 22 is grounded, a control end of the fifth switching tube 21 and a control end of the sixth switching tube 22 are connected to an output end of the pre-stage oscillator, and a second end of the fifth switching tube 21 and a second end of the sixth switching tube 22 serve as output ends of the second-stage oscillator 20.
Alternatively, in an embodiment of the present invention, referring to fig. 3, the fifth switching tube 21 may include a third PMOS tube P3, and the sixth switching tube 22 may include a third NMOS tube N3.
Optionally, in an embodiment of the present invention, referring to fig. 3, the second-stage oscillator 20 may further include: a seventh switching tube 23, wherein a first end of the seventh switching tube 23 is connected to the power supply 2, a second end of the seventh switching tube 23 is connected to a first end of the fifth switching tube 21, and a control end of the seventh switching tube 23 receives the enable inverted signal ENB; a first end of the eighth switching tube 24 is grounded, a second end of the eighth switching tube 24 is connected to the first end of the sixth switching tube 22, and a control end of the eighth switching tube 24 receives the enable signal EN. The eighth switching tube 24 is controlled by the enable signal EN and the seventh switching tube 23 is controlled by the enable inverted signal ENB, the seventh switching tube 23 and the eighth switching tube 24 perform a switching function, the clock generating circuit 1 can be reliably turned off, and the reliability of the clock generating circuit 1 is improved.
Alternatively, in an embodiment of the present invention, referring to fig. 3, the seventh switching tube 23 may include a fourth PMOS tube P4, and the eighth switching tube 24 may include a fourth NMOS tube N4.
Specifically, referring to fig. 3, a source terminal of a fourth PMOS transistor P4 is connected to the power supply 2, a gate terminal of the fourth PMOS transistor P4 receives the enable inverted signal ENB, a source terminal of a third PMOS transistor P3 is connected to a drain terminal of the fourth PMOS transistor P4, a gate terminal of the third PMOS transistor P3 is connected to an output terminal of the preceding oscillator, a drain terminal of a third NMOS transistor N3 is connected to a drain terminal of a third PMOS transistor P3, a gate terminal of a third NMOS transistor N3 is connected to an output terminal of the preceding oscillator, a drain terminal of the fourth NMOS transistor N4 is connected to a source terminal of a third NMOS transistor N3, a source terminal of the fourth NMOS transistor N4 is grounded, a gate terminal of the fourth NMOS transistor N4 receives the enable signal EN, and a drain terminal of the fourth NMOS transistor N4 and a drain terminal of the third NMOS transistor N3 serve as output terminals of the second stage oscillator 20.
In fig. 3, the clock generation circuit 1 includes a first-stage oscillator 10 and two second-stage oscillators 20, wherein the second-stage oscillator 20 connected to an output terminal of the first-stage oscillator 10 may be referred to as an intermediate-stage oscillator, and the second-stage oscillator 20 connected to an output terminal of the intermediate-stage oscillator may be referred to as an output-stage oscillator.
The working principle of the clock generation circuit 1 in fig. 3 is: the first preset voltage Vp and the second preset voltage Vn are preset fixed voltages, and the second PMOS transistor P2 and the first NMOS transistor N1 are always in a conducting state. When the input end voltage of the first-stage oscillator 10 (namely the output end voltage vc of the output-stage oscillator) jumps from high level to low level, the second NMOS tube N2 changes from a conducting state to a turning-off state, the first PMOS tube P1 changes from a turning-off state to a conducting state, the power supply 2 charges the capacitor C through the first PMOS tube P1, the second PMOS tube P2 and the first NMOS tube N1, when the node voltage vd between the first NMOS tube N1 and the second NMOS tube N2 gradually increases from 0 to vn-vt1, the vt1 is the threshold voltage of the first NMOS tube N1, the power supply 2 stops charging the capacitor C, the power supply 2 charges the node capacitor between the second PMOS tube P2 and the first NMOS tube N1 through the first PMOS tube P1 and the second PMOS tube P2, the node voltage between the second PMOS tube P2 and the first NMOS tube N1 is the voltage va of the first-stage oscillator until the end voltage of the first-stage oscillator 10 reaches the output end voltage va of the first-stage oscillator 10, and the output end voltage of the first-stage oscillator 10 is connected with the first-stage oscillator 10 The third NMOS transistor N3 in the intermediate-stage oscillator is turned on, the output voltage vb of the intermediate-stage oscillator is inverted, that is, vb jumps from high to low, and the output voltage vc of the output-stage oscillator is also inverted, that is, vc jumps from low to high.
In the process that the input end voltage vc of the first-stage oscillator 10 jumps from a low level to a high level, the second NMOS transistor N2 gradually changes from an off state to an on state, the first PMOS transistor P1 gradually changes from the on state to the off state, the capacitor C is discharged to the ground through the second NMOS transistor N2, the node voltage vd between the first NMOS transistor N1 and the second NMOS transistor N2 gradually decreases from vn-vt1 to 0, when vc is vt2, vt2 is the threshold voltage of the second NMOS transistor N2, the second NMOS transistor N2 is turned on, the node voltage va between the first NMOS transistor N1 and the second PMOS transistor P2 is discharged to the ground through the first NMOS transistor N1 and the second NMOS transistor N2, the node voltage va between the second PMOS transistor P2 and the first NMOS transistor N1 gradually decreases to the second inversion voltage of the intermediate-stage oscillator, at this time, the third PMOS transistor P35b is switched from a low level to a high level, that is changed to a high output voltage vb of the intermediate-stage oscillator P3, the output voltage vc of the corresponding output stage oscillator also flips, i.e., vc jumps from high to low, causing the input voltage vc of the first stage oscillator 10 to jump from high to low. In the above process, the voltage at the output end of the first-stage oscillator 10 oscillates only between the first flip-flop voltage (which may be the threshold voltage of the third NMOS transistor N3) and the second flip-flop voltage (which may be the threshold voltage of the third PMOS transistor P3) of the intermediate-stage oscillator, and the voltage at the output end of the first-stage oscillator 10 is always smaller than the voltage of the power supply 2. In the embodiment of the invention, the voltage of the output end of the first-stage oscillator 10 does not need to be boosted to the voltage of the power supply 2 or stepped down to zero voltage, so that the power consumption is effectively saved, and the performance of the circuit is improved.
Since the voltage difference between the two ends of the capacitor C is always between "the voltage of the power supply 2 to 0 voltage" and "the voltage of the power supply 2 to (vn-vt1) voltage", in the field of FLASH using the MOS transistor as the capacitor C, the voltage difference between the two ends of the capacitor C makes the capacitor of the MOS transistor always in the strong inversion layer region, that is, the capacitance value of the MOS transistor is always constant. However, the MOS capacitor c0 ' in the conventional clock generation circuit is connected to a ', and the voltage difference between the two ends of the MOS capacitor c0 ' swings between 0 and vdd ', so that the capacitance value of the MOS capacitor c0 ' changes dramatically, which results in drastic change of the output frequency of the conventional clock generation circuit and poor convergence. The capacitance value of the MOS tube is constant, so that the capacitance value of the MOS tube can still maintain a constant value even when the voltage of the power supply 2 is reduced to 1V, and the output frequency of the clock generation circuit also has good convergence. Therefore, the clock generation circuit of the embodiment of the invention has a wider applicable power supply voltage range compared with the existing clock generation circuit.
The clock generation circuit of the embodiment of the invention has the following advantages: the clock generating circuit comprises a first-stage oscillator and at least one second-stage oscillator, the first-stage oscillator and the at least one second-stage oscillator are connected in series, the first-stage oscillator comprises a first switching tube, a second switching tube, a third switching tube and a fourth switching tube which are sequentially connected in series, the first end of the first switching tube is connected with a power supply, the first end of the fourth switching tube is grounded, the control end of the first switching tube and the control end of the fourth switching tube are respectively connected with the output end of the last second-stage oscillator in the at least one second-stage oscillator, the control end of the second switching tube is connected with the supply end of a first preset voltage, the control end of the third switching tube is connected with the supply end of a second preset voltage, the connection point between the third switching tube and the second switching tube is used as the output end of the first-stage oscillator, the output end of the first-stage oscillator is connected with the input end of the second-stage oscillator, the voltage of the output end of the first-stage oscillator is smaller than the voltage of the power supply, and the voltage of the output end of the first-stage oscillator is larger than or equal to the overturning voltage of the second-stage oscillator connected with the output end of the first-stage oscillator. Therefore, the voltage of the output end of the first-stage oscillator is smaller than the voltage of the power supply by controlling the first preset voltage and the second preset voltage, and the voltage of the output end of the first-stage oscillator is larger than or equal to the overturning voltage of the second-stage oscillator connected with the output end of the first-stage oscillator. After the output end voltage of the front-stage oscillator reaches the turnover voltage of the rear-stage oscillator, the output end voltage of the front-stage oscillator does not need to be boosted to the voltage of a power supply or reduced to zero voltage, and the output end voltage of the front-stage oscillator always oscillates near the turnover voltage of the rear-stage oscillator. Therefore, the power consumption is effectively saved, the performance of the circuit is improved, and the applicable power supply voltage range is wider (for example, the power supply voltage can be as low as 1V).
The embodiment of the invention also discloses a charge pump circuit, which comprises the clock generation circuit 1.
The charge pump circuit of the embodiment of the invention has the following advantages: the clock generating circuit comprises a first-stage oscillator and at least one second-stage oscillator, the first-stage oscillator and the at least one second-stage oscillator are connected in series, the first-stage oscillator comprises a first switching tube, a second switching tube, a third switching tube and a fourth switching tube which are sequentially connected in series, the first end of the first switching tube is connected with a power supply, the first end of the fourth switching tube is grounded, the control end of the first switching tube and the control end of the fourth switching tube are respectively connected with the output end of the last second-stage oscillator in the at least one second-stage oscillator, the control end of the second switching tube is connected with the supply end of a first preset voltage, the control end of the third switching tube is connected with the supply end of a second preset voltage, the connection point between the third switching tube and the second switching tube is used as the output end of the first-stage oscillator, the output end of the first-stage oscillator is connected with the input end of the second-stage oscillator, the voltage of the output end of the first-stage oscillator is smaller than the voltage of the power supply, and the voltage of the output end of the first-stage oscillator is larger than or equal to the overturning voltage of the second-stage oscillator connected with the output end of the first-stage oscillator. Therefore, the voltage of the output end of the first-stage oscillator is smaller than the voltage of the power supply by controlling the first preset voltage and the second preset voltage, and the voltage of the output end of the first-stage oscillator is larger than or equal to the overturning voltage of the second-stage oscillator connected with the output end of the first-stage oscillator. After the output end voltage of the front-stage oscillator reaches the turnover voltage of the rear-stage oscillator, the output end voltage of the front-stage oscillator does not need to be boosted to the voltage of a power supply or reduced to zero voltage, and the output end voltage of the front-stage oscillator always oscillates near the turnover voltage of the rear-stage oscillator. Therefore, the power consumption is effectively saved, the performance of the circuit is improved, and the range of the power supply voltage which can be applied by the clock generation circuit is wider (for example, the power supply voltage can be as low as 1V).
The embodiment of the invention also discloses a memory, which comprises the charge pump circuit.
In particular, the memory may comprise a flash memory or any other memory comprising a charge pump circuit.
The memory of the embodiment of the invention has the following advantages: by arranging a clock generating circuit in the charge pump circuit to comprise a first-stage oscillator and at least one second-stage oscillator, wherein the first-stage oscillator and the at least one second-stage oscillator are connected in series, the first-stage oscillator comprises a first switching tube, a second switching tube, a third switching tube and a fourth switching tube which are sequentially connected in series, the first end of the first switching tube is connected with a power supply, the first end of the fourth switching tube is grounded, the control end of the first switching tube and the control end of the fourth switching tube are respectively connected with the output end of the last second-stage oscillator in the at least one second-stage oscillator, the control end of the second switching tube is connected with the supply end of a first preset voltage, the control end of the third switching tube is connected with the supply end of a second preset voltage, the connection point between the third switching tube and the second switching tube is used as the output end of the first-stage oscillator, the output end of the first-stage oscillator is connected with the input end of the second-stage oscillator, the voltage of the output end of the first-stage oscillator is smaller than the voltage of the power supply, and the voltage of the output end of the first-stage oscillator is larger than or equal to the overturning voltage of the second-stage oscillator connected with the output end of the first-stage oscillator. Therefore, the voltage of the output end of the first-stage oscillator is smaller than the voltage of the power supply by controlling the first preset voltage and the second preset voltage, and the voltage of the output end of the first-stage oscillator is larger than or equal to the overturning voltage of the second-stage oscillator connected with the output end of the first-stage oscillator. After the output end voltage of the front-stage oscillator reaches the turnover voltage of the rear-stage oscillator, the output end voltage of the front-stage oscillator does not need to be boosted to the voltage of a power supply or reduced to zero voltage, and the output end voltage of the front-stage oscillator always oscillates near the turnover voltage of the rear-stage oscillator. Therefore, the power consumption is effectively saved, the performance of the circuit is improved, and the range of the power supply voltage which can be applied by the clock generation circuit is wider (for example, the power supply voltage can be as low as 1V).
For the memory embodiment and the charge pump circuit embodiment, since the memory embodiment and the charge pump circuit embodiment include the clock generation circuit, the description is relatively simple, and for the relevant points, reference may be made to partial description of the clock generation circuit embodiment.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The clock generation circuit, the charge pump circuit and the memory provided by the invention are described in detail, and specific examples are applied in the description to explain the principle and the implementation of the invention, and the description of the above embodiments is only used to help understanding the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (9)
1. A clock generation circuit is characterized by comprising a first-stage oscillator and at least one second-stage oscillator, wherein the first-stage oscillator and the at least one second-stage oscillator are mutually connected in series, the first-stage oscillator comprises a first switching tube, a second switching tube, a third switching tube and a fourth switching tube which are sequentially connected in series, wherein,
the first end of the first switch tube is connected with a power supply, the first end of the fourth switch tube is grounded, the control end of the first switch tube and the control end of the fourth switch tube are respectively connected with the output end of the last second-stage oscillator in the at least one second-stage oscillator, the control end of the second switching tube is connected with the supply end of the first preset voltage, the control end of the third switching tube is connected with the supply end of the second preset voltage, the connection point between the third switching tube and the second switching tube is used as the output end of the first-stage oscillator, the output end of the first-stage oscillator is connected with the input end of the second-stage oscillator, the voltage of the output end of the first-stage oscillator is less than the voltage of the power supply, and the voltage of the output end of the first-stage oscillator is greater than or equal to the overturning voltage of the second-stage oscillator connected with the output end of the first-stage oscillator.
2. The clock generation circuit of claim 1, wherein the first stage oscillator further comprises:
and one end of the capacitor module is connected with the first end of the first switch tube, and the other end of the capacitor module is connected with the second end of the fourth switch tube.
3. The clock generation circuit of claim 1 or 2, wherein the first switch tube comprises a first PMOS tube, the second switch tube comprises a second PMOS tube, the third switch tube comprises a first NMOS tube, and the fourth switch tube comprises a second NMOS tube.
4. The clock generation circuit of claim 1, wherein the second-stage oscillator comprises a fifth switching tube and a sixth switching tube connected in series, a first end of the fifth switching tube is connected to the power supply, a first end of the sixth switching tube is connected to ground, a control end of the fifth switching tube and a control end of the sixth switching tube are connected to an output end of a preceding-stage oscillator, and a second end of the fifth switching tube and a second end of the sixth switching tube serve as output ends of the second-stage oscillator.
5. The clock generation circuit of claim 4, wherein the fifth switching tube comprises a third PMOS tube and the sixth switching tube comprises a third NMOS tube.
6. The clock generation circuit of claim 1, wherein the second stage oscillator comprises:
a fifth switching tube, a sixth switching tube, a seventh switching tube and an eighth switching tube;
the first end of the seventh switching tube is connected with the power supply, the second end of the seventh switching tube is connected with the first end of the fifth switching tube, and the control end of the seventh switching tube receives an enable inverted signal;
the control end of the fifth switching tube and the control end of the sixth switching tube are connected with the output end of a pre-stage oscillator, and the second end of the fifth switching tube and the second end of the sixth switching tube are used as the output ends of the second-stage oscillator;
the first end of the eighth switching tube is grounded, the second end of the eighth switching tube is connected with the first end of the sixth switching tube, and the control end of the eighth switching tube receives an enabling signal.
7. The clock generation circuit of claim 6, wherein the seventh switching tube comprises a fourth PMOS tube and the eighth switching tube comprises a fourth NMOS tube.
8. A charge pump circuit comprising the clock generation circuit of any one of claims 1-7.
9. A memory comprising the charge pump circuit of claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710817910.2A CN109493893B (en) | 2017-09-12 | 2017-09-12 | Clock generation circuit, charge pump circuit and memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710817910.2A CN109493893B (en) | 2017-09-12 | 2017-09-12 | Clock generation circuit, charge pump circuit and memory |
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| Publication Number | Publication Date |
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| CN109493893A CN109493893A (en) | 2019-03-19 |
| CN109493893B true CN109493893B (en) | 2020-11-06 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6359809B1 (en) * | 1997-12-10 | 2002-03-19 | Intel Corporation | Oscillator for simultaneously generating multiple clock signals of different frequencies |
| JP4246971B2 (en) * | 2002-07-15 | 2009-04-02 | 富士通マイクロエレクトロニクス株式会社 | Semiconductor memory |
| KR100834404B1 (en) * | 2007-01-03 | 2008-06-04 | 주식회사 하이닉스반도체 | Semiconductor memory device with refresh-signal generator and method for the operation |
| KR101060099B1 (en) * | 2009-03-24 | 2011-08-29 | 창원대학교 산학협력단 | DC / DC converter of Ipyrom device |
| US7902915B2 (en) * | 2009-06-08 | 2011-03-08 | Freescale Semiconductor, Inc. | Method and circuit for charging and discharging a circuit node |
| CN204886695U (en) * | 2015-09-06 | 2015-12-16 | 北京兆易创新科技股份有限公司 | High precision low power dissipation charge pump circuit |
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