CN109462558A - A kind of pair of MPLS message carries out the device of GRE encapsulation process - Google Patents
A kind of pair of MPLS message carries out the device of GRE encapsulation process Download PDFInfo
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- CN109462558A CN109462558A CN201811240095.9A CN201811240095A CN109462558A CN 109462558 A CN109462558 A CN 109462558A CN 201811240095 A CN201811240095 A CN 201811240095A CN 109462558 A CN109462558 A CN 109462558A
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- message
- programmable gate
- fpga
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/50—Routing or path finding of packets in data switching networks using label swapping, e.g. multi-protocol label switch [MPLS]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
- H04L45/745—Address table lookup; Address filtering
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/25—Routing or path finding in a switch fabric
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/35—Switches specially adapted for specific applications
- H04L49/354—Switches specially adapted for specific applications for supporting virtual local area networks [VLAN]
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention discloses the devices that a kind of pair of MPLS message carries out GRE encapsulation process, described device includes exchange chip and on-site programmable gate array FPGA, connecting port in being arranged at the special interface of the exchange chip, it is connected using the interior connecting port with on-site programmable gate array FPGA, the on-site programmable gate array FPGA is located at the side of the exchange chip as standalone module；The message encapsulated with multiprotocol label switching MPLS is sent to FPGA by the interior connecting port by exchange chip, and the encapsulation of GRE heading is completed by FPGA；FPGA returns to the exchange chip after completing encapsulation, then through the interior connecting port, to carry out message forwarding.Above-mentioned apparatus takes full advantage of advantage and FPGA customized feature of the exchange chip in terms of stream process, smaller to the logistical overhead of FPGA, has expanded the flexibility of design and application.
Description
Technical field
The present invention relates to data exchange processing technical fields more particularly to a kind of pair of MPLS message to carry out GRE encapsulation process
Device.
Background technique
Multiprotocol label switching (MPLS, Multi-Protocol Label Switching) is the label of fixed length with short
Encapsulate network layer packet, MPLS VPN is that forwarding channel runs VPN traffics, prop up the network of an operator simultaneously
The IP VPN of multiple and different clients is supportted, this requires that the network whole process of operator supports MPLS forwarding.But in practice,
Sometimes due to the reason of network planning, the intermediate equipment of carrier network not necessarily all supports MPLS function, and basic BGP/
MPLS VPN is that used Provider Equipment whole process is required to support MPLS function just can be to use basic BGP/MPLS in this way
VPN method is with regard to unworkable.
GRE (Generic Routing Encapsulation) is packaged to the datagram of certain network layer protocols,
The datagram for keeping these packed is transmitted in another network layer protocol.GRE is the layer 3 Tunnel protocol of VPN,
A kind of technology for being referred to as Tunnel is used between protocol layer, Tunnel is a virtual point-to-point connection, in reality
The virtual interface for only supporting point-to-point connection can be regarded in border as, this interface, which provides an access, enables the datagram of encapsulation
Enough transparent transmissions on this access, and data message is packaged and is decapsulated respectively at the both ends of a Tunnel.
Not the problem of intermediate equipment using very good solution carrier network of GRE does not support MPLS function, it is only necessary to operator
Edge device supports MPLS forwarding to can be achieved with function, and GRE only needs to guarantee that one-port type is identical, and centre can be worn
More other kinds of network also reduces the requirement to carrier network.
But the exchange chip in prior art is not supported mostly directly to carry out MPLS message GRE encapsulation, therefore
When Hardware Design, on-site programmable gate array FPGA (Field-Programmable Gate Array) core can use
Piece completes the partial function, it is that occur as one of the field specific integrated circuit (ASIC) semi-custom circuit,
The customization work of hardware circuit is completed with hardware description language (Verilog or VHDL), uses one piece of fpga chip in systems,
It completes to the encapsulation of MPLS message and the decapsulation work of GRE message.But the program needs to support the interface of GRE independent demand
Reserved FPGA hardware resource, it is meant that cost increases, and can not achieve the function simultaneously for the interface of no deployment FPGA, no
It is enough flexible；And consider from QoS (Quality of Service, service quality) angle, if be sent to from exchange chip
The message of FPGA reaches interface line rate, and interface flow after FPGA is plus GRE partial encapsulation, can made to be more than linear speed
Rate, to cause packet loss.And since there is no the functions of identifying message priority by FPGA, so the behavior of packet loss is random
, that is, in interface surface speed forwarding, all types of protocol massages are possible to be dropped, this also just disposes band to network
Many unexpected problems are carried out.
Summary of the invention
The object of the present invention is to provide the device that a kind of pair of MPLS message carries out GRE encapsulation process, which is made full use of
Advantage and FPGA customized feature of the exchange chip in terms of stream process, it is smaller to the logistical overhead of FPGA, it expands
The flexibility of design and application.
The purpose of the present invention is what is be achieved through the following technical solutions:
A kind of pair of MPLS message carries out the device of GRE encapsulation process, and described device includes exchange chip and field-programmable
Gate array FPGA, in which:
Connecting port in being arranged at the special interface of the exchange chip, utilizes the interior connecting port and field-programmable gate array
It arranges FPGA to be connected, the on-site programmable gate array FPGA is located at the side of the exchange chip as standalone module；
The message encapsulated with multiprotocol label switching MPLS is sent to by the exchange chip by the interior connecting port
The on-site programmable gate array FPGA is completed the encapsulation of GRE heading by the on-site programmable gate array FPGA；
The on-site programmable gate array FPGA returns to the exchange after completing encapsulation, then through the interior connecting port
Chip, and routing table is searched according to the IP use of information L3 forwarding process in encapsulated message and finds outgoing interface, turned with carrying out message
Hair.
The register for further configuring the exchange chip, to the message for being sent to the on-site programmable gate array FPGA
The frame period register of configuration message, to carry out bandwidth reservation operation.
In said device, reflecting between the LSP label mark MPLS encapsulated message of distribution and gre tunneling is further used
Relationship is penetrated, and by realization of tabling look-up in the on-site programmable gate array FPGA, to complete to distinguish envelope to different business
Dress.
All panel interfaces of described device could act as the outgoing interface of GRE message after encapsulation.
As seen from the above technical solution provided by the invention, above-mentioned apparatus takes full advantage of exchange chip in stream process
The customized feature of advantage and FPGA of aspect, it is smaller to the logistical overhead of FPGA, expand the flexibility of design and application.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this
For the those of ordinary skill in field, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is the device overall structure diagram provided in an embodiment of the present invention that GRE encapsulation process is carried out to MPLS message；
Fig. 2 is that message seals up dress process schematic in example of the embodiment of the present invention；
The message decapsulation process schematic diagram that Fig. 3 is enumerated by the embodiment of the present invention.
Specific embodiment
With reference to the attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Based on this
The embodiment of invention, every other implementation obtained by those of ordinary skill in the art without making creative efforts
Example, belongs to protection scope of the present invention.
The embodiment of the present invention is described in further detail below in conjunction with attached drawing, is implemented as shown in Figure 1 for the present invention
Example provide to MPLS message carry out GRE encapsulation process device overall structure diagram, described device include exchange chip and
On-site programmable gate array FPGA, in which:
Connecting port in being arranged at the special interface of the exchange chip, such as can be by some Ethernet of exchange chip
Interface is set as interior connecting port, is connected using the interior connecting port with on-site programmable gate array FPGA, the field programmable gate
Array FPGA is located at the side of the exchange chip as standalone module；
The message encapsulated with multiprotocol label switching MPLS is sent to by the exchange chip by the interior connecting port
The on-site programmable gate array FPGA is completed the encapsulation of GRE heading by the on-site programmable gate array FPGA；
The on-site programmable gate array FPGA returns to the exchange after completing encapsulation, then through the interior connecting port
Chip, and routing table is searched according to the IP use of information L3 forwarding process in encapsulated message and finds outgoing interface, turned with carrying out message
Hair.
In the specific implementation, because the unicity of the function of inline mouth (is only realized and increases regular length encapsulated message to message
Function, and the down direction of inline mouth does not have other kinds of message), can be by configuring posting for the exchange chip
Storage, so that it is sent to the message deficiency linear speed of the on-site programmable gate array FPGA, and after adding the FPGA encapsulation, just
Reach the line rate of the interior connecting port well, i.e., to the message configuration message for being sent to the on-site programmable gate array FPGA
Frame period (IFG, Inter-Frame Gap) register carries out just right bandwidth reservation operation, the advantage of doing so is that losing
Packet is occurred in exchange chip, can be configured according to message priority, be controllable behavior.
Further, it is possible to use between LSP label (user does not perceive) the mark MPLS encapsulated message and gre tunneling of distribution
Mapping relations, that is, the packaging information of the LSP Hold sticker value and GRE distributed be it is one-to-one, can be by looking into FPGA
Table is realized, to complete to distinguish encapsulation to different business.
All panel interfaces of above-mentioned apparatus could act as encapsulation after GRE message outgoing interface, compared to FPGA direct screening
In scheme, since hardware design limits certain some specific outgoing interface, there is apparent advantage in terms of networking flexibility.
It is described in detail, is illustrated in figure 2 with the process that specific example carries out Message processing to above-mentioned apparatus below
Message seals up dress process schematic in example of the embodiment of the present invention, as shown in Figure 2:
Normal PW business is carried out in user side interface first to extract, and is encapsulated by exchange chip according to L2VPN operation flow
For MPLS message, there is configuration to determine different from the outer layer label of L2VPN business, outer layer label at this time is allocated by software,
It is invisible to user, and there are one-to-one mapping relations with the encapsulation IP information of gre tunneling.
Specifying the business outgoing interface again is the interconnecting interface of exchange chip and FPGA, and FPGA rejects outer layer to the message received
Hold sticker is substituted for its corresponding IP+GRE encapsulation, to complete hardware view to the encapsulation work of GRE message.
At this point, the message that FPGA returns to exchange chip has had IP+GRE encapsulation, then the destination IP information by encapsulating
Chip routing table is inquired, is forwarded by some panel interface, message encapsulation process whole process is so far completed.
It is illustrated in figure 3 the message decapsulation process schematic diagram that the embodiment of the present invention is enumerated, with reference to Fig. 3:
Decapsulation operation can not be carried out to GRE message in exchange chip default process, needing to carry out gre tunneling termination
In equipment, the ACL module by chip is needed, the message for reaching panel interface is grabbed, by the GRE message weight of successful match
It is directed to exchange chip and the interior connecting port of FPGA, delivers the GRE decapsulation that FPGA carries out the first step.
Then FPGA rejects IP+GRE field therein to the GRE message received, and is substituted for corresponding reservation mark
Label, then send back to exchange chip and carry out MPLS L2VPN termination operation.
So far, tunnel edge equipment decapsulates GRE message and completes, and for L2Payload, is equivalent in entire tunnel
Transparent transmission has been carried out on road, has only carried out entering tunnel and out encapsulation and the decapsulation movement in tunnel respectively in terminal device.
It is worth noting that, the content being not described in detail in the embodiment of the present invention belongs to professional and technical personnel in the field's public affairs
The prior art known.
In conclusion device provided by the embodiment of the present invention can satisfy access net low side devices MPLS vpn over
GRE service fulfillment demand；FPGA need to only complete simple message encapsulation, decapsulation, loop fuction, for other flow controls correlation
Work is still completed by exchange chip, takes full advantage of advantage of the exchange chip in terms of stream process, while to the logic of FPGA
Expense is smaller, takes full advantage of the customized feature of FPGA, has expanded the flexibility of design and application.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
Within the technical scope of the present disclosure, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of claims
Subject to enclosing.
Claims (4)
1. the device that a kind of pair of MPLS message carries out GRE encapsulation process, which is characterized in that described device includes exchange chip and shows
Field programmable gate array FPGA, in which:
Connecting port in being arranged at the special interface of the exchange chip, utilizes the interior connecting port and field programmable gate array
FPGA is connected, and the on-site programmable gate array FPGA is located at the side of the exchange chip as standalone module；
The message encapsulated with multiprotocol label switching MPLS is sent to described by the exchange chip by the interior connecting port
On-site programmable gate array FPGA is completed the encapsulation of GRE heading by the on-site programmable gate array FPGA；
The on-site programmable gate array FPGA returns to the exchange core after completing encapsulation, then through the interior connecting port
Piece, and routing table is searched according to the IP use of information L3 forwarding process in encapsulated message and finds outgoing interface, to carry out message forwarding.
2. the device of GRE encapsulation process is carried out to MPLS message according to claim 1, which is characterized in that
The register for further configuring the exchange chip configures the message for being sent to the on-site programmable gate array FPGA
The frame period register of message, to carry out bandwidth reservation operation.
3. the device of GRE encapsulation process is carried out to MPLS message according to claim 1, which is characterized in that in described device
In, the mapping relations between the LSP label mark MPLS encapsulated message of distribution and gre tunneling are further used, and described existing
By realization of tabling look-up in field programmable gate array FPGA, to complete to distinguish encapsulation to different business.
4. the device of GRE encapsulation process is carried out to MPLS message according to claim 1, which is characterized in that
All panel interfaces of described device could act as the outgoing interface of GRE message after encapsulation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811240095.9A CN109462558A (en) | 2018-10-23 | 2018-10-23 | A kind of pair of MPLS message carries out the device of GRE encapsulation process |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811240095.9A CN109462558A (en) | 2018-10-23 | 2018-10-23 | A kind of pair of MPLS message carries out the device of GRE encapsulation process |
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| CN109462558A true CN109462558A (en) | 2019-03-12 |
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| CN201811240095.9A Pending CN109462558A (en) | 2018-10-23 | 2018-10-23 | A kind of pair of MPLS message carries out the device of GRE encapsulation process |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112583731A (en) * | 2021-01-11 | 2021-03-30 | 北京华环电子设备有限公司 | Method and device for fragmenting and recombining GRE (generic routing encapsulation) message |
| CN116501684A (en) * | 2023-06-25 | 2023-07-28 | 苏州浪潮智能科技有限公司 | Server system and communication method thereof |
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| US20080049621A1 (en) * | 2004-12-31 | 2008-02-28 | Mcguire Alan | Connection-Oriented Communications Scheme For Connection-Less Communications Traffic |
| CN106789657A (en) * | 2016-12-23 | 2017-05-31 | 北京格林伟迪科技股份有限公司 | A kind of message forwarding method and device |
| CN107395504A (en) * | 2017-07-28 | 2017-11-24 | 江西山水光电科技股份有限公司 | A kind of method and device of oversized frame service message forwarding |
| CN107689952A (en) * | 2017-07-28 | 2018-02-13 | 江西山水光电科技股份有限公司 | A kind of implementation method for supporting MPLS and GRE messages to change mutually |
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2018
- 2018-10-23 CN CN201811240095.9A patent/CN109462558A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080049621A1 (en) * | 2004-12-31 | 2008-02-28 | Mcguire Alan | Connection-Oriented Communications Scheme For Connection-Less Communications Traffic |
| CN106789657A (en) * | 2016-12-23 | 2017-05-31 | 北京格林伟迪科技股份有限公司 | A kind of message forwarding method and device |
| CN107395504A (en) * | 2017-07-28 | 2017-11-24 | 江西山水光电科技股份有限公司 | A kind of method and device of oversized frame service message forwarding |
| CN107689952A (en) * | 2017-07-28 | 2018-02-13 | 江西山水光电科技股份有限公司 | A kind of implementation method for supporting MPLS and GRE messages to change mutually |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112583731A (en) * | 2021-01-11 | 2021-03-30 | 北京华环电子设备有限公司 | Method and device for fragmenting and recombining GRE (generic routing encapsulation) message |
| CN116501684A (en) * | 2023-06-25 | 2023-07-28 | 苏州浪潮智能科技有限公司 | Server system and communication method thereof |
| CN116501684B (en) * | 2023-06-25 | 2023-09-12 | 苏州浪潮智能科技有限公司 | Server system and communication method thereof |
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