CN109435764A - A kind of the wake/sleep system and its logic control method of battery management system - Google Patents
A kind of the wake/sleep system and its logic control method of battery management system Download PDFInfo
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- CN109435764A CN109435764A CN201811526224.0A CN201811526224A CN109435764A CN 109435764 A CN109435764 A CN 109435764A CN 201811526224 A CN201811526224 A CN 201811526224A CN 109435764 A CN109435764 A CN 109435764A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02T10/70—Energy storage systems for electromobility, e.g. batteries
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Abstract
The invention discloses the wake/sleep systems and its logic control method of a kind of battery management system.Wherein, the first logic configuration switch and the second logic that the signal inputted via the D signal input part of d type flip flop is set to low level signal is configured into switch in closed state that system includes d type flip flop, in closed state externally exports activation signal and activation signal is enabled switch by the input signal that the clock signal input terminal of d type flip flop is input to d type flip flop simultaneously, the signal inputted via the clock signal input terminal of d type flip flop is set to low level signal in closed state and triggering d type flip flop acts in the off state.Only need the logic control for carrying out level translation to the clock signal input terminal and D signal input part of d type flip flop that the wake-up or suspend mode of activation signal can be realized using d type flip flop as core；Compared to existing Power Supply Monitoring IC scheme, organization plan can be more succinct, use cost and maintenance cost is lower, scalability is stronger.
Description
Technical field
The present invention relates to technical field of battery management, especially a kind of CP signal wake-up applied to battery management system/
Sleeping system and its logic control method.
Background technique
It is well known that battery management system (Battery Management System, abbreviation BMS) is battery and user
Tie between terminal can prevent battery from occurring overcharging and the problem of over-discharge to improve by battery management system
The utilization rate of battery is widely used in numerous areas such as electric car, battery truck, robot, unmanned planes.
By taking electric car as an example, with the fast development of China's new-energy automobile industry, the vehicle mounted dynamic battery that is encountered
(generally lead-acid accumulator) charging problems are also more and more；Vehicle mounted dynamic battery charging is such as carried out using exchanging trickle charge mode
When, the problem of pulling out charging gun in time and lead-acid accumulator is caused to feed is forgotten after charging electricity often, and then greatly
Ground reduces user experience effect；Main reason is that: when vehicle is fully charged and does not pull out charging gun, charging gun is to vehicle mounted electric
The activation signal of gas components (such as BMS or Vehicular charger) still has, the onboard electricals components meeting such as battery management system
It constantly works in the presence of activation signal, since the working power of these vehicle components is lead-acid accumulator, at this point,
If the DC-DC module of vehicle is in off position, lead-acid accumulator is easily caused to feed；And if vehicle
DC-DC module for a long time it is in running order, then for power battery be also it is a kind of consumption and cause the wasting of resources.
In consideration of it, at present occur on the market it is some using Power Supply Monitoring IC to activation signal carry out wake-up or dormancy control
Solution, but the use cost of such scheme is high and be not easy to safeguard.Therefore, there is an urgent need to a kind of low in cost and can fit
The solution of activation wake-up or suspend mode is carried out for rigid line, the charging signals line etc. to vehicle components.
Summary of the invention
In view of the deficiency of the prior art, the first purpose of this invention is to provide a kind of applied to cell tube
The CP signal wake/sleep system of reason system；Second object of the present invention is to provide a kind of logic based on above system
Control method.
To achieve the goals above, first technical solution that the present invention uses are as follows:
A kind of CP signal wake/sleep system applied to battery management system, it includes the original of a D signal input part
Input signal externally exports for the d type flip flop of high level signal, in closed state by activation signal and simultaneously by activation signal
The enabled switch of the input signal that d type flip flop is input to by the clock signal input terminal of d type flip flop, in closed state will be via D
The signal that the clock signal input terminal of trigger is inputted is set to low level signal and triggering d type flip flop carries out in the off state
The signal that the first logic configuration of movement is switched and will be inputted in closed state via the D signal input part of d type flip flop
It is set to the second logic configuration switch of low level signal.
Preferably, it further includes one for CP pulsed activation signal to be converted to direct current input activation signal and is believed input
Number enabled switch makees the input signal processing module of on-off control.
Preferably, the input signal processing module includes one sharp for CP pulsed activation signal to be converted to direct current input
The amplitude detection circuit of signal living and the signal that is exported according to amplitude detection circuit lead to the enabled switch of input signal
The signal circuit of disconnected control.
Preferably, it further includes one for being become according to the clock signal input terminal of d type flip flop and the level of Q signal output end
Change to decide whether that the output signal processing module for externally exporting activation signal, the output signal processing module are serially connected with D touching
It sends out between the clock signal input terminal and Q signal output end of device and is connected simultaneously with the ground terminal of d type flip flop.
Preferably, the output signal processing module includes first diode and the second diode, the first diode
Anode connect one end of the enabled switch of input signal simultaneously and clock signal input terminal, the cathode of d type flip flop are connected to second
The anode of diode, the cathode of second diode connect the Q signal output and ground of d type flip flop simultaneously；Described
As the activation signal output end of output signal processing module between the cathode of one diode and the anode of the second diode.
Preferably, the enabled switch of the input signal is serially connected with the clock signal input terminal and power input of d type flip flop
Between, one end of the first logic configuration switch is connected to the clock signal input of input signal enabled switch and d type flip flop
Between end, the other end be connected with the ground terminal of d type flip flop, one end of second logic configuration switch D with d type flip flop simultaneously
Signal input part and power input are connected, the other end is connected with the ground terminal of d type flip flop.
Preferably, it further includes third logic configuration switch, and one end of third logic configuration switch is connected to the
One logic configuration switch the clock signal input terminal of d type flip flop between, the other end connection d type flip flop power input.
Second technical solution that the present invention uses for
A kind of logic control method based on the above-mentioned CP signal wake/sleep system applied to battery management system,
It includes
S1, control the first logic configuration switch and the second logic configuration switch make to be both at off-state, to input
The enabled switch of signal applies activation signal so that input signal enables switch conduction, and cut-off is defeated by the Q signal output end of d type flip flop
High level signal out, so that activation signal is directly externally exported via the enabled switch of input signal, to realize that system CP believes
Number wake-up；
S2, control the first logic configuration switch and the second logic configuration switch make to be both at off-state, cancel to
The activation signal that the enabled switch of input signal applies, exports system without activation signal, thus the case where cancelling activation signal
The suspend mode of lower realization system CP signal；
S3, apply activation signal to the enabled switch of input signal so that input signal enables switch conduction, while controlling the
One logic configures switch conduction so that the clock signal input terminal of d type flip flop is set to low level, control the second logic configuration switch
Then conducting controls the first logic configuration switch and disconnects to trigger D touching so that the D signal input part of d type flip flop is set to low level
Device movement is sent out, by making the Q signal output end of d type flip flop export low level and ending via the enabled switch output of input signal
Activation signal mode make system without activation signal export, thus in the case where retaining activation signal realization system CP signal
Suspend mode.
As the above scheme is adopted, the present invention only needs the clock signal input terminal to d type flip flop using d type flip flop as core
The wake-up or suspend mode of activation signal can be realized in the logic control for carrying out level translation with D signal input part；Compared to existing
Power Supply Monitoring IC scheme, organization plan can be more succinct, and system power dissipation, use cost and maintenance cost are lower；Meanwhile it can expand
Malleability is stronger, is not only able to be applicable to the BMS system of the electric car of activation signal work, can also be applicable to swash
Other vehicle components or industrial products of signal work living, have very strong practical value and market popularization value
Detailed description of the invention
Fig. 1 is the circuit topology schematic diagram of the embodiment of the present invention.
Specific embodiment
The embodiment of the present invention is described in detail below in conjunction with attached drawing, but the present invention can be defined by the claims
Implement with the multitude of different ways of covering.
As shown in Figure 1, a kind of CP signal wake/sleep system applied to battery management system provided in this embodiment,
It includes:
D type flip flop 10, the original input signal of D signal input part are that high level signal (that is: is defaulted as high level letter
Number)；
Input signal enables switch K, can carry out the change that is turned on or off by applying or cancelling activation signal to it
It changes, and activation signal can externally be exported in closed state and clock signal by activation signal by d type flip flop 10 simultaneously
Input terminal is input to d type flip flop 10, in the clock signal input terminal of d type flip flop 10 there are when hopping edge (that is: rising edge), D
The D signal input pin and Q signal output pin of trigger are set to high level；
First logic configures switch K1, can control software program in component in CPU etc. by burning and carry out to it
The logic control being turned on or off, can be defeated by the clock signal input terminal institute via d type flip flop 10 in closed state
The signal entered is set to low level signal and triggering d type flip flop 10 is acted in the off state；
Second logic configures switch K2, can control software program in component in CPU etc. by burning and carry out to it
The logic control being turned on or off will can be inputted via the D signal input part of d type flip flop 10 in closed state
Signal is set to low level signal.
It is as a result, the core of whole system with d type flip flop 10, by enabling switch K to input signal, the first logic configures
The on-off conversion and control of switch K1 and the second logic configuration switch K2, to realize clock signal input terminal and D to d type flip flop 10
The level height transformation control of signal input part, to be created condition to realize to the wake-up output or suspend mode of activation signal；
When the system architecture using the present embodiment carries out suspend mode or wake up manipulation to activation signal, following logic control side can refer to
Method, specifically:
S1, the first logic of control configuration switch K1 and the second logic configuration switch K2 make to be both at off-state, to
Input signal enables switch K and applies activation signal so that the enabled switch K conducting of input signal, ends the Q signal by d type flip flop 10
The high level signal of output end output externally exports so that activation signal directly can enable switch K via input signal, thus
The activation of realization system CP signal wakes up；
S2, the first logic of control configuration switch K1 and the second logic configuration switch K2 make to be both at off-state, remove
It sells to input signal and enables the activation signal that switch K is applied, export system without activation signal, thus in revocation activation signal
In the case where realize system CP signal suspend mode；
S3, switch K application activation signal is enabled to input signal so that the enabled switch K conducting of input signal, controls simultaneously
The configuration switch K1 conducting of first logic is matched so that the clock signal input terminal of d type flip flop 10 is set to low level, controls the second logic
Switch K2 conducting is set so that the D signal input part of d type flip flop 10 is set to low level, it is disconnected then to control the first logic configuration switch K1
It opens to trigger the movement of d type flip flop 10, by making the Q signal output end of d type flip flop 10 export low level and ending via input
The mode that signal enables the activation signal of switch K output exports system without activation signal, thus in the feelings for retaining activation signal
The suspend mode of system CP signal is realized under condition.
It is that the system that core is constituted only needs clock signal input terminal and D to d type flip flop 10 with d type flip flop 10 based on this
The wake-up or suspend mode of activation signal can be realized in the logic control that signal input part carries out level translation；Compared to existing power supply
IC scheme is monitored, the organization plan of the system of the present embodiment can be more succinct, and system power dissipation, use cost and maintenance cost are more
It is low；Meanwhile scalability is stronger, is not only able to be applicable to the BMS system of the electric car of activation signal work, also can
It is applicable to other vehicle components or industrial products of activation signal work.
For the reliability and stability for guaranteeing activation signal input, the system of the present embodiment further includes one for by CP pulse
Activation signal is converted to direct current input activation signal and enables the input signal processing mould that switch K makees on-off control to input signal
Block.Wherein, preferably, the input signal processing module of the present embodiment is mainly transmitted by amplitude detection circuit 20 and signal
Circuit 30 is constituted, and amplitude detection circuit 20 is mainly used for being converted to CP pulsed activation signal into direct current input activation signal (amplitude
Detection circuit 20 can be according to the actual situation using at present on the market with the circuit structure of similar functions), signal circuit 30
The signal then mainly exported according to amplitude detection circuit 20 switch K enabled to input signal makees on-off control to input
The enabled switch K of signal can make activation signal make subsequent transmission in the state of being on, and (signal circuit 30 can be according to reality
Border situation is composed of electronic components such as NMOS tube, PNP triode, photoelectrical couplers, or using on the market its
His circuit structure with similar functions).
Reliability and stability to guarantee activation signal output are (especially defeated to the Q signal output end of d type flip flop 10
High level signal out is ended, and is directly externally exported so that activation signal can only enable switch K via input signal), this
The system of embodiment further includes one for according to the clock signal input terminal of d type flip flop 10 and the level change of Q signal output end
To decide whether that (such as clock signal input terminal of d type flip flop 10 is height to the output signal processing module of externally output activation signal
When level signal, the activation signal for enabling switch K input via input signal is externally exported；When d type flip flop 10
When clock signal input part is low level signal and signal output switch K output activation signal, then the output of activation signal can be prevented
To enter the dormant state of system), it is serially connected between the clock signal input terminal of d type flip flop 10 and Q signal output end and same
When be connected with the ground terminal of d type flip flop 10 (in the specific implementation, can d type flip flop 10 ground terminal and signal output processing mould
The electronic components such as first resistor R1 are set between block).As a result, using signal processing output module as whole system
Signal o controller part come use, realize to activation signal wake-up output or suspend mode control.
Preferably, the output signal processing module of the present embodiment is mainly by first diode D1 and the second diode
D2 is constituted；Wherein, first diode D1 anode simultaneously connect input signal enable switch K one end and d type flip flop 10 when
(cathode that in the specific implementation, input signal enables switch K and first diode D1 can be by the of setting for clock signal input part
Two resistance R2 are connected with the clock signal input terminal of d type flip flop 10), cathode be connected to the anode of the second diode D2, the two or two
The Q signal output and ground that the cathode of pole pipe D2 connects d type flip flop 10 simultaneously (that is: can be triggered by first resistor R1 and D
The ground terminal of device 10 is connected)；It is handled between the cathode of first diode D1 and the anode of the second diode D2 as output signal
The activation signal output end of module.As a result, when the Q signal output end of d type flip flop 10 is high level, the second diode D2 is cut
Only, activation signal to enable switch K and first diode D1 via input signal externally to transmit；Conversely, working as d type flip flop
When 10 clock signal input terminal is low level, then it may make what the activation signal output end of output signal processing module was exported
Signal is low level (that is: entering activation signal dormant state).
For the circuit topological structure for optimizing whole system to the maximum extent, guarantee the function effect between related device
Fruit, the input signal of the present embodiment enable switch K and are serially connected between the clock signal input terminal and power input of d type flip flop 10
(in the specific implementation, can by the 3rd resistor R3 and second resistance R3 above-mentioned of setting by input signal enable switch K into
Row concatenation), one end of the first logic configuration switch K1 is connected to the clock signal that input signal enables switch K and d type flip flop 10
Between input terminal, the other end be connected with the ground terminal of d type flip flop 10, the second logic configure switch K2 one end simultaneously with D triggering
The D signal input part of device 10 is connected with power input (in the specific implementation, can realize second by the 4th resistance R4 of setting
The connection of logic configuration switch K2 and d type flip flop 10), the other end is connected with the ground terminal of d type flip flop 10.As a result, based on described
And related device between connection relationship, in conjunction with logic control method above-mentioned can be realized the wake-up to activation signal output
Or suspend mode.
Preferably, the system of the present embodiment further includes third logic configuration switch K3, and the configuration of third logic is opened
The one end (in the specific implementation, using the 5th resistance R5 of setting) for closing K3 is connected to the first logic configuration switch K1 and D and touches
It sends out between the clock signal input terminal of device 10, the other end then connects the power input of d type flip flop 10.As a result, in BMS etc.
After needing the workable vehicle component of activation signal ability to be activated, to control the configuration switch K3 closure conducting of third logic, instead
Then disconnect, to be to realize to enable switch K and the first logic to input signal and configure to open using third logic configuration switch K3
The conversion and control that is turned on or off for closing K1 provides basis of signals.Certainly, the logic configuration switch that the present embodiment is addressed can basis
Actual conditions use the electronic components such as photoelectrical coupler, triode；And it is the stabilization for guaranteeing to power to d type flip flop 10
Property, it is realized using linear voltage regulator 40 and the electricity of d type flip flop 10 is supplied.
In conclusion the effect between the circuit topological structure of the system based on the present embodiment and each component is closed
System, and cooperate corresponding logic control method, the mode adjusting to whole system can be realized, specifically:
1, activation signal wakes up output mode:
Typical activation signal source is CP PWM wave, will by amplitude detection circuit 20 after activation signal input
Pwm pulse signal becomes direct-flow input signal, and input signal is then connected by signal circuit 30 again and enables switch K；
Due to d type flip flop 10 be defaulted as high level input and its output end be grounded, input signal enable switch K be switched on after, D trigger
There are a hopping edge (that is: rising edges) for the clock signal input terminal of device 10, so that the D signal input part and Q of d type flip flop 10
Signal output end is high level, and the second diode D1 is ended, and activation signal is exported via first diode D1, to realize
The wake-up of activation signal exports.
2, the signal suspend mode after removing activation signal: after revocation activation signal, input signal enables switch K cut-off
(that is: disconnecting), whole system so that the Q signal output end of d type flip flop 10 is low level, and then cause whole without activation signal source
A system is exported without activation signal, it may be assumed that enters suspend mode.
3, signal suspend mode when activation signal is not removed: firstly, control the first logic configuration switch K1 conducting (D touching
Hair device 10 clock signal input terminal become low level), control the second logic configuration switch K2 be connected (the D signal of d type flip flop 10
Input terminal becomes low level)；Then, the first logic configuration switch K1 is disconnected to trigger the movement of d type flip flop 10；At this point, d type flip flop
10 D signal input part and Q signal output end is low level, and output signal is pulled low, and does not remove activation signal to realize
Signal suspend mode.
4, activation signal being removed under dormant state will not restart: after entering signal suspend mode, then cancelling activation signal, make
It obtains input signal and enables switch K cut-off (that is: disconnecting), since whole system is without activation signal source, the Q signal of d type flip flop 10 is defeated
Outlet is low level, and then causes whole system to export without activation signal, therefore will not reactivate system.
The above description is only a preferred embodiment of the present invention, is not intended to limit the scope of the invention, all utilizations
Equivalent structure or equivalent flow shift made by description of the invention and accompanying drawing content is applied directly or indirectly in other correlations
Technical field, be included within the scope of the present invention.
Claims (8)
1. a kind of CP signal wake/sleep system applied to battery management system, it is characterised in that: it includes that a D signal is defeated
The original input signal for entering end is the d type flip flop of high level signal, in closed state externally exports activation signal and simultaneously
Activation signal is enabled into switch by the input signal that the clock signal input terminal of d type flip flop is input to d type flip flop, in closed state
It is lower that the signal inputted via the clock signal input terminal of d type flip flop is set to low level signal and triggers D in the off state
The first logic configuration that trigger is acted switchs and in closed state will be via the D signal input part institute of d type flip flop
The signal of input is set to the second logic configuration switch of low level signal.
2. a kind of CP signal wake/sleep system applied to battery management system as described in claim 1, feature exist
In: it further includes one for CP pulsed activation signal to be converted to direct current input activation signal and is made to the enabled switch of input signal
The input signal processing module of on-off control.
3. a kind of CP signal wake/sleep system applied to battery management system as claimed in claim 2, feature exist
In: the input signal processing module includes one for CP pulsed activation signal to be converted to the amplitude of direct current input activation signal
Detection circuit and the signal that is exported according to amplitude detection circuit make the signal of on-off control to the enabled switch of input signal
Transmission circuit.
4. a kind of CP signal wake/sleep system applied to battery management system as described in claim 1, feature exist
In: it further includes one for being decided whether according to the level change of the clock signal input terminal of d type flip flop and Q signal output end
The externally output signal processing module of output activation signal, the output signal processing module are serially connected with the clock letter of d type flip flop
Number it is connected between input terminal and Q signal output end and simultaneously with the ground terminal of d type flip flop.
5. a kind of CP signal wake/sleep system applied to battery management system as claimed in claim 4, feature exist
In: the output signal processing module includes first diode and the second diode, and the anode of the first diode connects simultaneously
The clock signal input terminal, cathode of one end and d type flip flop for connecing the enabled switch of input signal are connected to the anode of the second diode,
The cathode of second diode connects the Q signal output and ground of d type flip flop simultaneously；The cathode of the first diode
As the activation signal output end of output signal processing module between the anode of the second diode.
6. a kind of CP signal wake/sleep system applied to battery management system according to any one of claims 1 to 5,
It is characterized by: the enabled switch of the input signal is serially connected between the clock signal input terminal of d type flip flop and power input,
One end of first logic configuration switch be connected to the enabled switch of input signal and d type flip flop clock signal input terminal it
Between, the other end be connected with the ground terminal of d type flip flop, one end of second logic configuration switch D signal with d type flip flop simultaneously
Input terminal and power input are connected, the other end is connected with the ground terminal of d type flip flop.
7. a kind of CP signal wake/sleep system applied to battery management system as claimed in claim 6, feature exist
In: it further includes third logic configuration switch, and one end of the third logic configuration switch is connected to the configuration of the first logic and opens
It closes between the clock signal input terminal of d type flip flop, the power input of other end connection d type flip flop.
8. a kind of logic control based on the CP signal wake/sleep system described in claim 1 applied to battery management system
Method processed, it is characterised in that: it includes
S1, control the first logic configuration switch and the second logic configuration switch make to be both at off-state, to input signal
Enabled switch applies activation signal so that input signal enables switch conduction, and cut-off is exported by the Q signal output end of d type flip flop
High level signal, so that activation signal is directly externally exported via the enabled switch of input signal, to realize system CP signal
It wakes up；
S2, control the first logic configuration switch and the second logic configuration switch make to be both at off-state, cancel to input
The activation signal that the enabled switch of signal applies, exports system without activation signal, thus real in the case where cancelling activation signal
The suspend mode of existing system CP signal；
S3, apply activation signal to the enabled switch of input signal so that input signal enables switch conduction, while controlling first and patrolling
Configuration switch conduction is collected so that the clock signal input terminal of d type flip flop is set to low level, control the second logic configuration switch conduction
The D signal input part of d type flip flop is set to low level, then controls the first logic configuration switch and disconnect to trigger d type flip flop
Movement, by making the Q signal output end of d type flip flop export low level and ending swashing via the enabled switch output of input signal
The mode of signal living exports system without activation signal, to realize stopping for system CP signal in the case where retaining activation signal
It sleeps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811526224.0A CN109435764A (en) | 2018-12-13 | 2018-12-13 | A kind of the wake/sleep system and its logic control method of battery management system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811526224.0A CN109435764A (en) | 2018-12-13 | 2018-12-13 | A kind of the wake/sleep system and its logic control method of battery management system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110525248A (en) * | 2019-08-26 | 2019-12-03 | 东风汽车有限公司 | Electric automobile charging connection awakens up detection device |
| CN110920392A (en) * | 2019-11-19 | 2020-03-27 | 珠海格力电器股份有限公司 | Power supply control circuit, power supply control method and new energy automobile |
-
2018
- 2018-12-13 CN CN201811526224.0A patent/CN109435764A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110525248A (en) * | 2019-08-26 | 2019-12-03 | 东风汽车有限公司 | Electric automobile charging connection awakens up detection device |
| CN110525248B (en) * | 2019-08-26 | 2021-03-09 | 东风汽车有限公司 | Electric automobile charging connection awakens up detection device |
| CN110920392A (en) * | 2019-11-19 | 2020-03-27 | 珠海格力电器股份有限公司 | Power supply control circuit, power supply control method and new energy automobile |
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