CN109427711A - The heat-radiating substrate based on diamond of IC chip - Google Patents
The heat-radiating substrate based on diamond of IC chip Download PDFInfo
- Publication number
- CN109427711A CN109427711A CN201811006587.1A CN201811006587A CN109427711A CN 109427711 A CN109427711 A CN 109427711A CN 201811006587 A CN201811006587 A CN 201811006587A CN 109427711 A CN109427711 A CN 109427711A
- Authority
- CN
- China
- Prior art keywords
- chip
- hole
- diamond
- heat
- radiating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910003460 diamond Inorganic materials 0.000 title claims abstract description 74
- 239000010432 diamond Substances 0.000 title claims abstract description 74
- 239000000758 substrate Substances 0.000 title claims abstract description 59
- 238000005538 encapsulation Methods 0.000 claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 15
- 239000011159 matrix material Substances 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 5
- 239000002245 particle Substances 0.000 claims description 5
- 239000002131 composite material Substances 0.000 claims description 4
- 238000010884 ion-beam technique Methods 0.000 claims description 4
- 239000004575 stone Substances 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 34
- 239000004065 semiconductor Substances 0.000 description 16
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 15
- 239000011156 metal matrix composite Substances 0.000 description 15
- 229910002601 GaN Inorganic materials 0.000 description 14
- 239000000463 material Substances 0.000 description 11
- 229910002704 AlGaN Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 7
- 230000017525 heat dissipation Effects 0.000 description 7
- 238000005259 measurement Methods 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 230000009467 reduction Effects 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 230000005496 eutectics Effects 0.000 description 4
- 238000002474 experimental method Methods 0.000 description 4
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000003746 surface roughness Effects 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000011435 rock Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 238000003786 synthesis reaction Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910016525 CuMo Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 241001125929 Trisopterus luscus Species 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000010267 cellular communication Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 210000002615 epidermis Anatomy 0.000 description 1
- -1 for example Substances 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3732—Diamonds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
Abstract
This disclosure relates to the heat-radiating substrate based on diamond of IC chip.Disclosed technology relate generally to integrated circuit (IC) encapsulation, relate more specifically to include perforation the heat-radiating substrate based on diamond integrated antenna package.In an aspect, IC chip is configured to attach to for the heat-radiating substrate of IC chip and radiate from it.The through-hole array that heat-radiating substrate based on diamond can have conductive surface and pass through.At least one of through-hole is configured as when being attached to the heat-radiating substrate based on diamond and the imbricate of IC chip.
Description
Any priority application is introduced by reference
According to 37 CFR 1.57, foreign country or domestic priority requirement have been determined in the application data form that the application submits
Any and all applications be incorporated herein by reference.
Technical field
Disclosed technology relates generally to integrated circuit and integrated circuit device, relates more specifically to include based on diamond
Substrate integrated circuit and integrated circuit device.
Background technique
With active and the power of passive semiconductor integrated circuit (IC) device and the increase of current densities, IC device is in work
Heat management during work increasingly becomes challenge.Since heat management is insufficient, since device temperature increases, the performance meeting of IC device
It is affected, or even permanent structural failure can occur.For example, IC chip with for packaging certain integrated morphologies (such as
Radiator) between the mismatch of thermal expansion coefficient can lead to permanent structure failure, for example, the crack (solder in adhesive layer
Or solder metal) between IC chip and bottom plate or radiator, or in extreme circumstances, itself there is crack in IC chip.For one
A little high power IC devices, such as radio frequency (RF) power transistor and other high-power pulsed ion beams, may include such as broadband
The compound semiconductor of gap (WBG) semiconductor, effective heat management may bring especially difficult challenge.This may be because removing
Except the higher levels of heat that IC device generates, certain integrated morphologies for encapsulating high power IC device (such as radiate
Device) it should also be used to provide RF and DC ground connection.
Summary of the invention
In an aspect, integrated circuit (IC) device of encapsulation, comprising: radiator；With on the radiator based on
The heat-radiating substrate of diamond, wherein the heat-radiating substrate based on diamond has the through-hole array passed through.The IC of encapsulation
Device also comprises integrated circuit (IC) chip being located on the heat-radiating substrate based on diamond, wherein the IC chip
Edge is Chong Die at least one of the through-hole.
In another aspect, a method of assembling integrated circuit (IC) chip is based on Buddha's warrior attendant this method comprises: providing
The heat-radiating substrate of stone, with conductive surface and the through-hole array passed through.This method, which is also comprised, is attached to base for IC chip
In diamond heat-radiating substrate heat to be scattered from it, wherein attachment include at least one of positioning through hole with IC chip
Imbricate.
In another aspect, integrated circuit (IC) device of encapsulation has and wears including the heat-radiating substrate based on diamond
Cross through-hole array therein.The IC device of encapsulation also comprises the monolithic integrated microwave circuit on the heat-radiating substrate based on diamond
(MMIC) chip, the mmic chip are configured as output more than about 3W/mm parts of peak power densities, wherein the mmic chip
Edge it is Chong Die at least one through-hole, and wherein the heat-radiating substrate based on diamond is configured as the MMIC core
The heat diffusion that piece generates is far from the mmic chip.
Detailed description of the invention
Fig. 1 shows the IC device of encapsulation according to the embodiment comprising heat-radiating substrate, the substrate are attached on side
IC device and it is attached with radiator on another side.
Fig. 2A shows the perspective view of the heat-radiating substrate according to the embodiment based on diamond, which passes through its shape
At there is through-hole array.
Fig. 2 B shows the plan view of heat-radiating substrate shown in Fig. 2A.
Fig. 2 C shows the cross-sectional side view of heat-radiating substrate shown in Fig. 2A and 2B.
Fig. 3 A shows the perspective view of the IC device of encapsulation according to the embodiment, which includes being similar to Fig. 2A -2C
Shown in heat-radiating substrate, and be attached to IC chip thereon.
Fig. 3 B shows the sectional view of the IC device of encapsulation according to the embodiment, which includes being similar to Fig. 2A -2C
Shown in radiate, and be attached to monolithic microwave IC (MMIC) chip thereon.
Fig. 4 A shows the plan view of the IC device of encapsulation according to the embodiment, which includes being similar to Fig. 2A -2C
Shown in heat-radiating substrate, with IC chip and be attached to radiator thereon.
Fig. 4 B shows the viewgraph of cross-section of the IC device of the encapsulation of Fig. 4 A.
Fig. 5 shows the experiment triaxiality contour map between traditional heat-dissipating substrate and heat-radiating substrate according to the embodiment
Comparison.
Fig. 6 shows the device architecture in mmic chip, for obtaining the heat compared and electric result.
Fig. 7 shows the experimental temperature of the channel of high electron mobility transistor (HEMT) device under the conditions of pulse power
The curve graph of trace is derived from the device architecture of the device architecture similar to Fig. 6, and wherein mmic chip has HEMT device, attached
On different heat-radiating substrates.
Fig. 8 shows the power added efficiency (PAE) obtained from the device architecture of the device architecture similar to Fig. 6 and frequency
Comparison curve graph, wherein being connected on different heat-radiating substrates with the mmic chip of HEMT device.
Specific embodiment
The various descriptions described in detail below for presenting specific embodiment of some embodiments.However, wound described herein
It can newly realize in a number of different manners, for example, as defined and covered by the claims.In the present specification, reference is attached
Figure, wherein identical appended drawing reference can indicate identical or intimate element.It should be appreciated that element shown in figure is not necessarily
It is drawn to scale.In addition, it should be understood that some embodiments may include elements more more than element shown in figure and/or figure
Shown in element subset.In addition, some embodiments can be in conjunction with any conjunction of the feature from two or more attached drawings
Suitable combination.
With active and passive semiconductor integrated circuit (IC) device (including silicon and compound semiconductor IC device) function
The increase of rate and current densities, the heat management during operation have become challenge.Partially due to certain advantageous features on silicon,
Compound semiconductor becomes to become more and more popular in various applications.For example, some compound semiconductors, such as broad-band gap (WBG)
Semiconductor, provides the advantageous feature for being better than silicon in all fields, including higher breakdown voltage, higher thermal conductivity, higher
Temperature operability and low switching losses and other advantages.Due to these and other, various WBG semiconductors exist
It is commercially used or has been proposed for the commercial use of monolithic integrated microwave circuit (MMIC) device.In particular, in high frequency
(VHF), the demand in hyperfrequency (UHF) and microwave frequency band to high-power demand driving to MMIC device, the device can be
Tens of to hundreds of watts of power is provided under RF frequency to 10GHz and higher frequency.These devices can use WBG semiconductors manufacture,
Including GaAs, 6H-SiC, 4H SiC, GaN and diamond etc..Particularly, due to the various advantageous material properties of GaN, including
Broad-band gap and high-breakdown-voltage, are used for high pressure, high frequency and/or high power applications, and high-power pulsed ion beams use more and more
Power transistor based on gallium nitride (GaN).
Although WBG semiconductor has the advantageous feature for high power or microwave applications, implement for effectively business
Effective heat management can challenge on various integrated horizontals.For example, the power transistor based on WBG semiconductor sometimes by
Significant self-heating effect, this may limit achievable power density and/or efficiency.In addition to being caused by the reduction of such as mobility
Reduced performance except, the high pass channel temp as caused by self-heating can accelerate device failure rate and possibly even cause to destroy
Property is burnt out.The thermal management algorithm for solving these challenges includes chip-scale and package level solution.In addition to heat management, for height
The package level solution of pressure, high frequency and high power applications should also provide direct current (DC) and RF and the effective of mechanical integrity connects
Ground.Therefore, it is necessary to a kind of heat management solution for IC device, for solve the high pressures of these challenge from competition, high frequency and
High power applications.
In order to alleviate various problems, the various embodiments of the IC device of encapsulation disclosed herein include heat-radiating substrate or heat dissipation
Device.Referring to Fig.1, the IC device 100 of encapsulation includes radiator 104, and radiator 104 is heat-radiating substrate, and one side is attached by chip
Connect the base portion that layer 110 is attached to IC chip 108.Radiator 104 is attached to radiator in the other side by carrier attachment layer 106
112.The heat that radiator 104 is configured as to be generated by the IC chip 108 with the area smaller than radiator 104 is (by arrow
Instruction) radiator 112 is spread to, the area of radiator 112 is greater than the area of radiator 104.In order to be used as effective radiator,
It can enhance and/or optimize the different aspect of radiator, including thermal coefficient (TC), thermal expansion according to embodiment disclosed herein
Adhesion characteristic between coefficient (CTE) and chip component and adhesive layer.In the following, it is described that radiator including diamond
104 various embodiments, which solve these and other purposes.
In order to solve the various demands of the above-mentioned demand for grounding including thermal management requirements and high-power pulsed ion beams, retouch herein
The various embodiments stated include the radiator for including diamond, which is configured to attach to integrated circuit (IC) device.
The perspective view, plan view and viewgraph of cross-section of radiator 104 is shown in detail in Fig. 2A -2C respectively.Radiator 104 includes diamond
And it is configured to attach to IC tube core 108, as shown in Figure 1, and forming through-hole 116 or perforation array by it.Various
In embodiment, perforation is configured to when being attached to the edge of IC chip 108 and the imbricate of IC chip 108, and has
Outer surface 104S coated with conductive layer, as being described in detail about Fig. 3.According to embodiment, outer surface 104S is coated with conduction
The coating of layer may include one in one or more of top surface, bottom surface and side surface and through-hole array 116 or
Multiple inner surfaces.
In the embodiment described in which, through-hole array 116 includes even number through-hole 116, forms multiple rows of through-hole 116 along edge
Length direction extends across the line arrangement of distance l, for example, as shown in Figure 2 B.Through-hole array 116 also forms multiple row through-hole 116,
The through-hole 116 is arranged along the line extended in the width direction across distance w.The location arrangements of through-hole 116 are to lead to
One or two of the outermost skidding in hole 116 and/or one or two of outermost column are in IC chip (108 in Fig. 1)
One or more edges overlapping.In some embodiments, at least the outermost skidding of through-hole 116 is arranged around axial symmetry,
It is between the outermost skidding of through-hole 116 and extends in the longitudinal direction, outermost skidding of each of the axis and through-hole 116 etc.
Away from.Alternatively or additionally, for at least outermost column of through-hole 116 about axial symmetry, which arranges it in the outermost of through-hole 116
Between and extend in the direction of the width, each outermost column of the width direction and the through-hole 116 are equidistant.It is right due to symmetry
Each of through-hole 116 in column or row, there are a corresponding through-holes 116 in the column or row being arranged symmetrically.To,
The symmetrical corresponding row and/or column of through-hole 116 can have the through-hole of identical quantity, and wherein through-hole has essentially identical ruler
It is very little so that when IC chip 108 is attached to radiator 104, the stress of application by the radiator 104 in IC chip 108 symmetrically
Reduce.For example, opposite edge symmetrically corresponds to the corresponding row of through-hole 116 when IC chip 108 is attached to radiator 104
Or column pair, cause between the rigidity of radiator 104 and IC chip 108 and radiator 104 in the stress of the first and second edges
Reduction be about symmetrical axisymmetric as described above.
In the embodiment described in which, through-hole 116 is arranged in two rows, and there are three through-hole 116 and three columns, Mei Getong for every row's tool
There are two through-holes for hole tool.However, embodiment is without being limited thereto, and through-hole 116 can be arranged to any appropriate number of row and appoint
The column for quantity of anticipating, for example, between 2 and 10, according to embodiment, wherein each row and column can have it is any appropriate number of logical
Hole 116, for example, between 2 and 10.
According to various embodiments, most of material by including diamond of radiator 104 is formed.Since it is preferably led
Hot, diamond provides various interesting advantages for the heat management of IC device.It is responsible for the metal of high-termal conductivity with conduction electronics
On the contrary, heat is conducted in electrical insulator by lattice vibration.The velocity of sound of diamond is about per second 17,500 meters (m/s), is had non-
Often high Debye temperature (2220 Kelvins (K)) more than the order of magnitude of other most of insulating materials, and causes non-at room temperature
Often high thermal conductivity (2000-2500 watts/meter of Kelvin (W/mK)), more than five times of conductivity of copper.
Although it can be relatively poor electric conductor with ideal hot property, diamond, so that when being used as IC
When the radiator of device, bulk diamond itself may be it is inappropriate, it is conductive which is also arranged as offer, such as makees
For a part and/or RF grounding path of DC.In addition, diamond also has one of highest rigidity value, and when being connected to IC chip, heat
Mismatching for the coefficient of expansion (CTE) may bonding circle to IC chip and/or IC chip between the substrate based on diamond
Face causes stress.Therefore, various embodiments described herein is advantageously combined material and physical Design to provide and be used for IC chip
Radiator, such as mmic chip, with excellent heat dissipation and electrically grounded ability, and compatible with the excellent mechanical of IC chip
Property.
Although single-crystal diamond may be prohibitively expensive, polycrystal synthesis diamond can be used for reducing the cost of radiator 104.
Although being lower than single-crystal diamond, polycrystalline diamond can still have the highest thermal conductivity of any non-diamond materials.Therefore, according to
Some embodiments, radiator 104 include polycrystal synthesis diamond.This polycrystalline diamond can pass through chemical vapor deposition
(CVD) it is formed.Polycrystalline diamond can be formed, for example, in the reaction substance environment with relatively high hydrogen-carbon ratio, for example,
About 0.1 to 10% methane (CH4) in hydrogen (H2), such as the 1%CH4 in H2, in temperature for example, 700 DEG C and 1000 DEG C
Between, gas pressure range is 30-300 support.Deposition technique may include such as plasma assisted CVD and use heated filament or filament
Hot assisted CVD.According to various embodiments, by controlling reaction condition, the thermal conductivity of radiator 104 is controlled as having big
In 1000W/mK, greater than 1200W/mK, greater than 1400W/mK, greater than 1600W/mK, greater than 1800W/mK, greater than 2000W/mK's
Value or value in the range of being defined by any one of these values, for example, 1200 to 2000W/mK.
It is conductive in order to be provided between IC chip 108 and radiator 112, for example, in order to provide electrical ground, in various implementations
In example, the outer surface 104S of radiator 104 is coated with one or more conductive layers, for example, metal layer.According to embodiment, coating
Outer surface 104S includes the surface of through-hole 116.In one embodiment, conductive metal layer includes Ti/Pt/Au lamination, wherein Ti
There is the about thickness of 50nm, 100nm, 200nm, 300nm or by the definition of any one of these values with each of Pt layers
In the range of thickness, Au has the thickness of about 500nm, 1000nm, 1500nm, 2000nm, 2500nm, 3000nm, Huo Zheyou
The thickness in the range of any value restriction in these values.Advantageously, Ti/Pt/Au lamination is using chip adhesive layer (in Fig. 1
110), for example, Au/Ge eutectic, Au/Si eutectic or Au/Sn solder etc., can be compatible with radiator 104 being attached to IC chip
108.In addition, Ti/Pt/Au can bear the subsequent technique temperature more than 450 DEG C.However, embodiment is without being limited thereto, and at other
In embodiment, the outer surface 104S of coating can be coated with any stacking, such as TiW/Au, TiW/Ni/Au, TiW/Cu/Ni/
Au, TiW/Au/Cu/Ni/Au, Ti/Au, TaN/TiW/Au and TaN/Ti/Ni/Au are named a few, depending on required heat
And electrical property.
In some other embodiments, most of composite material by including diamond of radiator 104 is formed, the Buddha's warrior attendant
Stone can have relatively high thermal conductivity and electric conductivity.In some embodiments, radiator 104 includes metal matrix composite
(MMC) comprising diamond crystals and the intergranular matrix comprising suitable metal (such as Al, Ag or Cu).MMC material can pass through
Certain metal or metal alloy (Ag, Al, Cu or their alloy) are penetrated into the mold containing diamond particles and are manufactured.
For example, diamond particles can be filled to the fusion temperature for being heated above metal or alloy in a mold and in a vacuum furnace
Temperature.Then, high pressure can be applied penetrating into metal in the mold including diamond particles, using formed have metal as
The composite material of matrix.In some embodiments, substrate includes metal matrix diamond composite, and it includes metal matrixs
In diamond particles.In some embodiments, the metal of metal matrix includes or aluminium.
According to embodiment, by using the MMC with the diamond volume fraction more than about 30%, 50% or 70% or by
The range that any one of these percentages limit forms the major part of radiator 104, can control the effective of radiator 104
Thermal conductivity has and is higher than 200W/mK, is higher than 400W/mK, is higher than 600W/mK, is higher than 800W/mK, higher than 1000W/mK's
Value, or with the value in the range defined by any of these values.Advantageously, by selecting the metal of MMC and the volume of diamond
Score etc. can control thermal conductivity for higher than such as CuW (about 200W/mK), CuMo (about 250W/mK) and Cu/Mo/Cu
(350W/mK).Advantageously, when being formed by wrapping diamantiferous MMC, the surface of radiator 104 can be by the metal shape of MMC
At, and volume is formed by MMC.That is, radiator 104 may include being covered with " epidermis " formed by the metal of MMC
Blocky MMC, to provide electric conductivity.However, embodiment is without being limited thereto, and in other embodiments, the heat dissipation formed by MMC
Device 104 can be further coated with conductive metal layer or stacking, for example, the Ti/Pt/Au in various other metal stacks is stacked,
As described above.
A-2C still referring to Figure 2, radiator 104 can have various physical sizes, these physical sizes be based on it is various because
Element arrangement, including factor the considerations of electricity, heat and mechanical aspects.Other than other Considerations, various factors, which may depend on, to be wanted
It is attached to IC chip thereon, heat, operation temperature, CTE mismatch and the desired rigidity generated by IC chip.
In various embodiments described herein, radiator 104 can have about 0.10 ", 0.05 ", 0.02 ",
0.01 ", 0.005 ", 0.002 ", 0.001 " thickness (t in Fig. 2 C), or in the range of being limited by any value in these values
Any value.
In various embodiments described herein, radiator 104 can have about 0.05 ", 0.10 ", 0.20 ", 0.50 "
Length (L in Fig. 2 B), or any value in the range of being defined by any of these values, for example, about 0.27 ".
In various embodiments described herein, radiator 104 can have about 0.05 ", 0.10 ", 0.20 ", 0.50 "
Width (W in Fig. 2 B), or any value limited by any value in these values, for example, about 0.16 ".
In various embodiments described herein, the distance between the outermost of through-hole 116 column (l in Fig. 2 B) can be with
Any value in the range of being about 0.05 ", 0.10 ", 0.20 ", 0.50 " or being defined by any of these values, for example, about 0.13 ".
In various embodiments described herein, the distance between outermost column of through-hole 116 (w in Fig. 2 B) be can be
About 0.05 ", 0.10 ", 0.20 ", 0.50 " or any value in the range of being defined by any of these values, for example, about 0.08 ".
In various embodiments described herein, the diameter of through-hole 116 can be about 0.10 ", 0.05 ", 0.02 ",
0.01 ", 0.005 ", 0.002 ", 0.001 " or any by the value in the range of any definition.
In some embodiments, the through-hole 116 is hollow.However, embodiment is without being limited thereto, and in other realities
It applies in example, through-hole 116 can be filled or be partially filled with suitable material, to provide the further control to mechanical and thermal property
System.For example, any conductive layer of the above-mentioned outer surface 104S about coating can be filled or be filled partially with to through-hole 116.
Fig. 3 A and 3B respectively illustrate the perspective view and sectional view of IC the device 300A and 300B of encapsulation according to the embodiment,
It includes radiator 104 and is attached to IC chip 108 thereon, such as mmic chip.Although not showing in figures 3 a and 3b,
It is that IC chip 108 and radiator 104 can be attached by chip attachment layer (110 in Fig. 1), for example, Au/Ge eutectic, Au/Si
Eutectic or Au/Sn solder.The IC device 300A/300B of encapsulation includes diamantiferous radiator 104, can be similar to upper
Face refers to the radiator 104 of Fig. 2A -2C description.Radiator 104 is attached with integrated circuit (IC) chip 108 in side.Although not
It shows in figures 3 a and 3b, but integrated IC device 300A/300B can be also comprised and is attached on the other side of radiator 104
Radiator (112 in Fig. 1), be similar to Fig. 1 shown in radiator.Similar to above for described in Fig. 2A -2C, dissipate
The main body of hot device 104 can be based on diamond, for example, by polycrystalline diamond or the MMC including diamond is formed, and dissipate
The surface of hot device 104 may include conductive layer.
Referring to the packaging 300A of Fig. 3 A, according to embodiment, through-hole array 116a, 116b have quantity, size and position
It sets, so that they reduce the rigidity of radiator 104, to reduce the stress between IC chip 108 and radiator 104.In addition, through-hole
116a, 116b can be provided for IC chip 108 and be directly grounded path, such as DC grounding path.
When the embodiment configuration radiator 104 shown in the A-2C according to fig. 2, the through-hole 116a and 116b of Fig. 3 A indicates through-hole
Those of 116 column jacket is separated by the distance l in Fig. 2 B, and in the presence of the middle column of through-hole 116, it can be from view
It hides (that is, being covered by IC chip 108).However, embodiment is without being limited thereto, and can be omitted from the radiator 104 of Fig. 3 A logical
The middle column in hole.
As described in above for Fig. 2A -2C, through-hole 116a, 116b are located in and to be attached to IC chip 108 thereon
At the corresponding position in edge.In the embodiment as shown in fig. 3 a, through-hole 116a, 116b be located so that each through-hole 116a,
A part of the cross section of 116b is covered by IC chip 108, and rest part remains not covered.For example, in the reality
It applying in scheme, through-hole 116a, 116b cover the approximately half of cross section of each through-hole 116a, 116b, and through-hole 116a,
The remaining half cross section of 116b remains not covered.However, embodiment is without being limited thereto, and in other embodiments,
Through-hole 116a, 116b cover any suitable score cross-sectional area of each of through-hole 116a, 116b, for example, 5%,
20%, 40%, 60%, 80%, 95% or by any one of these values definition in the range of score.
Referring still to Fig. 3 A, through-hole array 116a, 116b include even number through-hole, including one arranges the first through-hole 116a,
It is positioned to Chong Die with the first edge of IC chip 108, one arranges the 2nd through-hole 116b, is positioned to the second side with IC chip 108
Edge overlapping, wherein the first edge of IC chip 108 and second edge are laterally opposite.In the embodiment described in which, first is logical
The row of the row of hole 116a and the second through-hole 116b are symmetrically that the axis is at the first and second edges of IC chip 108 about axis
Each of between and it is equidistant or between every row of first through hole 116a and every row of the second through-hole 116b it is equidistant.Also
It is to say, for each of first through hole 116a, there are corresponding one in symmetrically positioned second through-hole 116b.Described
In embodiment, the row via count having the same of the row of first through hole 116a and the second through-hole 116b.In addition, first through hole
Respective through hole 116a and 116b in 116a and the second through-hole 116b are respectively provided with essentially identical size and are symmetrically positioned
At, the rigidity reduction of such radiator 104 Chong Die with IC chip 108 in the first and second laterally opposite edges, and/
Or the stress between IC chip 108 and the radiator 104 of the first and second edges reduces, the first He about IC chip 108
Equidistant axial symmetry between second edge.It was found by the inventors that the symmetry of through-hole 116a and 116b can inhibit radiator
104 warpage.
In the embodiment described in which, the row of through-hole 116a, 116b is oriented in a pair of of opposite edges with IC chip 108
A pair of of overlapping, and another pair opposite edges of IC chip 108 are not Chong Die with through-hole 116a, 116b.On the contrary, IC chip 108
Another pair opposite edges are aligned with the respective edges of radiator 104.However, embodiment is without being limited thereto, and in other embodiments, IC
Another pair of the opposite edges centering of chip 108 can also be Chong Die with the row of through-hole.
Through-hole can be used suitable technique and be formed, including laser and/or water jet technique.
In other function, through-hole 116,116b solve each side of the heat management problems encountered in integrated IC chip
Face, it may for example comprise using the IC chip for the device that WBG semiconductor is formed, as described above.For IC chip 108 and radiator 104
Between given thermal expansion coefficient (CTE) mismatch, various heat management problems can be associated with the effective rigidity of radiator 108.
When the rigidity of radiator 104 is lower, radiator 108 is adapted to the stress as caused by CTE mismatch, to reduce IC chip
Caused total stress on 108.Effective rigidity depends on the thickness of radiator 104 again.When the thickness of radiator 104 is too thin, subtract
The thickness of small radiator 104 can lead to rigidity reduction, under the conditions of high-temperature operation, between IC chip 108 and radiator 104
CTE mismatches the warpage or bending that may cause radiator 104, this will lead to the crack or its various interface of various parts again
Layering.It was found by the inventors that the space layout of through-hole 116a, 116b combine a variety of materials as described herein design that can have
Effect ground reduces the rigidity of radiator 104.
The various arrangements of through-hole 116a, 116b can be optimized including their size based on various factors.For example,
The quantity of through-hole and the diameter of through-hole determine the volume relative to the substrate removal formed by the identical material of not through-hole.Hair
Bright people has been found that the material by removing given volume in this way, the rigidity of adjustable substrate with realize substrate and
The suitable or acceptable mismatch of strain between IC chip 108.According to various embodiments, relative to not forming through-hole
Substrate, the volume that the diameter and quantity of through-hole remove through-hole can be more than about 3% more than about 1%, be more than about 5%, be more than about
10%, it is more than about 15%, more than about 20% or with percentage in the range of being defined by any two in these values.?
Under some configurations, for the stiffness reduction amount of radiator 104, reduced by the volume that these percentages remove corresponding to thickness
About the same amount.
Referring still to Fig. 3 A, in some embodiments, radiator 104 has at least the first main surface, the first main table
Face is configured as the IC chip 108 that contact has relative smooth surface, this can be by being polished after depositing conductive layer
It realizes, as above for example, described in chemical vapor deposition.For example, the first main surface of radiator 108 can have less than 5 × 10-3、
Less than 1 × 10-3, less than 5 × 10-4, less than 1 × 10-4Or the value in the range defined by any two in these values is square
Root (RMS) surface roughness.In some embodiments, in some embodiments, radiator 104 is opposite with the first main surface
The second main surface (its can be configured as contact radiator) can also be polished with similar smooth surface.However,
In other embodiments, it is convenient to omit polishing, so that the second main surface has the surface of relative coarseness, greater than the first main surface
Roughness value can be the surface roughness obtained by the conductive layer that chemical vapor deposition is grown.
According to embodiment, IC chip 108 (for example, mmic chip) may include be configured as operating under RF frequency it is each
Kind device.As an example, Fig. 3 B shows the sectional view of the IC device 300B of encapsulation, the IC device 300B include be similar to about
The radiator 104 arranged shown in Fig. 2A -2C, and attachment High-Power Microwave IC chip 108 example.For example, using chip
Adhesive layer 110.Fig. 3 B shows the detailed view of the IC device in IC chip 108.IC device shown in IC chip 108 includes base
In the power microwave device of GaN comprising high electron mobility transistor (HEMT) device, such as AlGaN/GaN HEMT device
Part is used for High-Power Microwave application.
HEMT device shown in IC chip 108 includes semiconductor substrate 304, such as silicon carbide (SiC) substrate, such as half
Insulate 4H SiC substrate, grows nucleating layer 308, such as AlN nucleation on it.GaN layer 312 is formed on nucleating layer 308, such as
The insulation GaN of Fe doping, followed by middle layer 316, for example, AlN middle layer and AlGaN cap rock 320, for example, undoped
AlGaN cap rock.Multiple contacts, including source contact 324S, gate contact 324G and drain contact are formed in AlGaN layer 320
324D.GaN layer 312 can be configured as formation two-dimensional electron gas (2DEG) wherein, and AlGaN layer 320 can be with grid
It contacts 324G and forms schottky junction.
In some embodiments, HEMT device can be depletion type HEMT, and wherein 2D electron gas can be formed in GaN layer
Without being biased to grid in 312.This transistor is referred to as " normally opened ", and will when gate contact 324B is negatively biased
It closes.In other embodiments, by sufficiently adulterating AlGaN cap layers 320 with acceptor, HEMT can be configured as " often closing " device
Part.Shown transistor can be in the operation at frequencies for being up to about 20GHz or even as high as about 200GHz.
Although the exemplary IC chip 108 in illustrated embodiment includes the HEMT device based on GaN as explanation, embodiment
It is without being limited thereto, and IC chip 108 can be various other devices.For example, IC chip 108 may include various other crystal
Pipe, including bipolar junction transistor (BJT), emos (MOSFET), hetero-junctions
The MOS (LDMOS) of bipolar transistor (HBT), metal semiconductor FET (MESFET) and horizontal proliferation, names a few,
It can be formed based on such as GaAs or GaN.These transistors are generated using these combinations of materials at the amplification and power of customization
Reason ability.
It should be appreciated that the general MMIC device based on GaN could generally have higher compared with the device based on GaAs
Power generation and heat-sinking capability.For example, although the peak power density of some MMIC devices based on GaAs is likely less than 5W/mm, small
MMIC device in 4W/mm or even less than 3W/mm, but based on GaN can have peak power density more than about 3W/mm, be more than
About 4W/mm, it is more than about 13W/mm more than about 5W/mm, more than about 7W/mm, more than about 9W/mm, more than about 11W/mm, or by these
Power density in the range of the definition of any one of value.
Referring still to Fig. 3 B, with the similar fashion that is described above with reference to Fig. 3 A, IC chip 108 passes through chip attachment layer
110 (for example, AuSn layers) are attached to radiator 104, and position relative to through-hole array, and column are so that one of IC chip 108
Or multiple edges are Chong Die with one or more through-holes 116 that radiator 104 is formed are passed through, and IC chip 108 is generated
Heat is effectively spread by radiator 104.As described above, the mechanical advantage that through-hole 116 provides, radiator 104 also pass through to be formed
Conductive layer on the surface of radiator 104 is that IC chip 108 provides DC and RF grounding path, including in such as through-hole 116
Portion surface.
Fig. 4 A and 4B show the plan view and sectional view of the IC device 400 according to the encapsulation of some other embodiments.Envelope
The IC device 400 of dress includes IC chip 108, for example, mmic chip, is attached to radiator 104, radiator 104 is connected to scattered
Hot device 512.Shown in configuration be sometimes referred to as " on piece chip " configuration, the configuration phase of radiator is directly connected to IC chip
Than various business and/or technical advantage can be provided.Advantage includes that can accommodate relatively large IC chip, is had excellent
Heat-sinking capability and can re-workability, name just a few.As described above, radiator 104 includes through-hole array and is coated with conductive metal layer.
Through-hole is located so that one or more imbricates of they and IC chip 108, as described above, it reduces its rigidity and provides
DC grounding path.IC chip 108 and radiator 104, which are similar to, those of to be described above, and wherein radiator 104 is configured as spreading
The heat generated by IC chip 108 has the area smaller than radiator 104, before diffusing into radiator 512, face
Long-pending and thermal mass is significantly greater than radiator 104.In addition, as described above, the volume and through-hole of the material by optimization through-hole removal
Position, the rigidity of heat-radiating substrate can be optimized, for use as resist CTE related stress buffer, otherwise in no radiator
The stress can be bigger in the case where 104.
Referring to Fig. 4 A, the IC device 400 of encapsulation also comprises multiple input pins 524 comprising Vg, GND, NC and
RFin, for DC and RF signal to be input to 520 pin of IC chip 108 and multiple output pins, including Vdd, GND,
RFout, for exporting DC and RF signal from IC chip 108.Though it is shown that pin, but can alternately or in addition realize
Any suitable contact and/or pad.Radiator 512 has been formed on a plurality of planar transmission line 516, such as 50 ohm of biography
Defeated line, for RF signal to be coupled to IC chip 108 and from 108 coupling RF signals of IC chip.IC chip 108 and radiator 104
It is electrically connected by multiple conducting wires (for example, Au conducting wire), and IC chip 108 and planar transmission line 516 pass through a plurality of conducting wire (example
Such as, Au conducting wire) electrical connection.
Fig. 4 B shows the cross-sectional view for example by the line AA' interception in Fig. 4 A.Fig. 4 B, which is schematically shown, to be come from
The heat dissipation path 532 of heat source, such as semiconductor-semiconductor knot or semiconductor-metal knot.In addition, Fig. 4 B is schematically shown
Lateral RF grounding path 536, path include the outer conducting layer of radiator 104.
Fig. 5 show experiment triaxiality contour map 502 between traditional heat sinks and radiator according to the embodiment,
508 comparison.According to embodiment, upper stress contour map 502 is shown with the public heat dissipation for being attached to traditional heat sinks 504
Device 512 and radiator 104 based on diamond, the through-hole array which has conductive surface and pass through.Heat dissipation
Device 504,104 has identical IC chip 108 connected to it.Radiator 504,104 is attached using identical epoxy resin, tool
There is identical size and arrange identical, is passed through in addition to radiator 504 is formed without through-hole by CuW, and radiator 104
It configures in a similar way as described above.The stress measured at the respective edges position on radiator 504,104 at 150 DEG C
(wherein stress part is higher) shows the stress value of 41.5 megapascal (MPa) and 38.7MPa respectively.Lower stress contour map 508
The common heat sink 512 according to the embodiment for having and being attached to traditional heat sinks 504 and radiator 104 is similarly illustrated,
Middle radiator 504,104 has the identical IC chip 108 being attached to thereon.Component in Imitating stress contour map 508
It is arranged in a manner of identical with the respective components in upper simulation stress contour map 502, in addition in lower stress contour map 508
Radiator 504,504 uses different from the epoxy resin for radiator 504,104 to be attached in upper stress contour map 502
Epoxy resin attachment.Respective edges position similar with top contour map 502, at 150 DEG C on radiator 504,104
Locate the stress of measurement, wherein stress part is higher, and stress value is respectively 42.0MPa and 39.7MPa.Test stress contour map
502,508 show by using radiator 104 according to the embodiment, can significant reduction stress.
Fig. 6-8 shows device architecture and comparison result according to the embodiment, and it illustrates include dissipating based on diamond
The heat and electrical dominance of the integrated IC device of hot device.Fig. 6 shows the device architecture 600 in mmic chip, is used to obtain following
The various comparison results of description.Device architecture 600 includes similar to the 0.25 μm of design rule HEMT described above with reference to Fig. 3 B
The model of device.HEMT device includes stacking GaN layer 312, AlN middle layer 316 and the AlGaN being formed on 4HSiC substrate lid
Layer 320.Source contact 324S, gate contact 324G and drain contact 324D are formed in AlGaN layer 320.As described above, GaN
Layer can be configured to form two-dimensional electron gas (2DEG) wherein.Tables 1 and 2 is shown to be based on according to the embodiment be attached to
The lower acquisition of continuous wave (CW) operation of HEMT device in the mmic chip of the radiator of CuW and the radiator based on diamond
The comparison result of heat distribution.
Table 1. simulates the measurement of temperature during v. is operated: the HEMTMMIC on CuW radiator
Table 2. simulates the measurement of temperature during v. is operated: on the radiator based on diamond with through-hole array
HEMTMMIC
Table 1 is shown for (the figure of device architecture 600 in the mmic chip including 0.25 μm of design rule HEMT device
6), be similar to above for device described in Fig. 3 B, channel temperature, basal temperature and the channel of simulation and experiment measurement with
The contrast table of the temperature difference (Δ T) of (MMIC is connected to CuW radiator herein) between pedestal.Table 2 is shown according to embodiment pair
Device architecture 600 (Fig. 6) in the mmic chip for including 0.25 μm of design rule HEMT device is similar to above for figure
Device described in 3B, the channel temperature of simulation and experiment measurement, (MMIC is attached herein between basal temperature and channel and pedestal
Be connected to the radiator based on diamond of through-hole array passed through) the temperature difference (Δ T) contrast table.In Tables 1 and 2
Result between comparison show it is according to the embodiment with the through-hole array passed through by the way that mmic chip to be attached to
Radiator, the temperature difference (Δ T) between channel and base portion can reduce by 30 DEG C -35 DEG C.According to the various embodiments of this paper, substrate
Difference between basal temperature and the channel temperature of HEMT remain less than about 110 DEG C, less than about 100 DEG C, less than about 90 DEG C, be less than
About 80 DEG C or by any one of these values definition in the range of temperature.
Fig. 7 shows the experimental temperature curve of the channel of HEMT device under pulse (10ms) power condition.Measurement corresponds to
In the measurement carried out on device architecture, which is similar to device architecture 600 (Fig. 6), wherein with HEMT device
Mmic chip is connected to different radiating elements.Temperature trace 704,708 and 712 correspond to from it is according to the embodiment be attached to by
Those of the mmic chip of radiator of CuW, diamond-aluminium MMC and the diamond formation with the through-hole array passed through.
Temperature trace 712 shows up to about 20 degree of minimum peak temperature relative to temperature trace 704.
Fig. 8 shows curve graph 800, and it illustrates power added efficiencies (PAE) compared with frequency, is to be similar to
The quality factor of RF power amplifier are used in the industry measured on the device architecture of device architecture 600 (Fig. 6), wherein having
The mmic chip of HEMT device is connected on different radiators.Consider that the PAE of the input power (Pin) of driving amplifier is RF
Power output (Pout) subtracts the ratio between input power (Pin) and total DC power (PDC) of consumption, is expressed as percentage, indicates are as follows:
PAE=100 (Pout–Pin)/PDC.PAE curve 804,808, which corresponds to, to be attached to by the mmic chip of the CuW radiator formed,
PAE curve 812,816, which corresponds to, is attached to the radiator based on diamond (according to embodiment with the through-hole battle array passed through
Column) mmic chip, PAE curve 820,824 correspond to is connected to by the mmic chip of diamond-aluminium MMC radiator formed.
PAE curve shows that mmic chip is attached to the dissipating based on diamond with the through-hole array passed through according to embodiment
The peak efficiency of hot device, at least partially due to the lower junction temperature being achieved in, as described above.This phase is also shown in table 3
Guan Xing shows various performance indicators, improves including gain improving, output power and using by having the through-hole battle array passed through
The PAE that the radiator that the diamond of column is formed is observed improves, and can be at least partially attributed to lower operation temperature.
3. performance parameter of table compares abstract: CuW, diamond-aluminium MMC and the heat dissipation based on diamond with through-hole array
HEMTMMIC on device
All aspects of this disclosure can be realized in various electronic devices.The example of electronic device can include but is not limited to
Consumption electronic product, the component of consumption electronic product, electronic test equipment, the cellular communication infrastructure etc. of base station.Electricity
The example of sub- device may include, but be not limited to, and the mobile phone of such as smart phone, such as smartwatch or earphone are worn
It wears and calculates equipment, phone, TV, computer monitor, computer, modem, handheld computer, laptop, puts down
Plate computer, personal digital assistant (PDA), micro-wave oven, refrigerator, automobile electronic system, such as automobile electronic system, three-dimensional sonic system
System, DVD player, CD Player, the digital music player of such as MP3 player, radio, field camera, such as
Camera, pocket memory chip, washing machine, dryer, washer/dryer, peripheral equipment, clock of digital camera etc..
In addition, electronic equipment may include unfinished product.All aspects of this disclosure can be particularly in various wireless telecommunication technologies
Realize, wherein expectation high power, high frequency band, improvement the linearity and/or improved efficiency, including military and space application is all
Such as radar, community antenna television (CATV), radar jammer and aerogram base station, name just a few.
Unless the context clearly requires otherwise, otherwise in entire disclosure and claims, word "include", "comprise",
" containing ", " having " etc. should be explained in a manner of containing, rather than exclusiveness or the meaning of exhaustion；That is, in " packet
Include but be not limited to " in the sense that.If herein it is commonly used, " coupling " word " being directly connected to " refer to can be directly connected to or
Two or more elements connected by one or more intermediary elements.Similarly, as herein commonly used, " connection "
One word refers to two or more elements that can be directly connected to or connect by one or more intermediary elements.In addition, working as
In this application in use, word " herein ", " top ", " lower section " and similar meaning word should refer to the entirety of the application
Rather than any specific part of the application.Under where the context permits, the above-mentioned specific implementation of singular or plural is used
Word in mode can also respectively include plural number or odd number.Word "or" refers to the list of two or more projects, the list
Word covers all explained below of the word: any project in list, any in all items and list in list
The combination of project.
In addition, unless expressly stated otherwise, or otherwise understand in used context, otherwise makes herein
Conditional statement, for example, " can with ", " possibility ", " such as ", " " etc., being typically aimed at expression some embodiments includes, and
Other embodiments do not include certain features, element and/or state.Therefore, this conditional statement be generally not intended to imply one or
Multiple embodiments characteristics of needs, element and/or state in any way, or whether include these features, element and/or state
Or these features, element and/or state are executed in any specific embodiment.
Although some embodiments have been described, but these embodiments are only used as example to present, and are not intended to be limited to
The scope of the present disclosure.In fact, novel device described herein, method and system can be embodied in the form of various other；In addition,
Without departing from the spirit of the present disclosure, various omissions can be carried out to the form of method and system described herein, replaced
It changes and changes.Although alternate embodiment can be executed with different components and/or electricity for example, block is presented with given arrangement
The similar functions of road topology, and can delete, move, add, segment, combine and/or modify some pieces.It is every in these blocks
One can be implemented in various different ways.The element of above-mentioned various embodiments and any appropriate combination of movement can be combined
To provide further embodiment.Above-mentioned various features and process can realize independently of one another, or can be in various ways
Combination.The all possible combinations and sub-portfolio of the feature of the disclosure are intended to fall in the scope of the present disclosure.
Claims (20)
1. integrated circuit (IC) device of encapsulation, comprising:
Radiator；
The heat-radiating substrate based on diamond on the radiator, wherein the heat-radiating substrate based on diamond has across it
In through-hole array；With
Integrated circuit (IC) chip on the heat-radiating substrate based on diamond, wherein the edge of the IC chip and institute
State the overlapping of at least one of through-hole.
2. the IC device of encapsulation described in claim 1, wherein the through-hole is hollow via-hole.
3. the IC device of encapsulation described in claim 1 is configured as exporting wherein the IC chip is monolithic microwave IC chip
More than about 3W/mm parts peak power densities.
4. the IC device of encapsulation described in claim 1, wherein the IC chip includes GaN base high electron mobility transistor.
5. the IC device of encapsulation described in claim 1, wherein the heat-radiating substrate based on diamond, which has, is coated with conductive layer
Outer surface.
6. the IC device of encapsulation described in claim 5, wherein the outer surface of the heat-radiating substrate based on diamond forms institute
A part for stating the radio frequency grounding path of IC chip, in the main table for being arranged essentially parallel to the heat-radiating substrate based on diamond
Extend in the transverse direction in face.
7. the IC device of encapsulation described in claim 1, wherein it is described based on the heat-radiating substrate of diamond by polycrystalline diamond shape
At.
8. the IC device of encapsulation described in claim 1, wherein it is described based on the heat-radiating substrate of diamond by metal matrix Buddha's warrior attendant
Stone composite material is formed, which includes the diamond particles in metal matrix.
9. the IC device of encapsulation described in claim 1, wherein the through-hole is hollow.
10. the IC device of encapsulation described in claim 1, wherein the total volume of the through-hole is at least described based on diamond
The 3% of the volume of heat-radiating substrate.
11. the IC device of encapsulation described in claim 1, wherein the through-hole array includes even number through-hole, wherein half is logical
Hole positioning is with Chong Die with the first edge of the IC chip, and the positioning of another half-via is with the second edge with the IC chip
Overlapping.
12. a kind of method for assembling integrated circuit (IC) chip, this method comprises:
IC chip is located on the heat-radiating substrate based on diamond, which has the through-hole array passed through, makes
Obtain the imbricate of at least one through-hole and the IC chip；With
The IC chip is attached to the heat-radiating substrate based on diamond, so that at least one through-hole and the IC chip
Imbricate.
13. method described in claim 12, wherein positioning IC chip includes by the first through hole of the through-hole and the IC core
The imbricate of piece, and the second through-hole of the through-hole is Chong Die with the second edge of the IC chip.
14. method described in claim 12, wherein positioning IC chip includes logical around positioning described first substantially symmetrical about its central axisly
Hole and second through-hole, the central axis are upwardly extended in the side for being basically parallel to edge and second edge.
15. method described in claim 12, wherein the heat-radiating substrate based on diamond includes being coated with conductive metal layer
Outer surface.
16. integrated circuit (IC) device of encapsulation, comprising:
Heat-radiating substrate based on diamond has the through-hole array passed through；With
Monolithic integrated microwave circuit (MMIC) chip on the heat-radiating substrate based on diamond, the mmic chip are configured
It is more than about 3W/mm parts of peak power densities for output, wherein the edge of the mmic chip is Chong Die at least one through-hole, and
Wherein the heat-radiating substrate based on diamond is configured as the heat diffusion for generating the mmic chip far from the MMIC
Chip.
17. the IC device of encapsulation described in claim 16, wherein the through-hole is hollow, and described based on diamond
Heat-radiating substrate has conductive metal layer, which is substantially coated in the entire of the substrate on the surface including through-hole
On surface.
18. the IC device of encapsulation described in claim 16 is configured to wherein the mmic chip includes high-power pulsed ion beams
Dissipate at least peak power density of 3W/mm.
19. the IC device of encapsulation described in claim 17, wherein the mmic chip includes GaN base high electron mobility crystal
It manages (HEMT), is configured such that when peak power density consumption is more than about 3W/mm, substrate basal temperature and GaN base
Difference between the channel temperature of HEMT remains less than about 100 DEG C.
20. the IC device of encapsulation described in claim 16, wherein first group of through-hole is overlapped the first edge of the IC chip simultaneously
And the second edge of second group of corresponding through-hole overlapping and the of laterally opposite IC chip of the first edge, wherein described the
Each through-hole in one group and it is second group described in corresponding through-hole volume having the same.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201762553650P | 2017-09-01 | 2017-09-01 | |
| US62/553,650 | 2017-09-01 | ||
| US15/857,324 US10658264B2 (en) | 2017-09-01 | 2017-12-28 | Diamond-based heat spreading substrates for integrated circuit dies |
| US15/857,324 | 2017-12-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109427711A true CN109427711A (en) | 2019-03-05 |
| CN109427711B CN109427711B (en) | 2022-07-29 |
Family
ID=65364198
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811006587.1A Active CN109427711B (en) | 2017-09-01 | 2018-08-31 | Diamond-based heat dissipation substrate for integrated circuit chip |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109427711B (en) |
| DE (1) | DE102018121208B4 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110223918A (en) * | 2019-04-23 | 2019-09-10 | 西安电子科技大学 | A kind of aperture formula compound substrate gallium nitride device and preparation method thereof |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5371407A (en) * | 1991-06-07 | 1994-12-06 | Norton Company | Electronic circuit with diamond substrate and conductive vias |
| US6498394B1 (en) * | 1995-07-10 | 2002-12-24 | Ose Usa | IC packages with diamond substrate thermal conductor |
| US20090108437A1 (en) * | 2007-10-29 | 2009-04-30 | M/A-Com, Inc. | Wafer scale integrated thermal heat spreader |
| US20100140790A1 (en) * | 2008-12-05 | 2010-06-10 | Seagate Technology Llc | Chip having thermal vias and spreaders of cvd diamond |
| US20110001162A1 (en) * | 2008-04-18 | 2011-01-06 | Asahi Glass Company, Limited | Light emitting diode package |
| US20110062579A1 (en) * | 2003-01-02 | 2011-03-17 | Cree, Inc. | Group iii nitride based flip-chip integrated circuit and method for fabricating |
| US20140110722A1 (en) * | 2012-10-24 | 2014-04-24 | The Government Of The United States Of America, As Represented By The Secretary Of The Navy | Semiconductor Structure or Device Integrated with Diamond |
| WO2016151329A1 (en) * | 2015-03-26 | 2016-09-29 | Inex Microtechnology Limited | Carrier and insert |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9059254B2 (en) * | 2012-09-06 | 2015-06-16 | International Business Machines Corporation | Overlay-tolerant via mask and reactive ion etch (RIE) technique |
| US9997428B2 (en) * | 2015-07-14 | 2018-06-12 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Via structures for thermal dissipation |
-
2018
- 2018-08-30 DE DE102018121208.9A patent/DE102018121208B4/en active Active
- 2018-08-31 CN CN201811006587.1A patent/CN109427711B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5371407A (en) * | 1991-06-07 | 1994-12-06 | Norton Company | Electronic circuit with diamond substrate and conductive vias |
| US6498394B1 (en) * | 1995-07-10 | 2002-12-24 | Ose Usa | IC packages with diamond substrate thermal conductor |
| US20110062579A1 (en) * | 2003-01-02 | 2011-03-17 | Cree, Inc. | Group iii nitride based flip-chip integrated circuit and method for fabricating |
| US20090108437A1 (en) * | 2007-10-29 | 2009-04-30 | M/A-Com, Inc. | Wafer scale integrated thermal heat spreader |
| US20110001162A1 (en) * | 2008-04-18 | 2011-01-06 | Asahi Glass Company, Limited | Light emitting diode package |
| US20100140790A1 (en) * | 2008-12-05 | 2010-06-10 | Seagate Technology Llc | Chip having thermal vias and spreaders of cvd diamond |
| US20140110722A1 (en) * | 2012-10-24 | 2014-04-24 | The Government Of The United States Of America, As Represented By The Secretary Of The Navy | Semiconductor Structure or Device Integrated with Diamond |
| WO2016151329A1 (en) * | 2015-03-26 | 2016-09-29 | Inex Microtechnology Limited | Carrier and insert |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110223918A (en) * | 2019-04-23 | 2019-09-10 | 西安电子科技大学 | A kind of aperture formula compound substrate gallium nitride device and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| DE102018121208A1 (en) | 2019-03-07 |
| DE102018121208B4 (en) | 2021-04-29 |
| CN109427711B (en) | 2022-07-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI688062B (en) | Diamond-based heat spreading substrates for integrated circuit dies, method for assembling integrated circuit dies, and packaged integrated circuit device | |
| TWI809368B (en) | Rf amplifier devices and methods of manufacturing | |
| JP2013243362A (en) | Thermal spreader having graduated thermal expansion parameters | |
| US8796843B1 (en) | RF and milimeter-wave high-power semiconductor device | |
| US11863130B2 (en) | Group III nitride-based radio frequency transistor amplifiers having source, gate and/or drain conductive vias | |
| TWI798129B (en) | Rf amplifiers having shielded transmission line structures | |
| US11670605B2 (en) | RF amplifier devices including interconnect structures and methods of manufacturing | |
| CN115362545A (en) | Group III-nitride based radio frequency amplifier with backside source, gate and/or drain terminals | |
| JP7326844B2 (en) | Semiconductor device heat dissipation structure, manufacturing method thereof, amplifier | |
| CN108376705A (en) | Gallium nitride base power device of inverted structure with graphene heat dissipating layer and preparation method thereof | |
| TW201826533A (en) | High power transistors | |
| JP2023531915A (en) | Multizone radio frequency transistor amplifier | |
| CN109427711A (en) | The heat-radiating substrate based on diamond of IC chip | |
| KR102304613B1 (en) | Gallium nitride-based semiconductor package and method for fabricating thereof | |
| CN109037066A (en) | Semiconductor devices and its manufacturing method | |
| US10600718B1 (en) | Heat sink package | |
| CN108364923A (en) | Using the gallium nitride base power device and preparation method thereof of carbon nanotube microchannel heat sink | |
| US10593610B2 (en) | Semiconductor power device including wire or ribbon bonds over device active region | |
| US20240105692A1 (en) | Packaged flip chip radio frequency transistor amplifier circuits | |
| US8344430B2 (en) | Multiple substrate electrical circuit device | |
| US20230421119A1 (en) | Semiconductor device packages with exposed heat dissipating surfaces and methods of fabricating the same | |
| TW202324668A (en) | Radio frequency packages containing substrates with coefficient of thermal expansion matched mount pads and associated fabrication methods | |
| JP2013105977A (en) | High-frequency semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |