CN109426300A - Clock jitter detection method and device for system on chip - Google Patents
Clock jitter detection method and device for system on chip Download PDFInfo
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- CN109426300A CN109426300A CN201710764640.3A CN201710764640A CN109426300A CN 109426300 A CN109426300 A CN 109426300A CN 201710764640 A CN201710764640 A CN 201710764640A CN 109426300 A CN109426300 A CN 109426300A
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- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
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Abstract
The invention discloses a kind of clock jitter detection method and device for system on chip, method receives external detection signal the following steps are included: when system on chip is under preset reference atmosphere；From, to finish time, the clock to be measured controlled in system on chip remains operational state, and is counted to the jump number of clock to be measured to obtain the first count value, and using the first count value as a reference value at the beginning of reception external detection signal；In the actual moving process of system on chip, if necessary to carry out separate-blas estimation to clock to be measured, then external detection signal is received, and counted the jump number of clock to be measured to obtain the second count value during receiving external detection signal；Deviation ratio is calculated according to the second count value and a reference value, and detects the deviation situation of clock to be measured according to deviation ratio.Design accurate clock is avoided as a result, reduces design complexities, while flexibly control system can be needed to be detected according to detection.
Description
Technical field
The present invention relates to automobile technical field, in particular to a kind of clock jitter detection method for system on chip and
A kind of clock jitter detection device for system on chip.
Background technique
MCU chip internal clocking can generate deviation with the variation of external environment such as voltage, temperature, humidity etc., if partially
Difference exceeds the range of limit value, can run and impact to system, system may failure.In the related technology, usually using one
The continual monitoring clock to be detected of accurate clock frequency in a system design, and there are bright with clock to be monitored for accurate clock
Aobvious frequency distance passes through the clock of another slow frequency of the clock acquisition an of fast frequency, if certain time as a result,
Interior collected clock number appearance is significantly different, then can determine whether that obvious deviation occurs in clock to be monitored.
But the relevant technologies the problem is that, need an accurate clock frequency continual monitoring band detection clock,
It needs to guarantee that the clock and chip can guarantee accuracy under any changes in environmental conditions simultaneously, realizes that condition is more demanding.
Summary of the invention
The present invention is directed to solve one of the technical problem in above-mentioned technology at least to a certain extent.For this purpose, of the invention
One purpose is to propose a kind of clock jitter detection method for system on chip, can be avoided and design one in any environment
The accurate clock that can guarantee accuracy under condition variation, reduces design complexities.
It is another object of the present invention to propose a kind of clock jitter detection device for system on chip.
In order to achieve the above objectives, one aspect of the present invention embodiment proposes a kind of clock jitter detection for system on chip
Method, comprising the following steps: when system is under preset reference atmosphere on said sheets, receive external detection signal；From connecing
It receives at the beginning of the external detection signal to finish time, the clock to be measured controlled in the system on chip remains operational shape
State, and the jump number of the clock to be measured is counted to obtain the first count value, and first count value is made
On the basis of be worth；On said sheets in the actual moving process of system, if necessary to carry out separate-blas estimation to the clock to be measured, then
The external detection signal is received, and to the jump number of the clock to be measured during receiving the external detection signal
It is counted to obtain the second count value；Deviation ratio is calculated according to second count value and a reference value, and according to described
Deviation ratio detects the deviation situation of the clock to be measured.
The clock jitter detection method for system on chip proposed according to embodiments of the present invention is in pre- in system on chip
If reference atmosphere under when, receive external detection signal, from receive external detection signal at the beginning of to finish time, treat
The jump number for surveying clock is counted to obtain the first count value, and using the first count value as a reference value, on piece system
In the actual moving process of system, if necessary to carry out separate-blas estimation to clock to be measured, then external detection signal is received, and receiving
The jump number of clock to be measured is counted to obtain the second count value during external detection signal, and then according to second
Count value and a reference value calculate deviation ratio, and the deviation situation of clock to be measured is detected according to deviation ratio.The embodiment of the present invention as a result,
Clock jitter detection method use scale of the external signal as clock detection, save under preset reference atmosphere clock spy
Property and clock jitter is detected as benchmark, thus avoid design one can guarantee under any changes in environmental conditions
The accurate clock of accuracy reduces design complexities, while flexibly control system can be needed to be detected according to detection, does not need
The continual monitoring band detection clock of frequency, flexibility are good.
In order to achieve the above objectives, another aspect of the present invention embodiment proposes a kind of clock jitter inspection for system on chip
Survey device, comprising: receiving port, the receiving port when system is under preset reference atmosphere on said sheets for receiving
External detection signal；Control unit, described control unit are used in the receiving port from receiving the external detection signal
Start time to finish time, the clock to be measured controlled in the system on chip remain operational state；Accumulated unit, it is described accumulative
Unit be used for during the receiving port receives the external detection signal to the jump number of the clock to be measured into
Row is counted to obtain the first count value, and first count value is sent to described control unit, and described control unit is used for
Using first count value as a reference value；Described control unit is also used to, on said sheets in the actual moving process of system,
If necessary to carry out separate-blas estimation to the clock to be measured, then the external detection signal is received by the receiving port, and
It is counted during receiving the external detection signal by jump number of the accumulated unit to the clock to be measured
Number calculates deviation ratio to obtain the second count value, and according to second count value and a reference value, and according to described inclined
Rate detects the deviation situation of the clock to be measured.
The clock jitter detection device for system on chip proposed according to embodiments of the present invention, receiving port is on piece system
Receive external detection signal when system is under the preset reference atmosphere, accumulated unit is at the beginning of receive external detection signal
To finish time, the jump number of clock to be measured is counted to obtain the first count value, control unit is by the first count value
As a reference value, and in the actual moving process of system on chip, if necessary to carry out separate-blas estimation to clock to be measured, then pass through
Receiving port receives external detection signal, and passes through accumulated unit to clock to be measured during receiving external detection signal
Jump number is counted to obtain the second count value, and then according to the second count value and a reference value calculating deviation ratio, and according to
Deviation ratio detects the deviation situation of clock to be measured.The clock jitter detection device of the embodiment of the present invention uses external signal as a result,
As the scale of clock detection, saves the clock characteristic under preset reference atmosphere and clock jitter is examined as benchmark
It surveys, so that design one be avoided to can guarantee the accurate clock of accuracy under any changes in environmental conditions, it is complicated to reduce design
Degree, while flexibly control system can be needed to be detected according to detection, do not need the continual monitoring band detection clock of frequency, spirit
Activity is good.
Detailed description of the invention
Fig. 1 is the flow chart according to the clock jitter detection method for system on chip of the embodiment of the present invention；
Fig. 2 is the block diagram according to the clock jitter detection device for system on chip of the embodiment of the present invention；With
And
Fig. 3 is to be illustrated according to the principle of the clock jitter detection device for system on chip of one embodiment of the invention
Figure.
Specific embodiment
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, it is intended to is used to explain the present invention, and is not considered as limiting the invention.
The clock jitter detection method and device for system on chip of the embodiment of the present invention described with reference to the accompanying drawing.
Fig. 1 is the flow chart according to the clock jitter detection method for system on chip of the embodiment of the present invention.Such as Fig. 1 institute
Show, detection method includes the following steps for the clock jitter for system on chip of the embodiment of the present invention:
S1: when system on chip is under preset reference atmosphere, external detection signal is received.
It should be noted that preset reference atmosphere can be so that system on chip is in and stablizes and typical external environment,
Ensure that the conditions constants such as temperature, voltage are constant.A specific embodiment according to the present invention, preset reference atmosphere can be ring
Border temperature is 25 degrees Celsius, and the voltage of system on chip is 5V.
According to one embodiment of present invention, external detection signal, method further include: connecing can be received by receiving port
When receiving detection instruction, judgement needs to carry out clock jitter detection, and the function of receiving port is automatically switched to time signal
Input function, while being sent to external device (ED) and preparing instruction to be measured, so as to when external device (ED), which receives, prepares instruction to be measured to connecing
Receiving end mouth sends external detection signal.In other words, which will be switched to the time when needing to carry out clock jitter detection
Signal input function, the i.e. input port as external detection signal, and do not needing to carry out the i.e. normal work of clock jitter detection
As when be switched to working port.
According to one embodiment of present invention, external detection signal can be set time signal.That is, outside system
External device (ED) can be sent into a set time signal to the clock jitter detection device of system on chip.Wherein, set time signal
Time span can be 100ms.
S2: from, to finish time, the clock to be measured controlled in system on chip is protected at the beginning of reception external detection signal
Operating status is held, and the jump number of clock to be measured is counted to obtain the first count value, and the first count value is made
On the basis of be worth.
It should be noted that clock to be measured can be the clock source that frequency changes vulnerable to external environment variation, together
When, internal control clock of the clock to be measured as system on chip, system on chip shifts to an earlier date system brought by processed good timing skew
System influences, it is ensured that system on chip is still able to work normally when clock to be measured is under largest tolerable deviation.
In one embodiment of the invention, it can be counted by jump number of the accumulated unit to clock to be measured.?
That is clock to be measured, which starts simultaneously at, to be run, and accumulated unit start recording is to be measured when external detection signal starts input
The jump number of clock；When the external detection signal terminates input, clock to be measured can be continued to run, and accumulated unit stops note
Record, accumulated unit generates a count value i.e. the first count value at this time.First count value can be used as a reference value C.
It should be understood that the proportionate relationship between the first count value and the time span of set time signal can be used as piece
The frequency of clock to be measured in the case where preset reference atmosphere is relatively stable and typical external environment, that is, be considered steady in upper system
Determine frequency.
S3: it in the actual moving process of system on chip, if necessary to carry out separate-blas estimation to clock to be measured, then receives outer
Signal is detected in portion, and is counted the jump number of clock to be measured to obtain second during receiving external detection signal
Count value.
That is, need to carry out separate-blas estimation to clock to be measured when the external environment of system on chip changes, with
Clock to be measured is detected whether since environmental change goes wrong.It can continue to examine to the clock jitter of system on chip under the present circumstances
It surveys device and is sent into a same external detection signal such as set time signal, passed through using method same as step S2 tired
Meter unit is counted, and count value i.e. the second count value C2 under current environment is obtained.
S4: deviation ratio is calculated according to the second count value and a reference value, and detects the deviation feelings of clock to be measured according to deviation ratio
Condition.
Wherein, deviation ratio p, i.e. p=can be calculated by the following formula | C-C2 | it is worth on the basis of/C, C, C2 is the second counting
Value.
That is, under the present circumstances, it, can the second count value and a reference value calculating deviation after obtaining the second count value
Rate, and calculated deviation ratio is compared with predetermined deviation rate, it can determine whether the deviation feelings of clock to be measured according to comparison result
Condition, for example, judging that obvious deviation occurs in clock to be measured if deviation ratio is greater than predetermined deviation rate, that is, being more than that maximum can be held
Bear deviation, system on chip can not work normally；If deviation ratio is less than or equal to predetermined deviation rate, judge that clock to be measured does not go out
Existing obvious deviation, i.e., under largest tolerable deviation, system on chip be can still work normally.
Specifically, in an embodiment of the present invention, when system on chip is in initial phase, system on chip is in pre-
If reference atmosphere, it is ensured that the conditions constants such as temperature, voltage are constant.At this point, external device (ED) is sent into one to by receiving port
External detection signal, the present embodiment control system on chip and are detecting set time letter by taking set time signal as an example
Number start and ending during be always maintained at operation clock to be measured, and by accumulated unit to clock to be measured during this
Jump number is counted.When accumulated unit is completed to count, the count value of accumulated unit at this time is saved to count as first
Value, using the first count value as a reference value.
When the external environment of system on chip changes, needs to carry out separate-blas estimation to clock to be measured, front ring can worked as
Outside port is continued through under border and receives a set time signal same as step S1, in the mistake for receiving external detection signal
It is also counted by jump number of the accumulated unit to clock to be measured in journey, the count value i.e. second obtained under current environment is counted
Numerical value.
Since external detection signal, that is, set time signal fixation is unchanged, so the count value directly obtained more twice is i.e.
A reference value and the second count value can be detected the deviation situation of clock to be measured, if the second count value compares the deviation ratio of a reference value
Beyond predetermined deviation rate, then it is assumed that current clock frequency has exceeded the frequency range normally approved, is completed at this time to clock to be measured
Detection.
In addition, according to one embodiment of present invention, when system on chip is under preset reference atmosphere, can repeatedly connect
Receive external detection signal, and every time receive external detection signal during to the jump number of clock to be measured counted with
Multiple first count values are obtained, and by carrying out mean value computation to multiple first count values to obtain a reference value.
That is, external detection signal can be repeatedly received, each when system on chip is under preset reference atmosphere
During receiving external detection signal, when external detection signal starts input, clock to be measured, which starts simultaneously at, to be run, and is tired out
The jump number for counting unit start recording clock to be measured, when the external detection signal terminates input, clock to be measured can be after reforwarding
Row, accumulated unit stop recording.As a result, after repeatedly having received external detection signal, accumulated unit can generate multiple respectively
First count value, for example, C1, C2, C3 ..., Cn, by taking average operation, can be obtained a reference value C=(C1+C2+C3+ ...+Cn)/
N, a reference value can be reserved for system on chip.
Thereby, it is possible to avoid the influence of environmental condition or system response time being slightly variable, error is reduced, improves detection essence
Degree.
Carry out the clock jitter for system on chip of the present invention is described in detail embodiment below with reference to a specific embodiment
Detection method.
It include clock A to be measured inside system on chip, design center frequency (achievable frequency under i.e. preset reference atmosphere
Rate) it is 20MHz, frequency range normal fluctuation is 20MHz ± 10%, i.e. 18MHz~22MHz then thinks to be measured beyond this range
Clock A is abnormal.And, it is possible to provide a receiving port, to receive external detection signal, in the present embodiment, external detection
Signal is set time signal.Specifically, which is working port in normal work, is needing to carry out clock jitter
Port when detection to receive set time signal.
When system on chip is under the preset reference environment that environment temperature is 25 degrees Celsius, the voltage of system on chip is 5V,
System on chip needs to detect clock to be measured, is at this time time signal input function by the function switch of receiving port, and inform outer
Part device is ready for receiving set time signal, sets the time span of set time signal as 100ms, when the set time
When signal starts to be input to receiving port, the clock to be measured for controlling system on chip, which starts simultaneously at, to be run, and accumulated unit starts
Record the jump number of clock to be measured；When the set time signal terminates input, clock to be measured can be continued to run, accumulated unit
It stops recording, generates a first count value C1 at this time.It, can be after due to being slightly variable for environmental condition or system response time
Same set time signal is received in continued access, and in the received jump for recording clock to be measured by accumulated unit in the process every time
Number, can generate respectively first count value C2, C3 ..., Cn.After the completion of detection, by taking average operation to reduce error, benchmark is obtained
Value C=(C1+C2+C3+ ...+Cn)/n is saved to storage unit.For example, it can receive set time signal 5 times, obtain respectively
To the first count value be respectively as follows: C1=2,000,085, C2=2,000,032, C3=2,000,064, C4=2,000,102,
C5=2,000,023, then C=2,000,061.
It needs to carry out separate-blas estimation to clock to be measured, can be again time signal input work by the function switch of receiving port
Can, and inform that external device (ED) is ready for receiving set time signal, by accumulative during receiving set time signal
Unit is counted to obtain the second count value C2.
Under a certain environment, the second count value C2=1,882,361, the second count value C2 of calculating and a reference value C can be measured
Deviation ratio are as follows: | C-C2 |/C=5.9%,
Under another environment, the second count value C2=2,318,992, the second count value C2 of calculating and a reference value C can be measured
Deviation ratio are as follows: | C-C2 |/C=15.9%；
It can detect the deviation situation of clock to be measured under any environment according to deviation ratio as a result,.
To sum up, the clock jitter detection method for system on chip proposed according to embodiments of the present invention, in system on chip
When under preset reference atmosphere, receive external detection signal, from receive external detection signal at the beginning of at the end of
It carves, the jump number of clock to be measured is counted to obtain the first count value, and using the first count value as a reference value,
In the actual moving process of system on chip, if necessary to carry out separate-blas estimation to clock to be measured, then external detection signal is received, and
The jump number of clock to be measured is counted to obtain the second count value, Jin Ergen during receiving external detection signal
Deviation ratio is calculated according to the second count value and a reference value, and detects the deviation situation of clock to be measured according to deviation ratio.It is of the invention as a result,
The clock jitter detection method of embodiment uses scale of the external signal as clock detection, saves under preset reference atmosphere
Clock characteristic simultaneously detects clock jitter as benchmark, to avoid design one equal under any changes in environmental conditions
It can guarantee the accurate clock of accuracy, reduce design complexities, while flexibly control system can be needed to be detected according to detection,
The continual monitoring band detection clock of frequency is not needed, flexibility is good.
It is corresponding with the clock jitter detection method for system on chip that above-mentioned several embodiments provide, of the invention one
Kind embodiment also provides a kind of clock jitter detection device for system on chip, is used for piece due to provided in an embodiment of the present invention
The clock jitter detection method for system on chip that the clock jitter detection device of upper system and above-mentioned several embodiments provide
It is corresponding, thus the embodiment for the clock jitter detection method for being previously used for system on chip be also applied for the present embodiment provides
The clock jitter detection device for system on chip, be not described in detail in the present embodiment.
Fig. 2 is the block diagram of the clock jitter detection device according to an embodiment of the present invention for system on chip.Such as
Clock jitter detection device shown in Fig. 2, for system on chip, comprising: receiving port 10, accumulated unit 20 and control unit
30。
Wherein, receiving port 10 is used to receive external detection signal when system on chip is under preset reference atmosphere；
Control unit 30 is used in receiving port 10 to finish time, controlling system on chip at the beginning of receiving external detection signal
In clock to be measured remain operational state；Accumulated unit 20 is used for right during receiving port 10 receives external detection signal
The jump number of clock to be measured is counted to obtain the first count value, and the first count value is sent to control unit 30, control
Unit 30 processed is used for using the first count value as a reference value；Control unit 30 is also used to, in the actual moving process of system on chip
In, if necessary to carry out separate-blas estimation to clock to be measured, then external detection signal is received by receiving port 10, and outer receiving
It is counted during portion's detection signal by jump number of the accumulated unit 20 to clock to be measured to obtain the second count value,
And deviation ratio is calculated according to the second count value and a reference value, and the deviation situation of clock to be measured is detected according to deviation ratio.
According to this specific embodiment of the invention, preset reference atmosphere can be that environment temperature is 25 degrees Celsius, piece
The voltage of upper system is 5V.
According to this specific embodiment of the invention, external detection signal is set time signal.
According to this specific embodiment of the invention, when system on chip is under preset reference atmosphere, control is single
Member 30 is also used to, by more than 10 reception external detection signals of receiving port, and in the process for receiving external detection signal every time
In counted by jump number of the accumulated unit 20 to clock to be measured to obtain multiple first count values, and to multiple
One count value carries out mean value computation to obtain a reference value.
A specific embodiment according to the present invention, as shown in figure 3, control unit 30 is also used to receiving detection instruction
When judgement need to carry out separate-blas estimation to clock to be measured, and the function of receiving port 10 is automatically switched into time signal input work
Can, while being sent to external device (ED) and preparing instruction to be measured, so as to when external device (ED), which receives, prepares instruction to be measured to receiving port
10 send external detection signal.
Specifically, as shown in figure 3, control unit 30 can when system on chip configuration needs to carry out clock jitter detection
Detection instruction is received, control unit 30 controls subelement 31 by function switch and automatically switches to the function of receiving port 10
Time signal input function, while external device (ED) is issued and prepares instruction to be measured, external device (ED), which will receive, prepares instruction to be measured
When issue external detection signal immediately to receiving port 10.Control unit 30 detects outside by time signal detection sub-unit 32
Signal is detected, when receiving port 10 receives the starting end of external detection signal, control unit 30 will start accumulative single simultaneously
Member 20 and clock to be measured, it is ensured that effectively count, accumulated unit 20 records the jump number of clock to be measured, when receiving port 10 receives
To external detection signal end when, control unit 30 will control accumulated unit 20 and stop counting, while by accumulated unit 20
Count results save into storage unit 40, in order to system on chip reading.
To sum up, the clock jitter detection device for system on chip proposed according to embodiments of the present invention, receiving port exist
External detection signal is received when system on chip is under preset reference atmosphere, accumulated unit is opened from reception external detection signal
Begin moment to finish time, the jump number of clock to be measured is counted to obtain the first count value, control unit is by first
Count value carries out separate-blas estimation to clock to be measured if necessary as a reference value, and in the actual moving process of system on chip,
External detection signal is then received by receiving port, and passes through accumulated unit to be measured during receiving external detection signal
The jump number of clock is counted to obtain the second count value, and then calculates deviation ratio according to the second count value and a reference value,
And the deviation situation of clock to be measured is detected according to deviation ratio.The clock jitter detection device of the embodiment of the present invention is using outer as a result,
Scale of portion's signal as clock detection saves the clock characteristic under preset reference atmosphere and as benchmark to clock jitter
It is detected, to avoid designing the accurate clock that can guarantee accuracy under any changes in environmental conditions, reduction is set
Complexity is counted, while flexibly control system can be needed to be detected according to detection, does not need the continual monitoring band detection of frequency
Clock, flexibility are good.
In the description of the present invention, it is to be understood that, term " center ", " longitudinal direction ", " transverse direction ", " length ", " width ",
" thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside", " up time
The orientation or positional relationship of the instructions such as needle ", " counterclockwise ", " axial direction ", " radial direction ", " circumferential direction " be orientation based on the figure or
Positional relationship is merely for convenience of description of the present invention and simplification of the description, rather than the device or element of indication or suggestion meaning must
There must be specific orientation, be constructed and operated in a specific orientation, therefore be not considered as limiting the invention.
In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include one or more of the features.In the description of the present invention, the meaning of " plurality " is two or more,
Unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " fixation " etc.
Term shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integral；It can be mechanical connect
It connects, is also possible to be electrically connected；It can be directly connected, can also can be in two elements indirectly connected through an intermediary
The interaction relationship of the connection in portion or two elements.It for the ordinary skill in the art, can be according to specific feelings
Condition understands the concrete meaning of above-mentioned term in the present invention.
In the present invention unless specifically defined or limited otherwise, fisrt feature in the second feature " on " or " down " can be with
It is that the first and second features directly contact or the first and second features pass through intermediary mediate contact.Moreover, fisrt feature exists
Second feature " on ", " top " and " above " but fisrt feature be directly above or diagonally above the second feature, or be merely representative of
First feature horizontal height is higher than second feature.Fisrt feature can be under the second feature " below ", " below " and " below "
One feature is directly under or diagonally below the second feature, or is merely representative of first feature horizontal height less than second feature.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
It must be directed to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be in office
It can be combined in any suitable manner in one or more embodiment or examples.In addition, without conflicting with each other, the skill of this field
Art personnel can tie the feature of different embodiments or examples described in this specification and different embodiments or examples
It closes and combines.
Although the embodiments of the present invention has been shown and described above, it is to be understood that above-described embodiment is example
Property, it is not considered as limiting the invention, those skilled in the art within the scope of the invention can be to above-mentioned
Embodiment is changed, modifies, replacement and variant.
Claims (9)
1. a kind of clock jitter detection method for system on chip, which comprises the following steps:
When system is under preset reference atmosphere on said sheets, external detection signal is received；
From, to finish time, the clock to be measured controlled in the system on chip is protected at the beginning of the reception external detection signal
Operating status is held, and the jump number of the clock to be measured is counted to obtain the first count value, and by described first
Count value is as a reference value；
On said sheets in the actual moving process of system, if necessary to carry out separate-blas estimation to the clock to be measured, then receive
The external detection signal, and the jump number of the clock to be measured is carried out during receiving the external detection signal
It counts to obtain the second count value；
Deviation ratio is calculated according to second count value and a reference value, and the clock to be measured is detected according to the deviation ratio
Deviation situation.
2. the clock jitter detection method according to claim 1 for system on chip, which is characterized in that described preset
Reference atmosphere is that environment temperature is 25 degrees Celsius, and the voltage of the system on chip is 5V.
3. the clock jitter detection method according to claim 1 for system on chip, which is characterized in that the external inspection
Survey signal is set time signal.
4. the clock jitter detection method according to claim 1 for system on chip, which is characterized in that on said sheets
When system is under the preset reference atmosphere, the external detection signal is repeatedly received, and receiving the outside every time
The jump number of the clock to be measured is counted during detection signal to obtain multiple first count values, and is passed through
Mean value computation is carried out to obtain a reference value to the multiple first count value.
5. a kind of clock jitter detection device for system on chip characterized by comprising
Receiving port, the receiving port is for receiving external detection when system is under preset reference atmosphere on said sheets
Signal；
Control unit, described control unit be used for the receiving port from receive the external detection signal at the beginning of to
Finish time, the clock to be measured controlled in the system on chip remain operational state；
Accumulated unit, the accumulated unit are used for during the receiving port receives the external detection signal to described
The jump number of clock to be measured is counted to obtain the first count value, and first count value is sent to the control list
Member, described control unit are used for using first count value as a reference value；
Described control unit is also used to, on said sheets in the actual moving process of system, if necessary to the clock to be measured
Separate-blas estimation is carried out, then the external detection signal is received by the receiving port, and receiving the external detection signal
During counted by jump number of the accumulated unit to the clock to be measured to obtain the second count value, and
Deviation ratio is calculated according to second count value and a reference value, and the inclined of the clock to be measured is detected according to the deviation ratio
Poor situation.
6. the clock jitter detection device according to claim 5 for system on chip, which is characterized in that described preset
Reference atmosphere is that environment temperature is 25 degrees Celsius, and the voltage of the system on chip is 5V.
7. the clock jitter detection device according to claim 5 for system on chip, which is characterized in that the external inspection
Survey signal is set time signal.
8. the clock jitter detection device according to claim 5 for system on chip, which is characterized in that on said sheets
When system is under the preset reference atmosphere, described control unit is also used to, and repeatedly receives institute by the receiving port
State external detection signal, and during receiving the external detection signal every time by the accumulated unit to described to be measured
The jump number of clock is counted to obtain multiple first count values, and carries out mean value meter to the multiple first count value
It calculates to obtain a reference value.
9. being used for the clock jitter detection device of system on chip according to any one of claim 5-8, which is characterized in that
Described control unit is also used to judge to need when receiving detection instruction to carry out the clock to be measured separate-blas estimation, and by institute
The function of stating receiving port automatically switches to time signal input function, while sending to external device (ED) and preparing instruction to be measured, with
Toilet is stated and sends the external detection signal to the receiving port when external device (ED) receives preparation instruction to be measured.
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