CN109413339A - A kind of vision signal generating means and method - Google Patents
A kind of vision signal generating means and method Download PDFInfo
- Publication number
- CN109413339A CN109413339A CN201811612805.6A CN201811612805A CN109413339A CN 109413339 A CN109413339 A CN 109413339A CN 201811612805 A CN201811612805 A CN 201811612805A CN 109413339 A CN109413339 A CN 109413339A
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- fpga
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- generating means
- signal generating
- vision signal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/2621—Cameras specially adapted for the electronic generation of special effects during image pickup, e.g. digital cameras, camcorders, video cameras having integrated special effects capability
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Studio Devices (AREA)
Abstract
A kind of vision signal generating means and method, belong to electronic technology field, it is characterised in that: including FPGA main control module, CameraLink coding module, PCIe communication module and power module；The FPGA main control module includes FPGA, memory module, crystal oscillator and communication interface；The memory module, crystal oscillator and communication interface are electrically connected with FPGA；The PCIe communication module is provided with PCIe interface；The CameraLink coding module and power module are electrically connected with FPGA；The PCIe communication module is electrically connected by PCIe interface and FPGA.CameraLink is generated by FPGA and exports video, makes full use of the field-programmable characteristic of FPGA, for the debugging and emulation of a variety of CameraLink signal handling equipments, is significantly improved the flexibility of CameraLink exploitation debugging, is reduced development cost.
Description
Technical field
The invention belongs to electronic technology field more particularly to a kind of vision signal generating means and method.
Background technique
CameraLink interface is digital picture interface.At present in fields such as Image Acquisition, safety monitoring and industrial productions
A large amount of to use, the image procossing product category based on CameraLink interface is various.Since CameraLink does not have the logical of standard
Letter specification has differences on transmission time sequence and definition, makes though the different product of each producer is all made of CameraLink interface
It is not high at the compatibility between different product.The product of CameraLink interface mainly includes the camera and figure of Image Acquisition front end
As the image processing equipment of processing rear end.In the development phase of both products, it is required to opposite equip. and carries out joint debugging and verifying.
In product service stage, two kinds of products tend not to replacement opposite end product type due to compatibility issue.If desired it replaces wherein
The product type of one end generally requires opposite end product and is replaced or modified.
For the joint debugging and verifying of CameraLink camera, there is CameraLink image pick-up card on the market.It is this
Capture card is feature-rich, can support a variety of resolution ratio and frame frequency, and provides the state modulator of camera.CameraLink is schemed
As processing equipment, on the market still without good joint debugging and verifying equipment；When replacing camera model, often bring at image
Manage the change of equipment.During change, the adjustment and verifying of many kinds of parameters are needed, this just needs a kind of parameter that can flexibly adjust
Whole vision signal generating means.
Summary of the invention
Present invention seek to address that the above problem, a kind of vision signal generating means that parameter can be adjusted flexibly and side are provided
Method.
Vision signal generating means of the present invention, including FPGA main control module, CameraLink coding module, PCIe are logical
Believe module and power module；The FPGA main control module includes FPGA, memory module, crystal oscillator and communication interface；The storage mould
Block, crystal oscillator and communication interface are electrically connected with FPGA；The PCIe communication module is provided with PCIe interface；It is described
CameraLink coding module and power module are electrically connected with FPGA；The PCIe communication module by PCIe interface with
FPGA is electrically connected.
Vision signal generating means of the present invention, the memory module include NOR FLASH and DDR III SDRAM；
There are two the DDR III SDRAM settings；The NOR FLASH is provided with QSPI interface；NOR FLASH is for storing work
Make code, DDR III SDRAM for running caching.
Vision signal generating means of the present invention, the communication interface include JPTG interface, and JPTG interface is for debugging.
Vision signal generating means of the present invention, the coding module are made of LVDS serializer module.
Vision signal generating means of the present invention, the power module include the DC/DC chip that several are set side by side；
The power voltage step down of input is the various low-tension supplies needed inside vision signal generating device by power module, for each modular circuit
Work uses.Several DC/DC are in sane level relationship, and different voltages output is generated after taking electricity from same voltage source respectively.
Vision signal generating means of the present invention, the power module include four LTM4623 chips and one
TPS51100 chip.
Vision signal generating means of the present invention, the output voltage of four LTM4623 chips be respectively 3.3V,
1.0V, 1.2V and 1.5V；The output voltage of the TPS51100 chip is 0.75V.
The generation method of vision signal generating means of the present invention, will need video content to be shown and control command to lead to
The PCIe interface for crossing PCIe communication module is transmitted to FPGA, and FPGA main control module passes through FPGA root after caching to video content
Image modulation processing is carried out to the image in video content according to control command, then is carried out serially by CameraLink coding module
It is exported after processing.
The generation method of vision signal generating means of the present invention, described image modulation treatment include image scaling, DDR
Caching, image sharpening, color space conversion, image superposition, frame frequency conversion and resolution ratio setting.
The generation method of vision signal generating means of the present invention, the serial process out is to believe 28 bit parallel datas
Number be converted to LVDS differential signal.
Vision signal generating means and method of the present invention, including FPGA main control module, CameraLink coding module,
PCIe communication module and power module；The FPGA main control module includes FPGA, memory module, crystal oscillator and communication interface；It is described
Memory module, crystal oscillator and communication interface are electrically connected with FPGA；CameraLink, which is generated, by FPGA exports video, sufficiently benefit
With the field-programmable characteristic of FPGA, the flexibility of CameraLink exploitation debugging is significantly improved, development cost is reduced.
Detailed description of the invention
Fig. 1 is the structural schematic block diagram of vision signal generating means of the present invention；
Fig. 2 is the flow diagram of vision signal generation method of the present invention；
Fig. 3 is the CameraLink coding module structural schematic diagram of vision signal generating means of the present invention；
Fig. 4 is vision signal generating means PCIe communication module structural schematic diagram of the present invention；
Fig. 5 is vision signal generating means power module structure schematic diagram of the present invention.
Specific embodiment
Vision signal generating means of the present invention and method are described in detail below by embodiment.
Embodiment one
Vision signal generating means of the present invention, as shown in Figure 1, include FPGA main control module, CameraLink coding module,
PCIe communication module and power module；The FPGA main control module includes FPGA, memory module, crystal oscillator and communication interface；It is described
Memory module, crystal oscillator and communication interface are electrically connected with FPGA；The PCIe communication module is provided with PCIe interface；It is described
CameraLink coding module and power module are electrically connected with FPGA；The PCIe communication module by PCIe interface with
FPGA is electrically connected.The memory module includes NOR FLASH and DDR III SDRAM；The DDR III SDRAM setting
There are two；The NOR FLASH is provided with QSPI interface；NOR FLASH is for storing operation code, DDR III SDRAM use
It is cached in operation.The communication interface includes JPTG interface, and JPTG interface is for debugging.
Vision signal generating means of the present invention, as shown in figure 3, the CameraLink coding module is serial by LVDS
Device module composition.As shown in figure 5, the power module includes five DC/DC chips being set side by side；Including four LTM4623
Chip and a TPS51100 chip, power module need the power voltage step down of input each inside vision signal generating device
Kind low-tension supply, works for each modular circuit and uses.The output voltage of four LTM4623 chips be respectively 3.3V, 1.0V,
1.2V and 1.5V；The output voltage of the TPS51100 chip is 0.75V；Input is the 12V power supply of PCIe interface.
In the present embodiment, FPGA selects XC7A100T-FGG676 model, FPGA main control module according to consumption I/O pin number
It receives and connects each functional module, mainly complete Digital Image Processing, including image scaling, DDR caching, image sharpening, color sky
Between conversion, image superposition, frame frequency conversion, resolution ratio setting etc..CameraLink coding module major function is to export FPGA
Parallel 28 data serial process be the difference LVDS signal for meeting CameraLink transmission specification.PCIe communication module is main
The data communication between flying-spot video generator and PC host is completed, Content of Communication includes display image and control command etc..Power supply
Module will be the various low-tension supplies needed inside flying-spot video generator from the power voltage step down that PC host inputs, for each module electricity
Road work uses.The golden finger part of PCIe interface, can be directly in the PCIe slot for being inserted in PC host, as shown in figure 4, with X1
For the PCIe communication of rate, the X16 rate communication of PCIe can be extended to according to use environment.PC host passes through golden finger interface
Communication and power supply are provided for vision signal generating means.
FPGA main control module is by groups such as the NOR FLASH of FPGA, QSPI interface, DDR3 SDRAM, crystal oscillator and jtag interfaces
At.FPGA contains 8 pairs of high speed ports, the DDR3 of the model MT41K256M16HA-125IT:E of company, plug-in two panels Micron Technology
Caching of the SDRAM as image, capacity 512MB, the total 1GB of two panels, clock frequency are up to 667MHz, meet FPGA calculation process
Data buffering demand in the process.In data handling, two panels caching does ping-pong operation, guarantees data normal communication.FPGA matches
The NOR FALSH chip that ROM uses QSPI interface is set, model W25Q128FV, operating voltage 3.3V are directly connect with FPGA.
As shown in figure 3, CameraLink coding module is mainly made of LVDS serializer DS90CR287 chip, by FPGA
28 3.3V parallel data signals of output are converted to LVDS differential signal, and the data bit of coding meets CameraLink transmission rule
Model.Out connector is CameraLink standard connector MDR26.
As shown in figure 4, PCIe communication module is realized using PCIe bridge chip between flying-spot video generator and PC host
Video data transmission is completed in communication.PCIe bridge chip model selects PEX8311 in the present embodiment.Design PCIe is connected using X1
It connects, the every direction speed of the chip is up to 2.5Gbps.
Embodiment two
On the basis of example 1, the generation method of vision signal generating means of the present invention, as shown in Fig. 2, will need
The video content and control command of display are transmitted to FPGA by the PCIe interface of PCIe communication module, and FPGA main control module is to view
Frequency content passes through FPGA and carries out image modulation processing to the image in video content according to control command after being cached, then passes through
CameraLink coding module exports after carrying out serial process.Described image modulation treatment includes image scaling, DDR caching, figure
As sharpening, color space conversion, image superposition, frame frequency conversion and resolution ratio setting.The serial process out is by 28 parallel-by-bits
Data-signal is converted to LVDS differential signal.
PC host is generated by the software in host computer needs video to be shown；Video content is communicated to by PCIe interface
After the FPGA of flying-spot video generator, FPGA carry out the processing such as image buffer storage, graph transformation, superposition reinforcing, pass through
CameraLink video interface carries out output and shows.FPGA can produce customized output timing, thus generate different frame frequencies and
The vision signal of resolution ratio.
Vision signal generating means of the present invention use modularized design, cooperate simple structural housing that can form function
Video signal source abundant has high flexibility for the debugging and emulation of a variety of CameraLink signal handling equipments.
Claims (10)
1. a kind of vision signal generating means, it is characterised in that: including FPGA main control module, CameraLink coding module,
PCIe communication module and power module；The FPGA main control module includes FPGA, memory module, crystal oscillator and communication interface；It is described
Memory module, crystal oscillator and communication interface are electrically connected with FPGA；The PCIe communication module is provided with PCIe interface；It is described
CameraLink coding module and power module are electrically connected with FPGA；The PCIe communication module by PCIe interface with
FPGA is electrically connected.
2. vision signal generating means according to claim 1, it is characterised in that: the memory module includes NOR FLASH
With DDR III SDRAM；There are two the DDR III SDRAM settings；The NOR FLASH is provided with QSPI interface.
3. vision signal generating means according to claim 2, it is characterised in that: the communication interface includes JPTG interface.
4. vision signal generating means according to claim 3, it is characterised in that: the coding module is by LVDS serializer mould
Block composition.
5. vision signal generating means according to claim 4, it is characterised in that: the power module includes that several are arranged side by side
The DC/DC chip of setting.
6. vision signal generating means according to claim 5, it is characterised in that: the power module includes four
LTM4623 chip and a TPS51100 chip.
7. vision signal generating means according to claim 6, it is characterised in that: the output of four LTM4623 chips
Voltage is respectively 3.3V, 1.0V, 1.2V and 1.5V；The output voltage of the TPS51100 chip is 0.75V.
8. a kind of generation method of vision signal generating means according to claim 1, it is characterised in that: will need to be shown
Video content and control command are transmitted to FPGA by the PCIe interface of PCIe communication module, and FPGA main control module is to video content
Image modulation processing is carried out to the image in video content according to control command by FPGA after being cached, then is passed through
CameraLink coding module exports after carrying out serial process.
9. the generation method of vision signal generating means according to claim 8, it is characterised in that: described image modulation treatment
It is arranged including image scaling, DDR caching, image sharpening, color space conversion, image superposition, frame frequency conversion and resolution ratio.
10. the generation method of vision signal generating means according to claim 9, it is characterised in that: the serial process out
For 28 bit parallel data signals are converted to LVDS differential signal.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811612805.6A CN109413339A (en) | 2018-12-27 | 2018-12-27 | A kind of vision signal generating means and method |
| PCT/CN2019/113897 WO2020134502A1 (en) | 2018-12-27 | 2019-10-29 | Video signal generation apparatus and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811612805.6A CN109413339A (en) | 2018-12-27 | 2018-12-27 | A kind of vision signal generating means and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109413339A true CN109413339A (en) | 2019-03-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201811612805.6A Withdrawn CN109413339A (en) | 2018-12-27 | 2018-12-27 | A kind of vision signal generating means and method |
Country Status (2)
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| CN (1) | CN109413339A (en) |
| WO (1) | WO2020134502A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020134502A1 (en) * | 2018-12-27 | 2020-07-02 | 西安奇维科技有限公司 | Video signal generation apparatus and method |
| CN112449139A (en) * | 2020-11-12 | 2021-03-05 | 北京环境特性研究所 | Video processing and video signal analog simulation output system and method |
| CN112653860A (en) * | 2021-01-05 | 2021-04-13 | 苏州羿景睿图信息科技有限公司 | Camera Link signal source data processing method based on HDMI interface |
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- 2018-12-27 CN CN201811612805.6A patent/CN109413339A/en not_active Withdrawn
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2019
- 2019-10-29 WO PCT/CN2019/113897 patent/WO2020134502A1/en active Application Filing
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| CN105187765A (en) * | 2015-07-21 | 2015-12-23 | 中国科学院西安光学精密机械研究所 | Embedded multifunctional video interface module |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020134502A1 (en) * | 2018-12-27 | 2020-07-02 | 西安奇维科技有限公司 | Video signal generation apparatus and method |
| CN112449139A (en) * | 2020-11-12 | 2021-03-05 | 北京环境特性研究所 | Video processing and video signal analog simulation output system and method |
| CN112653860A (en) * | 2021-01-05 | 2021-04-13 | 苏州羿景睿图信息科技有限公司 | Camera Link signal source data processing method based on HDMI interface |
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| Publication number | Publication date |
|---|---|
| WO2020134502A1 (en) | 2020-07-02 |
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Application publication date: 20190301 |