CN109412732A - A kind of control method and device of receiving end delay jitter - Google Patents
A kind of control method and device of receiving end delay jitter Download PDFInfo
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- CN109412732A CN109412732A CN201710701927.1A CN201710701927A CN109412732A CN 109412732 A CN109412732 A CN 109412732A CN 201710701927 A CN201710701927 A CN 201710701927A CN 109412732 A CN109412732 A CN 109412732A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J14/00—Optical multiplex systems
- H04J14/02—Wavelength-division multiplex systems
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/14—Monitoring arrangements
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Abstract
The invention discloses a kind of control method and device of receiving end delay jitter, including the first pulse signal of point generation on the basis of on the water level line of the First Input First Output of receiving end a bit；Generate the second pulse signal of Fractional-N frequency signal of the first pulse signal；When the first pulse signal every time arrives and framing is successful, the memory value backed up and First Input First Output water level line will be needed to store into the first register group；When interval and the framing success of the second pulse signal, the value in the first register group is stored into the second register group；When occurring losing frame, keep the water level line of the first register group, the second register group and First Input First Output constant；When the first pulse signal after framing success arrives, restore the memory value of backup and the water level line of First Input First Output.By the present invention in that ensure that the stability of receiving end data traffic with two groups of register group backup storage memory values and First Input First Output water level line, being reduced delay jitter.
Description
Technical field
The present invention relates to field of communication technology more particularly to a kind of control method and device of receiving end delay jitter.
Background technique
The rapid growth of data service in recent years to transmission network more stringent requirements are proposed: large capacity, low cost, quickly
Flexible traffic scheduling, extended capability be strong and high reliability.Currently, the following rank of the development experience of optical fiber transmission network
Section: space division multiplexing (Space Division Multiplexing, SDM) stage, time division multiplexing (Time Division
Multiplex, TDM) stage and wavelength-division multiplex (Wavelength Division Multiplexing, WDM) stage, currently make
Fibre-optic transmission system (FOTS) is mainly based on wavelength-division multiplex system.With the continuous development of the communication technology, current commercial 40G
(Gigabit) wavelength-division transmission gradually evolves to the transmission rate of the even higher rate of 100G, 400G, at the same time, data transmission
Distance also constantly expanding.
But with the expansion of the raising of transmission rate and transmission range, influence of the delay jitter to optic communication quality is got over
Come more very important.In optical transfer network (Optical Transport Network, OTN) system, transmission link and receives link
In delay jitter will cause the transmission impairment of data-signal, have a negative impact to the reliability and performance of whole system.Mesh
Digital Signal Processing (Digital Signal Processing, the DSP) chip of preceding industry mainstream to this without special processing,
In 100G/400G long away from transmission services, 100G/400G express traffic and 100G/400G loopback business, the reliability of system and
Performance will receive influence；For there is the business of particular/special requirement to latency requirement, such as 100GE (Gigabit Ethernet)/
400GE business, then be unable to satisfy demand, so that the usage scenario of 100G/400G dsp chip greatly reduces.
Summary of the invention
In order to solve the above-mentioned technical problems, the present invention provides a kind of control method and device of receiving end delay jitter,
It can reduce the delay jitter of receiving end link.
In order to reach the object of the invention, the technical solution of the embodiment of the present invention is achieved in that
The embodiment of the invention provides a kind of control methods of receiving end delay jitter, comprising:
By on the water level line of the First Input First Output of receiving end a little on the basis of point generate the first pulse signal, described the
The period of the water level line in the period and First Input First Output of one pulse signal is identical；Generate the second pulse signal, second arteries and veins
The Fractional-N frequency signal that signal is the first pulse signal is rushed, N is the clock cycle needed for judging data exception more than or equal to receiving end
Several natural numbers；
When the first pulse signal every time or the second pulse signal arrive and framing is successful, need that backs up to deposit receiving end
The water level line of reservoir value and First Input First Output is stored into the first register group；Every the interval of the second pulse signal and fixed
When frame success, the value in the first register group is stored into the second register group；
When receiving end occurs losing frame, the water of the first register group, the second register group and First Input First Output is kept
Bit line is constant；
When the first pulse signal after framing success arrives, connect according to the register value recovery of the second register group storage
The memory value of receiving end backup and the water level line of First Input First Output.
Further, the framing successfully specifically includes: the receiving end carries out frame synchronization inspection to the data frame received
It surveys and judges that the data frame frame synchronization received remains to N1 frame length, wherein the N1 is natural number.
Further, the receiving end appearance is lost frame and specifically included: the receiving end carries out frame to the data frame received
It is synchronous to detect and judge the data frame out of frame that continuous N2 frame receives, wherein the N2 is the natural number greater than 1.
Further, the first pulse signal after the framing success is first described first after framing success
Pulse signal.
Further, the control method further include: according to the data decoding rate of receiving end and the first in, first out team
The ratio for exporting the useful signal in data cached of the First Input First Output is arranged in the reading data rate of column.
The embodiment of the invention also provides a kind of control device of receiving end delay jitter, including First Input First Output, when
Clock tracking module, synchronization module, recovery of stomge module, the first register group and the second register group, in which:
First Input First Output, the data received for caching the receiving end；
Clock tracking module, for by the water level line of the First Input First Output of receiving end a little on the basis of point generate the
One pulse signal, the period of first pulse signal are identical with the period of the water level line of First Input First Output；Generate the second arteries and veins
Signal is rushed, second pulse signal is the Fractional-N frequency signal of the first pulse signal, and N is to judge data more than or equal to receiving end
The natural number of abnormal required clock periodicity；By the first pulse signal and the second output of pulse signal to recovery of stomge module；
Synchronization module is used to analyze the received data frame and carries out Frame Synchronization Test, exports framing pass signal or loses frame signal
To recovery of stomge module；
Recovery of stomge module is used for when the first pulse signal every time or the second pulse signal arrive and framing is successful, will
Receiving end needs the water level line of the memory value and First Input First Output that back up to store into the first register group；Every second
When the interval of pulse signal and framing success, the value in the first register group is stored into the second register group；When losing
When frame, keep the water level line of the first register group, the second register group and First Input First Output constant；After framing success
First pulse signal arrive when, according to the second register group storage register value restore receiving end backup memory value and
The water level line of First Input First Output；
First register group and the second register group are used to storage receiving end and need the memory value backed up and first enter elder generation
The water level line of dequeue.
It further, include: that the recovery of stomge module judgement receives when the framing success of the recovery of stomge module
Data frame frame synchronization remain to N1 frame length, wherein the N1 be natural number.
Further, the recovery of stomge module includes: that the recovery of stomge module judgement is continuous when occurring and losing frame
When the data frame out of frame that N2 frame receives, wherein the N2 is the natural number greater than 1.
Further, the first pulse signal after the framing success of the recovery of stomge module is after the framing is successful
First first pulse signal.
Further, the control device further includes setup module, for according to receiving end data decoding rate and institute
The ratio for exporting the useful signal in data cached of the First Input First Output is arranged in the reading data rate for stating First Input First Output
Example.
Technical solution of the present invention has the following beneficial effects:
The control method and device of receiving end delay jitter provided by the invention are deposited in advance by using two groups of register groups
Storage needs the water level line of memory value and First Input First Output backed up, when occurring losing frame, keep two groups of register values and
The water level line of First Input First Output is constant, and the benchmark point moment after framing success restores the memory value of backup and first enters elder generation
The water level line of dequeue, so that data traffic has been restored to the shape of the last normal work when receiving end link is abnormal
State ensure that the stability of data traffic, reduce delay jitter；
Further, by the ratio for exporting the useful signal in data cached of setting First Input First Output, reduce
Influence of the subsystem of data traffic larger fluctuation to subsequent subsystem ensure that the enabled uniformity of data, expand data
The application scenarios of transmission.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present invention, constitutes part of this application, this hair
Bright illustrative embodiments and their description are used to explain the present invention, and are not constituted improper limitations of the present invention.In the accompanying drawings:
Fig. 1 is a kind of flow diagram of the control method of receiving end delay jitter of the embodiment of the present invention；
Fig. 2 is the water level week of the First Input First Output (First In First Out, FIFO) of receiving end in the related technology
Phase fluctuates schematic diagram；
Fig. 3 is a kind of structural schematic diagram of the control device of receiving end delay jitter of the embodiment of the present invention；
Fig. 4 is the link structure schematic diagram of the receiving end of the preferred embodiment of the present invention；
Fig. 5 is the time sequence control logic signal of the first register group and the second register group of the preferred embodiment of the present invention
Figure；
Fig. 6 is the state machine architecture schematic diagram of the clock tracking module of the preferred embodiment of the present invention；
Fig. 7 is the structural schematic diagram of the setup module of the preferred embodiment of the present invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention
Embodiment be described in detail.It should be noted that in the absence of conflict, in the embodiment and embodiment in the application
Feature can mutual any combination.
As shown in Figure 1, a kind of control method of receiving end delay jitter according to the present invention, includes the following steps:
Step 101: point generates the first pulse letter on the basis of any on the water level line of the First Input First Output of receiving end
Number, the period of first pulse signal is identical with the period of the water level line of First Input First Output；Generate the second pulse signal, institute
The Fractional-N frequency signal that the second pulse signal is the first pulse signal is stated, N is to judge needed for data exception more than or equal to receiving end
The natural number of clock periodicity；
It should be noted that receiving end data transmission is transmitted as unit of frame, due to the two sides FIFO clock
Frequency is inconsistent, as shown in Fig. 2, will show the water-level fluctuation of fixed cycle in FIFO.In the period water level wave of FIFO
A datum mark is chosen in dynamic, selections of the datum mark can be chosen in any time in each period, but after selecting, whole
It is no longer changed in a transmission process, i.e. the period of datum mark is identical with the FIFO water-level fluctuation period.
Step 102: when the first pulse signal every time or the second pulse signal arrive and framing is successful, receiving end being needed
The memory value of backup and the water level line of First Input First Output are stored into the first register group；Every the second pulse signal
When interval and framing success, the value in the first register group is stored into the second register group；
Further, the framing success, specifically includes:
The receiving end carries out Frame Synchronization Test to the data frame received and judges that the data frame frame synchronization received is protected
Hold N1 frame length, wherein the N1 is natural number.
Step 103: when receiving end occurs losing frame, keeping the first register group, the second register group and first in, first out
The water level line of queue is constant；
Further, the receiving end appearance is lost frame and is specifically included:
The receiving end carries out Frame Synchronization Test to the data frame received and judges the data frame that continuous N2 frame receives
Out of frame, wherein the N2 is the natural number greater than 1.
Step 104: when the first pulse signal after framing success arrives, according to the register of the second register group storage
Value restores the water level line of memory value and First Input First Output that receiving end needs to back up.
Further, the first pulse signal after the framing success is first described first after framing success
Pulse signal.
Further, the control method further include:
According to the reading data rate of the data decoding rate of receiving end and the First Input First Output, first in, first out team is set
The ratio of useful signal during the output of column is data cached.
As shown in figure 3, a kind of control device of receiving end delay jitter according to the present invention, including First Input First Output,
Clock tracking module, synchronization module, recovery of stomge module, the first register group and the second register group, in which:
First Input First Output, the data received for caching the receiving end；
Clock tracking module, for by the water level line of the First Input First Output of receiving end a little on the basis of point generate the
One pulse signal, the period of first pulse signal are identical with the period of the water level line of First Input First Output；Generate the second arteries and veins
Signal is rushed, second pulse signal is the Fractional-N frequency signal of the first pulse signal, and N is to judge data more than or equal to receiving end
The natural number of abnormal required clock periodicity；By the first pulse signal and the second output of pulse signal to recovery of stomge module；
Synchronization module is used to analyze the received data frame and carries out framing, exports framing pass signal or loses frame signal to storage
Recovery module；
Recovery of stomge module is used for when the first pulse signal every time or the second pulse signal arrive and framing is successful, will
Receiving end needs the water level line of the memory value and First Input First Output that back up to store into the first register group；Every second
When the interval of pulse signal and framing success, the value in the first register group is stored into the second register group；When losing
When frame, keep the water level line of the first register group, the second register group and First Input First Output constant；After framing success
First pulse signal arrive when, according to the second register group storage register value restore receiving end backup memory value and
The water level line of First Input First Output；
First register group and the second register group are used to storage receiving end and need the memory value backed up and first enter elder generation
The water level line of dequeue.
It further, include: that the recovery of stomge module judgement receives when the framing success of the recovery of stomge module
Data frame frame synchronization remain to N1 frame length, wherein the N1 be natural number.
Further, the recovery of stomge module includes: that the recovery of stomge module judgement is continuous when occurring and losing frame
When the data frame out of frame that N2 frame receives, wherein the N2 is the natural number greater than 1.
Further, the first pulse signal after the framing success of the recovery of stomge module is after the framing is successful
First first pulse signal.
Further, the control device further includes setup module, for according to receiving end data decoding rate and institute
The ratio for exporting the useful signal in data cached of First Input First Output is arranged in the reading data rate for stating First Input First Output.
The embodiment of the invention also provides a preferred embodiments, and the present invention is further expalined, but is worth note
Meaning, the preferred embodiment are intended merely to preferably describe the present invention, do not constitute and improperly limit the present invention.
As shown in figure 4, after fiber data enters receiving end link, by eliminating optical fiber bring after data pre-processing subsystem
Some damages, then it is synchronous with data to enter synchronous (SYN) module progress data frame decoding for data；Data after synchronizing are by decoding
Module carries out the decoding of Turbo product code (Turbo Product Code Decoder, TPCD)；Data after decoding enter interface
Conversion and framing module carry out the data framing of interface conversion and another format；Data after framing pass through inner institute (Reed-
Solomon, RS) coding module enters data distribution and scrambling module after carrying out forward error correction channel, then by first entering
First dequeue (First Input First Output, FIFO) passes through serializer/de-serializers (Serializer/ afterwards
Deserializer, SerDes) interface output.
The clock tracking module (Clock and Reset Management module, CRM) during data transmission
By extracting the water level information of FIFO, the speed of data rate is judged after smoothing processing, to control entire data flow
Amount adjusts clock jitter, reduces clock delay.
A kind of control method of receiving end delay jitter according to the present invention, includes the following steps:
Step 401: choosing a datum mark on the output water level line of First Input First Output, generate a pulse signal
The output water level period of pr_start1, period and FIFO are identical；The Fractional-N frequency signal pr_start2 of pr_start1 is generated, it is described
N is the natural number for adding 1 more than or equal to clock periodicity needed for judging data exception；
It should be noted that the benchmark point moment in each period generates a pulse signal pr_start1, it is assumed that judgement
The time of data exception is N.M data period (N is integer part, and M is fractional part), in order not to allow abnormal data to enter
In 2nd register, fractional frequency signal pr_start2, pr_start2 >=pr_start1*N+1 of pr_start1 is generated, i.e., extremely
It is divided less for N+1.
Step 402: at the pr_start1 moment, all register values needed for restoring current state, which are stored to first, to be posted
In storage group；It is successfully out of frame (Out Of Frame, OOF) signal OOF=0 in framing, (OOF signal is that data generation is different
Normal mark) it remains to first pr_start1 moment after N1 frame length and deposits the key state in the first register group
Device value and FIFO water level are loaded into the second register group；
As shown in figure 5, the renewal time interval between the first register group and the second register group is two pr_start2
The distance between, this time interval can ensure that optical conversion element will not be written in data when SYN is abnormal completely
In (Optical Transform Unit, OTU) FIFO.When system worked well, (system needs storage key state register value
Restore all registers needed for current state) and OTU FIFO water level into the first register group.First register
Group and two groups of register groups of the second register group are at shift register, pr_start2&crm_work_en& (OOF==0) connection
To the first register group enable end, wherein pr_start2 be pr_start1 Fractional-N frequency signal, crm_work_en be clock with
The work enable signal of track module, OOF are out of frame signal, and (OOF==0) &flag connects pr_start2&crm_work_en&
It is connected to the second register group enable end, wherein flag signal value are as follows: as pr_start2&crm_work_en& (OOF==0)
When, flag=1；As 00f=1, flag=0, it should be noted that this is sequential logic, is not combinational logic, sequential logic
On have the delay in an enabled period.
Step 403: when each pr_start2 pulse signal arrives and framing is successful, refreshing the value of the first register group；
When pr_start2 pulse interval and framing success, the second register group is refreshed according to the value of the first register group
Value；
Step 404: when continuously there is N2 frame OOF, FIFO water level being maintained；
Step 405: after framing success OOF=0 remains to N1 frame length, first pr_start1 moment according to the
Key state register value and FIFO water level line restoring scene in two register groups.
As shown in fig. 6, clock tracking module does not work when electrifying startup, OTU FIFO keeps half-full, and FIFO does not read not write,
SerDes interface sends pseudo-random binary sequence (Pseudo-Random Binary Sequence, PRBS) data；In synchronization
First pr_start1 moment that module framing success OOF=0 is remained to after N1 frame length loads key state register value
To the second register group, clock recovery and OTU FIFO are worked normally, and SerDes interface sends the data in OTU FIFO at this time；
Pr_start2&crm_work_en& (OOF==0)==1 the first register group of normal refresh and pr_start2&
(OOF==0) &flag==1 the second register group of normal refresh, the data of the second register group are from the to crm_work_en&
The key state register value and FIFO water level for the benchmark point moment that one register group obtains, only continuous refresh just can guarantee
In second register group what the moment stored be all the datum at newest moment under data normal condition key state deposit
Device value and FIFO water level；
Occur maintaining clock tracking module when continuous N2 frame OOF, and FIFO water level Hold is lived, SerDes connects at this time
Mouth sends PRBS, and first pr_start1 moment after synchronization module framing success OOF=0 remains to N1 frame length loads
Second register group, clock recovery and OTU FIFO are worked normally, and SerDes interface sends the data in OTU FIFO at this time.
It should be noted that since definition of each system to data exception is different, such as the system having is to data exception
Being defined as 3 OOF is data exception, and it is data exception that some systems, which are defined as 5 OOF,.N2 herein can match online
It sets, when being interpreted as system N2 OOF of experience, it is believed that the data of system have exception, and starting clock tracking module module is kept
Current state prevents the system in data exception very big by the deviation of abnormal data band.
Further, as shown in fig. 7, the invention also includes setup module, the setup module is located at decoding module and elder generation
Enter between first dequeue, its purpose is to further decrease data delay, improves data and control precision.Number after TPC decoding
It is cached according to by FIFO, the data of caching are uniformly read according to setup module control.Setup module by setting molecule N and
Denominator M, the molecule N are the valid data amount in First Input First Output, and the denominator M is the data cached of First Input First Output
Amount, so that data uniformly export.Such as there are 75 effectively to enable in 100 clock cycle, then enabled number is 25 in vain,
Therefore 75, M can be configured by N is configured to 100.Actually such case N and M is not relatively prime, can continue to be reduced to N=3,
M=4.After the completion of configuration, this module will in output every 3 useful signal heels, one invalid signals, then proceeding to 3 has
Imitate signal, an invalid signals ....For the data of abnormal frame, this module, which is taken, only abandons data, does not add the side of data
Formula.The data of discarding can come out according to the data decoding rate of receiving end and the reading data rate calculation of First Input First Output,
By the discarding data calculated completion by the way of configurable or fixed filling data.Data have number in transmission process
Situations such as according to normal, data exception, data normal again, processing through the invention can make data normally and data are normal again
Between mean water difference only differ several clock cycle.
The control method and device of receiving end delay jitter provided by the invention are deposited in advance by using two groups of register groups
Storage needs the water level line of memory value and First Input First Output backed up, when occurring losing frame, keep two groups of register values and
The water level line of First Input First Output is constant, and the benchmark point moment after framing success restores the memory value of backup and first enters elder generation
The water level line of dequeue, so that data traffic has been restored to the shape of the last normal work when receiving end link is abnormal
State ensure that the stability of data traffic, reduce delay jitter；
Further, by the ratio for exporting the useful signal in data cached of setting First Input First Output, reduce
Influence of the subsystem of data traffic larger fluctuation to subsequent subsystem ensure that the enabled uniformity of data, expand data
The application scenarios of transmission.
Those of ordinary skill in the art will appreciate that all or part of the steps in the above method can be instructed by program
Related hardware is completed, and described program can store in computer readable storage medium, such as read-only memory, disk or CD
Deng.Optionally, one or more integrated circuits also can be used to realize, accordingly in all or part of the steps of above-described embodiment
Ground, each module/unit in above-described embodiment can take the form of hardware realization, can also use the shape of software function module
Formula is realized.The present invention is not limited to the combinations of the hardware and software of any particular form.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of control method of receiving end delay jitter characterized by comprising
Point generates the first pulse signal, first arteries and veins on the basis of any on the water level line of the First Input First Output of receiving end
The period for rushing the period of signal and the water level line of First Input First Output is identical；Generate the second pulse signal, the second pulse letter
Number be the first pulse signal Fractional-N frequency signal, N is clock periodicity needed for judging data exception more than or equal to receiving end
Natural number；
When the first pulse signal every time or the second pulse signal arrive and framing is successful, receiving end is needed to the memory backed up
The water level line of value and First Input First Output is stored into the first register group；Every the second pulse signal interval and framing at
When function, the value in the first register group is stored into the second register group；
When receiving end occurs losing frame, the water level line of the first register group, the second register group and First Input First Output is kept
It is constant；
When the first pulse signal after framing success arrives, receiving end is restored according to the register value of the second register group storage
The memory value of backup and the water level line of First Input First Output.
2. control method according to claim 1, which is characterized in that the framing successfully specifically includes: the receiving end
Frame Synchronization Test is carried out to the data frame received and judges that the data frame frame synchronization received remains to N1 frame length, wherein
The N1 is natural number.
3. control method according to claim 1, which is characterized in that the receiving end mistake frame occurs and specifically includes: described
Receiving end carries out Frame Synchronization Test to the data frame received and judges the data frame out of frame that continuous N2 frame receives, wherein
The N2 is the natural number greater than 1.
4. control method according to claim 1, which is characterized in that the first pulse signal after the framing success is institute
First first pulse signal after stating framing success.
5. control method according to claim 1, which is characterized in that the control method further include: according to receiving end
The reading data rate of data decoding rate and the First Input First Output, the output that the First Input First Output is arranged are data cached
In useful signal ratio.
6. a kind of control device of receiving end delay jitter, which is characterized in that including First Input First Output, clock tracking module,
Synchronization module, recovery of stomge module, the first register group and the second register group, in which:
First Input First Output, the data received for caching the receiving end；
Clock tracking module, for the first arteries and veins of point generation on the basis of any on the water level line of the First Input First Output of receiving end
Signal is rushed, the period of first pulse signal is identical with the period of the water level line of First Input First Output；Generate the second pulse letter
Number, second pulse signal is the Fractional-N frequency signal of the first pulse signal, and N is to judge data exception more than or equal to receiving end
The natural number of required clock periodicity；By the first pulse signal and the second output of pulse signal to recovery of stomge module；
Synchronization module is used to analyze the received data frame and carries out Frame Synchronization Test, exports framing pass signal or loses frame signal to depositing
Store up recovery module；
Recovery of stomge module, for will receive when the first pulse signal every time or the second pulse signal arrive and framing is successful
End needs the water level line of the memory value and First Input First Output that back up to store into the first register group；Every the second pulse
When the interval of signal and framing success, the value in the first register group is stored into the second register group；When occurring losing frame,
Keep the water level line of the first register group, the second register group and First Input First Output constant；First after framing success
When pulse signal arrives, the register value stored according to the second register group restores the memory value of receiving end backup and first enters
The water level line of first dequeue；
First register group and the second register group are used to memory value and first in, first out team that storage receiving end needs to back up
The water level line of column.
7. control device according to claim 6, which is characterized in that wrapped when the framing success of the recovery of stomge module
Include: the data frame frame synchronization that the recovery of stomge module judgement receives remains to N1 frame length, wherein the N1 is nature
Number.
8. control device according to claim 6, which is characterized in that the recovery of stomge module is wrapped when occurring and losing frame
It includes: when the recovery of stomge module judges the data frame out of frame that continuous N2 frame receives, wherein the N2 is oneself greater than 1
So number.
9. control device according to claim 6, which is characterized in that the after the success of the framing of the recovery of stomge module
One pulse signal is first first pulse signal after framing success.
10. control device according to claim 6, which is characterized in that further include setup module, for according to receiving end
The reading data rate of data decoding rate and the First Input First Output, the output that the First Input First Output is arranged are data cached
In useful signal ratio.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710701927.1A CN109412732B (en) | 2017-08-16 | 2017-08-16 | Method and device for controlling delay jitter of receiving end |
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| CN201710701927.1A CN109412732B (en) | 2017-08-16 | 2017-08-16 | Method and device for controlling delay jitter of receiving end |
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