CN109411441A - 电路板以及封装后芯片 - Google Patents
电路板以及封装后芯片 Download PDFInfo
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Abstract
本发明提供一种电路板,其包括彼此相对的一上表面以及一下表面、多个散热接垫以及多个散热导电垫。散热接垫设置在上表面上,用以电连接散热元件,其中散热接垫彼此电性绝缘。散热导电垫设置在下表面上,散热导电垫彼此电性绝缘,且散热导电垫分别电连接散热接垫。
Description
技术领域
本发明系关于一种电路板以及封装后芯片,尤指一种可透过电信号测试散热元件与电路板之间的电连接的电路板以及封装后芯片。
背景技术
随着电子产品的演进与发展,电子产品在现今社会中已成为不可或缺的物品,其中芯片更是广泛应用于电子产品中。在芯片的运作过程中,不可避免的会产生高热而造成芯片温度上升,因此为了避免芯片受到高温而影响其运作,封装后芯片中通常会设置例如散热片。然而,若散热元件的黏着状况不佳,可能会导致所谓的天线效应,也就是说散热元件黏着状况不佳的一端,会接收外界的电磁信号而干扰芯片运作,或是由此端发出电磁信号而影响其他元件。
发明内容
本发明的目的之一在于提供一种电路板与封装后芯片,透过电路板中彼此绝缘的散热走线分别连接多个散热接垫与多个散热导电垫,使具有黏着状况不佳的散热元件的封装后芯片可被找出。
本发明的一实施例提供一种电路板,其包括彼此相对的一上表面以及一下表面、多个散热接垫以及多个散热导电垫。散热接垫设置在上表面上,散热接垫用以电连接散热元件,其中散热接垫彼此电性绝缘。散热导电垫设置在下表面上,散热导电垫彼此电性绝缘,且散热导电垫分别电连接至散热接垫。
本发明的另一实施例提供一种封装后芯片,其包括电路板以及散热元件。散热元件黏着在电路板的散热接垫上,散热元件与散热接垫电连接,且散热接垫透过散热元件彼此电连接。
附图说明
图1绘示本发明一实施例的电路板的剖面示意图。
图2绘示本发明一实施例的封装后芯片的俯视图。
图3绘示封装后芯片沿着图2剖线A-A’的剖面示意图。
图4绘示封装后芯片沿着图2剖线B-B’的剖面示意图。
图5绘示本发明一实施例的散热片的俯视示意图。
符号说明
100 电路板
100a 上表面
100b 下表面
110 电路层
112 绝缘层
200 封装后芯片
210 散热片
210a 遮蔽主体
210b 引脚
212 开口
220 芯片
230 金属线
240 封装胶体
250 锡球
CBP1、CBP2 芯片接垫
HP 散热导电垫
CP1、CP2 芯片导电垫
HBP 散热接垫
TRH 散热走线
TRC1、TRC2 芯片走线
Z 俯视方向
具体实施方式
为使熟悉本发明所属技术领域的普通技术人员能更进一步了解本发明,下文特列举本发明的实施例,并配合所附图式,详细说明本发明的构成内容及所欲达成的功效,本说明书中的各项细节亦可基于不同观点与应用,在不悖离本发明的精神下进行各种修饰与变更。另须注意的是,以下图式均为简化的示意图式,而仅以示意方式说明本发明的基本构想,遂图式中仅显示与本发明有关的元件而非按照实际实施时的元件数目、形状与尺寸绘制,其实际实施时各元件的型态、数量及比例可随需求作变更,且元件布局型态可更为复杂。
图1绘示本发明一实施例的电路板的剖面示意图。如图1所示,本实施例的电路板100包括彼此相对的上表面100a以及下表面100b、一电路层110、设置于电路板100的上表面100a上的多个散热接垫HBP与多个芯片接垫CBP1、CBP2、以及设置于电路板100的下表面100b上的多个散热导电垫HP与多个芯片导电垫CP1、CP2。
电路层110可包括一绝缘层112、多条散热走线TRH以及多条芯片走线TRC1、TRC2。散热走线TRH与芯片走线TRC1、TRC2设置在绝缘层112中,使得各散热走线TRH与芯片走线TRC1、TRC2可透过绝缘层112分隔而使彼此电性绝缘。由于本领域熟知该项技艺者应知散热走线TRH与芯片走线TRC1、TRC2可透过多层绝缘层以及多层导线层形成,并可透过绝缘层的开口将不同导电层的导线进行垂直方向的电连接,因此在此不多赘述。
散热接垫HBP用以电连接散热元件(例如散热片),散热接垫HBP彼此电性绝缘,且各散热接垫HBP均与芯片接垫CBP1、CBP2电性绝缘,亦即在电路板100上尚未设置有电子元件或散热元件的情况下,各散热接垫HBP不与其他散热接垫HBP或任何芯片接垫CBP1、CBP2电连接。散热接垫HBP可分别透过电路层110中的散热走线TRH电连接至散热导电垫HP,亦即在电路板100上未设置有电子元件或散热元件的情况下,一个散热接垫HBP仅透过一条散热走线TRH与一个散热导电垫HP电连接,而不与芯片导电垫CP1、CP2电连接。散热导电垫HP彼此电性绝缘,且各散热导电垫HP均与芯片导电垫CP1、CP2电性绝缘,亦即在电路板100上尚未设置有电子元件或散热元件的情况下,各散热导电垫HP不与其他导电垫HP或任何芯片导电垫CP1、CP2电连接。散热导电垫HP用以电连接至外部的接地端。
芯片接垫CBP1、CBP2用以电连接电子元件(例如芯片)。芯片接垫CBP1可用以电连接至电子元件的接地端,并可透过电路层110中的芯片走线TRC1电连接至至少一芯片导电垫CP1,且不与散热导电垫HP电连接。举例而言,芯片接垫CBP1可电连接至两个芯片导电垫CP1。芯片导电垫CP1用以电连接至外部的接地端。芯片接垫CBP2可用以电连接至电子元件的非接地端(例如:其他电压信号端),并可透过电路层110中的芯片走线TRC2电连接至一芯片导电垫CP2。芯片导电垫CP2用以电连接至外部的非接地端(例如:电压信号)。请注意,芯片接垫CBP1、CBP2与芯片导电垫CP1、CP2之间的电连接方式并不限于此。在其他实施例中,芯片接垫CBP1、CBP2与芯片导电垫CP1、CP2之间的电连接方式可依据需求来设计。
图2绘示本发明一实施例的封装后芯片200的俯视图,图3绘示封装后芯片200沿着图2剖线A-A’的剖面示意图,图4绘示封装后芯片200沿着图2剖线B-B’的剖面示意图。如图2与图3所示,本实施例的封装后芯片200包括电路板100、散热片210、芯片220、金属线230、封装胶体240以及锡球(solderball)250,其中电路板100的结构可参酌上文的说明,不再重复赘述。
散热片210透过黏着剂(例如导电胶)与电路板100的散热接垫HBP电连接。散热片210在电路板100的俯视方向Z上覆盖芯片220,散热片210的上表面暴露出封装胶体240外,藉此可将芯片220在运作时所产生的热量散出。由于散热片210包括导热性佳的导电材料(例如金属),因此散热片210还具有电磁干扰(electromagnetic interference,EMI)防护的效果,可屏蔽芯片220受到外界信号的干扰。
图5绘示本发明一实施例的散热片210的俯视图,散热片210包括4个引脚210b。散热片210的4个引脚210b分别黏着于电路板100上的4个散热接垫HBP上,如图2与图3所示,以使散热片210透过4个散热导电垫HP电连接至接地端。此外,各引脚210b可具有一开口212,藉此可降低引脚210b在经过多次膨胀收缩之后产生断裂的可能性。请注意,本发明中在引脚210b的数量不限于4,在另一实施例中,引脚210b的数量为8,在此情况下,电路板100亦对应具有8个散热接垫HBP与8个散热导电垫HP。请注意,本发明中在引脚210b的数量亦不限于偶数。
芯片220可透过金属线230与电路板100上的芯片接垫CBP电连接。在本实施例中,芯片220的焊垫系藉由打线接合(wire bonding)的方式电连接至芯片接垫CBP1、CBP2,但不以此为限。在变化实施例中,焊垫亦可藉由覆晶技术(flip-chip)或其他方式电连接至芯片接垫CBP1、CBP2。
散热片210内外均设置有封装胶体240,且封装胶体240覆盖芯片220。在另一实施例中,可仅在散热片内设置封装胶体。在另一实施例中,封装后芯片亦可不具有封装胶体。
锡球250分别与散热导电垫HP与芯片导电垫CP1、CP2接合,以提高封装后芯片200与其他电路板接合的成功率。在另一实施例中,封装后芯片亦可不具有锡球。
值得说明的是,在传统的封装后芯片中,连接到散热导电垫的接地走线系互相电连接。在此情况下,即使散热片的引脚与散热接垫间有黏合不佳的情形,散热导电垫亦可透过接地走线与其他散热导电垫电连接,因此无法藉由量测两散热导电垫间的电阻值,来判断散热片的引脚与散热接垫间是否有黏合不佳的情形,以找出具有天线效应的封装后芯片。
然而,于本发明中,散热片210尚未黏着至电路板100的情况下,散热导电垫HP彼此电性绝缘。当散热片210黏着至电路板100后,原本在电路板100中彼此绝缘的散热导电垫HP,可经由各自的散热走线TRH电连接至散热片210,进而透过散热片210彼此电连接。因此,当散热片210的引脚210b与散热接垫HBP之间有黏合不佳的情形时,对应的散热导电垫HP与其他散热导电垫HP之间的电阻值会大幅增加,如此一来,便可藉由量测两散热导电垫HP间的电阻值,来判断散热片的引脚210b与散热接垫HBP间是否有黏合不佳的情形,以找出具有天线效应的封装后芯片。举例来说,当有任两散热导电垫间的电阻值未落在一预定范围内时,便代表散热片的引脚与散热接垫间有黏合不佳的情况,该封装后芯片会有天线效应而应被判定成不良品。
以上所述仅为本发明的实施例,凡依本发明申请权利要求所做的均等变化与修饰,皆应属本发明的涵盖范围。
Claims (12)
1.一种电路板,包括:
彼此相对的一上表面以及一下表面;
多个散热接垫,设置在该上表面上,用以电连接一散热元件,其中该等散热接垫彼此电性绝缘;以及
多个散热导电垫,设置在该下表面上,其中该等散热导电垫彼此电性绝缘,且该等散热导电垫分别电连接至该等散热接垫。
2.如权利要求1所述的电路板,其特征在于,另包括:
一电路层,包括多条散热走线,其中该等散热导电垫分别透过该等散热走线电连接至该等散热接垫,且该等散热走线彼此电性绝缘。
3.如权利要求2所述的电路板,其特征在于,另包括:
多个芯片接垫,设置在该上表面上,用以电连接一电子元件,其中各该散热接垫均与该等芯片接垫电性绝缘。
4.如权利要求3所述的电路板,其特征在于,另包括:
多个芯片导电垫,设置在该下表面上,其中各该散热导电垫均与该等芯片导电垫电性绝缘。
5.如权利要求4所述的电路板,其特征在于,该电路层另包括:
多条芯片走线,其中该等芯片导电垫中的至少一者透过该等芯片走线中至少之一者电连接至该等芯片接垫中的至少一者,且该等散热走线电性绝缘于该等芯片走线。
6.一种封装后芯片,包括:
如权利要求1所述的该电路板;以及
一散热元件,黏着在该电路板的该等散热接垫上,该散热元件与该等散热接垫电连接,且该等散热接垫透过该散热元件彼此电连接。
7.如权利要求6所述的封装后芯片,其特征在于,该电路层另包括:
多条散热走线,其中该等散热导电垫分别透过该等散热走线电连接至该等散热接垫。
8.如权利要求7所述的封装后芯片,其特征在于,另包括:
一电子元件,设置在该电路板与该散热元件之间;
其中该电路板另包括多个芯片接垫,设置在该上表面上,电连接该电子元件,且各该散热接垫均与该等芯片接垫电性绝缘。
9.如权利要求8所述的封装后芯片,其特征在于,该电路板另包括:
多个芯片导电垫,设置在该电路板的该下表面上,且各该散热导电垫均与该等芯片导电垫电性绝缘。
10.如权利要求9所述的封装后芯片,其特征在于,该电路层另包括:
多条芯片走线,其中该等芯片导电垫中的至少一者透过该等芯片走线中至少之一者电连接至该等芯片接垫中的至少一者,且该等散热走线电性绝缘于该等芯片走线。
11.如权利要求6所述的封装后芯片,其特征在于,还包括一封装胶体,设置于该电路板上。
12.如权利要求6所述的封装后芯片,其特征在于,还包括多个锡球,分别与该等散热导电垫接合。
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