CN109411350A - A kind of preparation method of GaN base p-type grid structure - Google Patents
A kind of preparation method of GaN base p-type grid structure Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 29
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 102
- 238000000034 method Methods 0.000 claims abstract description 54
- 238000005530 etching Methods 0.000 claims abstract description 39
- 239000000463 material Substances 0.000 claims abstract description 37
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 32
- 230000008569 process Effects 0.000 claims abstract description 32
- 230000003647 oxidation Effects 0.000 claims abstract description 30
- 238000001312 dry etching Methods 0.000 claims abstract description 27
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 21
- 238000005516 engineering process Methods 0.000 claims abstract description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 20
- 238000001259 photo etching Methods 0.000 claims abstract description 9
- 229910002704 AlGaN Inorganic materials 0.000 claims description 17
- 230000007797 corrosion Effects 0.000 claims description 16
- 238000005260 corrosion Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 16
- 238000001020 plasma etching Methods 0.000 claims description 10
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 claims description 9
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 4
- 229910052594 sapphire Inorganic materials 0.000 claims description 4
- 239000010980 sapphire Substances 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 abstract description 11
- 230000000694 effects Effects 0.000 abstract description 7
- 238000002156 mixing Methods 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000000243 solution Substances 0.000 description 9
- 230000002950 deficient Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000003628 erosive effect Effects 0.000 description 4
- 238000009616 inductively coupled plasma Methods 0.000 description 4
- 239000012670 alkaline solution Substances 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 2
- 125000005842 heteroatom Chemical group 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
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- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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Abstract
The present invention provides a kind of preparation method of GaN base p-type grid structure, and step includes: in gallium nitride-based material surface coating photoresist and photoetching regional graphics to be etched；It uses dry etching using photoresist as exposure mask, etches cap layers of the GaN of exposed region and the p-type grid layer of ~ 90% thickness, remove remaining photoresist；To treated, gallium nitride-based material carries out oxidation processes；Gallium nitride-based material is placed in corrosive solution and is corroded, GaN base p-type grid structure is obtained.This method completes the preparation of GaN base p-type grid structure using dry and wet mixing etching；Wet etching therein solves the problems, such as surface damage caused by dry etching, and self-stopping technology characteristic ensure that the uniformity of etching depth；Wet etching is needed the thickness etched to be obviously reduced by dry etching therein, can be greatly reduced merely using oxidation and etching time needed for wet etching, be not only increased efficiency, further reduce sideetching effect, ensure that process controllability.
Description
Technical field
The present invention relates to the technical field of semiconductors of gallium nitride base (GaN) material and device, and in particular to a kind of GaN base
The preparation method of p-type grid structure.
Background technique
Gallium-nitride-based devices are referred to as the device of material foundation with AlGaN/GaN, InGaN/GaN, InAlGa/GaN etc.,
Such as AlGaN/GaN hetero junction field effect pipe (heterostructure field effect transistors, HFET),
Heterojunction bipolar transistor (heterostructure bipolar transistor, HBT) etc..Gallium-nitride-based devices have
The advantages that breakdown field is powerful, electron mobility is high, saturated velocity is big, it is considered to be the strong competition of next-generation device for power switching
Person favors by researcher in recent years.
However due in above-mentioned material system heterojunction structure have powerful piezoelectricity and spontaneous polarization effect, be based on
The GaN base hetero junction field effect pipe of above-mentioned material system is depletion device, i.e., its threshold voltage is negative.Turn in actual power
It changes in application, enhancement device is more favored, and one side enhancement device can reduce the design complexities of driving circuit；It is another
Aspect, enhancement device can be to avoid the risks of maloperation.Currently, realizing mainly includes fluorine ion in the technology of enhancement device
Injection technique, groove gate technique, p-type gate technique etc..Wherein, p-type gate technique is the most mature, and produces in commercialization GaN at present
Most technologies is used in product.However, the preparation of p-type grid structure at present still using based on inductive coupling (ICP) or react from
The dry etching technology of son etching (RIE), one side dry etching are easy to cause to damage to the surface GaN, and device performance is caused to move back
Change；On the other hand, dry etching etch rate control difficulty is high, etching depth inconsistency is big, to cause in piece/piece between device
The consistency of part characteristic is poor, and then reduces GaN product yield.On the other hand, still not for the wet etch techniques of p-type grid structure
Maturation, meanwhile, wet etching course will inevitably introduce lateral corrosion phenomenon, influence device technology controllability.
Summary of the invention
It is an object of the invention in view of the above-mentioned problems, providing a kind of preparation method of GaN base p-type grid structure, this side
Method is based on customizing GaN epitaxial structure, provides the mixing lithographic technique that a kind of dry and wet combine and completes p-type grid structure
Preparation, the etching of 90% ± 5% thickness of p-type grid layer is completed by dry etching, and the p-type grid layer of residual thickness is complete using wet etching
At, and then complete the preparation of p-type grid structure.
To achieve the above object, the present invention adopts the following technical scheme:
The present invention provides a kind of preparation method of GaN base p-type grid structure, and step includes:
1) photoresist, and photoetching regional graphics to be etched are applied on gallium nitride-based material surface；Gallium nitride-based material is to customize
Epitaxial slice structure, the customization epitaxial slice structure include: 1) epitaxial substrate Substrate from bottom to top；2) high resistant GaN caches
Layer (GaN buffer)；3) GaN channel layer；4) barrier layer；5) GaN cutoff layer；6) p-type grid layer；7) GaN cap (GaN
Cap)；
2) dry etching technology is used, using photoresist as exposure mask, the GaN in the region to be etched on etch nitride gallium based material surface is covered
Cap layers and below the p-type grid layer of corresponding 90% ± 5% thickness, then remove remaining photoresist；
3) oxidation processes, the i.e. p to the residual thickness after over etching are carried out to by step 2 treated gallium nitride-based material
Type grid layer carries out oxidation processes；
4) gallium nitride-based material after oxidation processes is integrally placed in corrosive solution and is corroded, i.e., to the p-type after oxidation
Grid layer carries out corrosion treatment, obtains GaN base p-type grid structure.
Further, the epitaxial substrate includes but is not limited to silicon substrate, Sapphire Substrate, silicon carbide substrates.
Further, the high resistant GaN cache layer includes but is not limited to carbon doping or Fe2O3 doping GaN layer.
Further, the barrier layer includes but is not limited to AlGaN, InAlN, InGaN.
Further, the GaN cutoff layer is GaN material, with a thickness of 2-5nm.
Further, the p-type grid layer includes but is not limited to p-AlGaN, p-InAlN, p-AlN.
Further, the GaN cap is with a thickness of 2-5nm.
Further, the photoresist can be using materials such as AZ5214；The photoetching is using modes such as contact photolithographies.
Further, dry etching technology described in step 2 includes but is not limited to: 1. RIE(reactive ion etching,
Reactive Ion Etching) processing；2. ICP(inductively coupled plasma etching, Inductively coupled
Plasma it) handles.
Further, it is 590 ~ 670 DEG C that step 3), which carries out the temperature of oxidation processes, and the time is 10 ~ 20min；It is preferential to select
Tubular annealing furnace carries out oxidation processes, and atmosphere is oxygen.
Further, the corrosive solution is alkaline solution, such as potassium hydroxide solution or sodium hydroxide solution: its temperature
It is 50 ~ 90 DEG C, etching time is 10min ~ 20min.
Further, oxidation of the oxidizing temperature of the p-type grid layer of remaining 10% ± 5% thickness lower than GaN cutoff layer below
Temperature, under certain oxidizing temperature, only p-type grid layer can be oxidized, and the p-type grid layer after aoxidizing is easy by alkalinity such as KOH
Solution corrosion, while the alkaline solution does not have any influence to GaN cutoff layer, so as to the p of selective corrosion specific region
Type grid layer has self-stopping technology characteristic, to complete the preparation of GaN base p-type grid structure.
It, should will be complete if completing the preparation of p-type grid structure using conventional dry lithographic technique merely, in step 2 by comparing
Portion's (i.e. 100% ± 5%) removes p-type grid layer, but since dry etching depth uneven (100% ± 5%) will cause p-type grid layer
Over etching and deficient etching phenomenon, over etching and deficient etching can all cause the reduction of device two-dimensional electron gas, device property caused to be degenerated；
On the other hand merely institute's etachable material surface will be caused to damage using dry etching, and surface damage can seriously cause device
Dynamic characteristic is degenerated.The p-type grid layer for removing 90% ± 5% thickness in step 2 using dry etching first, due to the p of residual thickness
Type grid layer is removed using self-stopping technology wet etch techniques, be ensure that the uniformity of etching, is avoided and drawn using dry etching merely
Over etching, deficient etching and the surface damage problem risen.
Further, step 3), 4) in only need to complete the removal of remaining p-type grid layer, if rotten using self-stopping technology wet process merely
Erosion technology completes the removal of whole p-type grid layer in step 2, rather than removes the p-type grid layer of 90% ± 5% thickness, due to p-type
Grid layer thickness is larger (usually ~ 100nm), step 3), 4) in when will need using longer oxidization time (> 120min) and corrosion
Between (> 120min) removal of specific region p-type grid layer could be completed, and so prolonged corrosion will greatly increase corrosion process
In sideetching effect, thus greatly reduce process controllability.And dry etching is used to remove 90% first by step 2
The p-type grid layer of ± 5% thickness, step 3), 4) in residual thickness p-type grid layer oxidation and etching time can be controlled in 20min
Within, the sideetching effect in corrosion process is thus greatly reduced, process controllability is increased.
Beneficial effects of the present invention are as follows:
(1) compared to conventional dry lithographic technique is used merely, the present invention is carved using the mixing that dry and wet etching combines
Erosion technology, the wet etching in this method solve the problems, such as surface damage caused by dry etching, on the other hand, due to wet process corruption
Erosion has self-stopping technology characteristic, ensure that the uniformity of etching depth；
(2) compared to simple using traditional self-stopping technology wet etch techniques, the present invention is due to introducing dry etching technology for wet process
Corrosion needs the thickness etched to be contracted to 10% or so, simple using oxidation needed for wet etching and rotten so as to greatly reduce
The time is lost, efficiency is not only increased, it is often more important that the sideetching effect due to caused by wet etching overlong time is reduced,
It ensure that process controllability.
Detailed description of the invention
Fig. 1 is the customization epitaxy of gallium nitride structural schematic diagram in the embodiment of the present invention.
Fig. 2 is GaN base p-type grid structure schematic diagram prepared by the present invention.
If Fig. 3 is merely using over etching caused by dry etching removal p-type grid layer and deficient etching phenomenon schematic diagram.
If Fig. 4 is merely using surface damage phenomenon schematic diagram caused by dry etching removal p-type grid layer.
If Fig. 5 is merely using sideetching phenomenon schematic diagram caused by wet etching removal p-type grid layer.
Fig. 6 is the step flow chart of present invention preparation GaN base p-type grid structure.
Fig. 7 is structure chart after p-AlGaN grid layer dry etching in embodiment, while being also p-AlGaN layers to wet etching
The structure chart in region.
Fig. 8 is the GaN base p-type grid structure figure based on the preparation of p-AlGaN grid layer in embodiment.
Specific embodiment
Below by specific embodiment and cooperate attached drawing, the present invention is described in detail.
A kind of preparation method of GaN base p-type grid structure, as shown in fig. 6, its step includes:
1) photoresist, and photoetching regional graphics to be etched are applied on gallium nitride-based material surface；Gallium nitride-based material is to customize
Epitaxial slice structure, the customization epitaxial slice structure include: from bottom to top epitaxial substrate, channel layer, barrier layer, GaN cutoff layer,
P-type grid layer, GaN cap；
2) as shown in Fig. 2, using dry etching technology, using photoresist as exposure mask, etch nitride gallium based material surface it is to be etched
The GaN cap in region and below the p-type grid layer of corresponding 90% ± 5% thickness, then remove remaining photoresist；
3) oxidation processes, the i.e. p to the residual thickness after over etching are carried out to by step 2 treated gallium nitride-based material
Type grid layer carries out oxidation processes；
4) gallium nitride-based material after oxidation processes is integrally placed in corrosive solution and is corroded, i.e., to the p-type after oxidation
Grid layer carries out corrosion treatment, obtains GaN base p-type grid structure.
Further, the epitaxial substrate includes but is not limited to silicon substrate, Sapphire Substrate, silicon carbide substrates.
Further, the high resistant GaN cache layer includes but is not limited to carbon doping or Fe2O3 doping GaN layer.
Further, the barrier layer includes but is not limited to AlGaN, InAlN, InGaN.
Further, the GaN cutoff layer is GaN material, with a thickness of 2-5nm.
Further, the p-type grid layer includes but is not limited to p-AlGaN, p-InAlN, p-AlN.
Further, the GaN cap is with a thickness of 2-5nm.
Further, the photoresist can be using materials such as AZ5214；The photoetching is using modes such as contact photolithographies.
Further, dry etching technology described in step 2 includes but is not limited to: 1. RIE(reactive ion etching,
Reactive Ion Etching) processing；2. ICP(inductively coupled plasma etching, Inductively coupled
Plasma it) handles.
Further, it is 590 ~ 670 DEG C that step 3), which carries out the temperature of oxidation processes, and the time is 10 ~ 20min；It is preferential to select
Tubular annealing furnace carries out oxidation processes, and atmosphere is oxygen.
Further, the corrosive solution is alkaline solution, such as potassium hydroxide solution or sodium hydroxide solution: its temperature
It is 50 ~ 90 DEG C, etching time is 10min ~ 20min.
Further, oxidation of the oxidizing temperature of the p-type grid layer of remaining 10% ± 5% thickness lower than GaN cutoff layer below
Temperature.
It, will be whole in step 2 if completing the preparation of p-type grid structure using conventional dry lithographic technique merely by comparing
(i.e. 100% ± 5%) removes p-type grid layer, since dry etching depth uneven (100% ± 5%) will cause the over etching of p-type grid layer
Cause device property as shown in figure 3, over etching and deficient etching can all cause the reduction of device two-dimensional electron gas with deficient etching phenomenon
It degenerates；On the other hand merely institute's etachable material surface is caused to damage using dry etching, as shown in figure 4, and surface damage meeting
Seriously the dynamic characteristic of device is caused to be degenerated.Remove the p-type grid layer of 90% ± 5% thickness in step 2 using dry etching first,
Since the p-type grid layer of residual thickness is removed using self-stopping technology wet etch techniques, the uniformity of etching ensure that, avoid simple
Using over etching caused by dry etching, owe etching and surface damage problem.
Further, step 3), 4) in only need to complete the removal of remaining p-type grid layer, if rotten using self-stopping technology wet process merely
Erosion technology completes the removal of whole p-type grid layer in step 2, rather than removes the p-type grid layer of 90% ± 5% thickness, due to p-type
Grid layer thickness is larger (usually ~ 100nm), step 3), 4) in when will need using longer oxidization time (> 120min) and corrosion
Between (> 120min) removal of specific region p-type grid layer could be completed, and so prolonged corrosion will greatly increase corrosion process
In sideetching effect, as shown in figure 5, thus greatly reducing process controllability.And dry method is used by step 2 first
Etching removal 90% ± 5% thickness p-type grid layer, step 3), 4) in residual thickness p-type grid layer oxidation and etching time
Control thus greatly reduces the sideetching effect in corrosion process, increases process controllability within 20min.
Below by taking GaN cap/p-AlGaN/GaN/AlGaN/GaN/Sapphire material as an example, this method is carried out specific
Explanation.The step of self-stopping technology etching technics includes:
1) photoresist, and the figure of photoetching etch areas to be done are applied in GaN base material surface.
The domain that the present embodiment uses is etching domain, and the photoresist of use is AZ5214；Using contact photolithography method
Carry out photoetching.
2) the GaN cap of etch areas to be done and the p-AlGaN layer of ~ 90% thickness are removed.
The purpose of the step is to get rid of etched portions GaN cap to be done and p-AlGaN layers, is aoxidized convenient for subsequent reduction
And etching time, rather than the GaN cap of etch areas will not be etched away due to there is the protection of photoresist.The step uses
RIE(reactive ion etching) method performs etching.
3) remaining photoresist is removed.Photoresist is removed using the method for organic washing, solvent is that acetone, isopropanol etc. are organic
Solvent.
As shown in Figure 7.
4) gallium nitride-based material obtained by step 3) is put in the quick anneal oven under purity oxygen environment and carries out oxidation processes.
Step 1) -3) purpose be print oxidation before, by do not need oxidation region protected with cap layers of GaN,
The region needed to be oxidized exposes, and is aoxidized in this step.The temperature of oxidation is set as 645 DEG C, time 15min.
5) gallium nitride-based material after oxidation processes is soaked in potassium hydroxide solution to corrode, time 15min.
In step 5), the constant temperature of potassium hydroxide solution is 70 DEG C, and etching time is 15 min.
Fig. 8 is the structure chart of the GaN base p-type grid structure based on the preparation of p-AlGaN material.
P-type grid layer uses p-AlGaN material in above-described embodiment, can also use p-InAlN, p- in other embodiments
The materials such as AlN.
In above-described embodiment, when carrying out oxidation processes by tubular annealing furnace, temperature can be adjusted within the scope of 590 ~ 670 DEG C
Whole, the time is 10min ~ 20min.
In above-described embodiment, when being corroded by potassium hydroxide solution, temperature can adjust within the scope of 50 ~ 90 DEG C, the time
For 10 ~ 20min.
The above embodiments are merely illustrative of the technical solutions of the present invention rather than is limited, the ordinary skill of this field
Personnel can be with modification or equivalent replacement of the technical solution of the present invention are made, without departing from the spirit and scope of the present invention, this
The protection scope of invention should subject to the claims.
Claims (12)
1. a kind of preparation method of GaN base p-type grid structure, step include:
1) photoresist, and photoetching regional graphics to be etched are applied on gallium nitride-based material surface；Gallium nitride-based material is to customize
Epitaxial slice structure, the customization epitaxial slice structure include: from bottom to top epitaxial substrate, high resistant GaN cache layer, GaN channel layer,
Barrier layer, GaN cutoff layer, p-type grid layer, GaN cap；
2) dry etching technology is used, using photoresist as exposure mask, the GaN in the region to be etched on etch nitride gallium based material surface is covered
Cap layers and below the p-type grid layer of corresponding 90% ± 5% thickness, then remove remaining photoresist；
3) oxidation processes, the i.e. p to the residual thickness after over etching are carried out to by step 2 treated gallium nitride-based material
Type grid layer carries out oxidation processes；
4) gallium nitride-based material after oxidation processes is integrally placed in corrosive solution and is corroded, i.e., to the p-type after oxidation
Grid layer carries out corrosion treatment, obtains GaN base p-type grid structure.
2. the preparation method of GaN base p-type grid structure as described in claim 1, which is characterized in that the epitaxial substrate is used in
Silicon substrate, Sapphire Substrate, any one in silicon carbide substrates.
3. the preparation method of GaN base p-type grid structure as described in claim 1, which is characterized in that the high resistant GaN cache layer
Using carbon doping or Fe2O3 doping GaN layer.
4. the preparation method of GaN base p-type grid structure as described in claim 1, which is characterized in that the barrier layer uses
Any one in AlGaN, InAlN, InGaN.
5. the preparation method of GaN base p-type grid structure as described in claim 1, which is characterized in that the GaN cutoff layer is GaN
Material, with a thickness of 2-5nm.
6. the preparation method of GaN base p-type grid structure as described in claim 1, which is characterized in that the p-type grid layer uses p-
Any one in AlGaN, p-InAlN, p-AlN.
7. the preparation method of GaN base p-type grid structure as described in claim 1, which is characterized in that the thickness of the GaN cap
Degree is 2-5nm.
8. the preparation method of GaN base p-type grid structure as described in claim 1, which is characterized in that photoresist described in step 1)
Using AZ5214 material；The photoetching uses contact photolithography.
9. the preparation method of GaN base p-type grid structure as described in claim 1, which is characterized in that remove most surface in step 2
GaN cap and p-type grid layer lithographic method using RIE handle or ICP processing.
10. the preparation method of GaN base p-type grid structure as described in claim 1, which is characterized in that aoxidized in step 3)
The temperature of processing is 590-670 DEG C, time 10min-20min.
11. the preparation method of GaN base p-type grid structure as described in claim 1, which is characterized in that select tubular type in step 3)
Annealing furnace carries out oxidation processes, and atmosphere is oxygen.
12. the preparation method of GaN base p-type grid structure as described in claim 1, which is characterized in that corruption described in step 4)
Corrosion solution is potassium hydroxide solution or sodium hydroxide solution, etching time 10-20min.
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