CN109390307A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
CN109390307A
CN109390307A CN201711192001.0A CN201711192001A CN109390307A CN 109390307 A CN109390307 A CN 109390307A CN 201711192001 A CN201711192001 A CN 201711192001A CN 109390307 A CN109390307 A CN 109390307A
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China
Prior art keywords
substrate
electric conductor
passivation layer
semiconductor device
edge
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Granted
Application number
CN201711192001.0A
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Chinese (zh)
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CN109390307B (en
Inventor
林俊成
郑礼辉
蔡柏豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN109390307A publication Critical patent/CN109390307A/en
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Publication of CN109390307B publication Critical patent/CN109390307B/en
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

This exposure is about semiconductor device and its manufacturing method.Some embodiments of the present invention disclose a kind of semiconductor device, and it includes substrate, electric conductor and passivation layers.Each of described electric conductor includes the first part across the substrate, and positioned at the substrate surface and be connected to the second part of the first part.The passivation layer is located at the surface of the substrate, wherein the passivation layer partly covers the edge of the second part of each of described electric conductor.

Description

Semiconductor device and its manufacturing method
Technical field
This exposure is about semiconductor device and its manufacturing method.
Background technique
In the encapsulation of integrated circuit, semiconductor bare chip can be stacked by engagement, and engageable to other encapsulation Component, such as intermediary layer and package substrate.Gained encapsulation is known as three dimensional integrated circuits (3DIC).However, wafer breakage and stress Problem is the challenge in 3DIC.
Summary of the invention
One embodiment of the present of invention is about a kind of semiconductor device comprising: substrate, it includes first surfaces；It is more A first electric conductor, wherein each of the multiple first electric conductor includes first part and the position across the substrate Above the first surface of the substrate and it is connected to the second part of the first part；And passivation layer, it is located at institute Above the first surface for stating substrate, wherein the passivation layer partly covers each of the multiple first electric conductor The second part edge.
Another embodiment of the invention is about a kind of semiconductor device comprising: substrate, it includes first surfaces； Electric conductor is located above the first surface of the substrate；And passivation layer, it is located at the first surface of the substrate Top wherein the passivation layer includes the first part with the EDGE CONTACT of the electric conductor, and is connected to the first part And the second part with the spaced from edges of the electric conductor, and the first part of the passivation layer has bending table Face.
Another embodiment of the invention is about a kind of method for manufacturing semiconductor device comprising: receive substrate；? The surface of the substrate forms electric conductor；It selectively applies in the surface of the substrate with light curable material Material；And the light curable material is irradiated to form passivation layer in the surface of the substrate, wherein described Passivation layer partly covers the edge of the electric conductor.
Detailed description of the invention
Aspect according to the embodiment described in detail below that this exposure is best understood read together with attached drawing.It should infuse Meaning, according to the standard practices in industry, various structures are not necessarily drawn to scale.In fact, for the sake of discussing clearly, it can be arbitrarily Increased or decrease the size of various structures.
Fig. 1 is the side of the manufacture semiconductor device for the various aspects for illustrating one or more embodiments according to this exposure The flow chart of method.
Fig. 2A, Fig. 2 B, Fig. 2 C, Fig. 2 D, Fig. 2 E, Fig. 2 F and Fig. 2 G are the manufactures according to one or more embodiments of this exposure The schematic diagram at one of the various operations of semiconductor device place.
Fig. 3 A and Fig. 3 B are the schematic diagrames according to the semiconductor device of one or more embodiments of this exposure.
Fig. 4 A and Fig. 4 B are the schematic diagrames according to the semiconductor device of one or more embodiments of this exposure.
Fig. 5 A, Fig. 5 B, Fig. 5 C and Fig. 5 D are according to each of the manufacture semiconductor devices of one or more embodiments of this exposure The schematic diagram at one of kind operation place.
Fig. 6 A, Fig. 6 B and Fig. 6 C are the various operations according to the manufacture semiconductor device of one or more embodiments of this exposure One of place schematic diagram.
Fig. 7 A and Fig. 7 B are the schematic diagrames according to the semiconductor device of one or more embodiments of this exposure.
Fig. 8 A and Fig. 8 B are the schematic diagrames according to the semiconductor device of one or more embodiments of this exposure.
Specific embodiment
It discloses below and many different embodiments or examples of the different component for implementing provided subject matter is provided.Hereafter The particular instance of element and arrangement is described to simplify this exposure embodiment.Certainly, these are only example and are not intended to be limitation Property.For example, it may include wherein that first component is formed above second component or on the second component in the de-scription Embodiment that one component and second component are directly contact formed and also may include that wherein additional member can be formed in first component The embodiment that be not directly contacted with first component and second component can.In addition, this exposure embodiment can Repeated reference number and/or letter in various examples.This repeat be for simple and clear purpose and not essentially indicate that Relationship between discussed various embodiments and/or configuration.
In addition, can herein for be easy to describe and use space relative terms (such as " lower section ", " following ", " lower part ", " above ", " top ", "upper" etc.) relationship of an element or component and another element or component described, such as institute in each figure It illustrates.The spatially relative term intend to include device in use or operation in addition to describing in figure and orienting It is differently directed.Equipment can be oriented in other ways and (be rotated by 90 ° or with other orientations) and therefore can similarly understand institute herein The space used is opposite to describe language.
As used herein, for example, the terms such as " first ", " second " and " third " describe various elements, component, region, Layer and/or section, these elements, component, region, layer and/or section should not be limited by these terms.These terms can be only used for One element, component, region, layer or section are distinguished with another element, component, region, layer or section.Such as " the One ", the terms such as " second " and " third " when in this article and do not imply that sequence or order, unless context is explicitly indicated.
As used herein, term " about ", " generally ", " essence " and " about " by describe and based on and small change Change.When binding events or situation in use, the term can refer to the example that wherein event or situation accurately occur and The wherein event or the close example approximatively occurred of situation.For example, when in conjunction with numerical value in use, the term can refer to Less than or equal to that numerical value ± 10% (e.g., less than or equal to ± 5%, be less than or equal to ± 4%, be less than or equal to ± 3%, it is less than or equal to ± 2%, is less than or equal to ± 1%, is less than or equal to ± 0.5%, is less than or equal to ± 0.1% or small In or be equal to ± 0.05%) variation range.For example, if the difference between two values is less than or equal to the flat of described value Mean value ± 10% (e.g., less than or equal to ± 5%, be less than or equal to ± 4%, be less than or equal to ± 3%, be less than or equal to ± 2%, be less than or equal to ± 1%, be less than or equal to ± 0.5%, be less than or equal to ± 0.1% or be less than or equal to ± 0.05%), then described value can be considered as " generally " identical or equal.For example, it " generally " can refer in parallel opposite In 0 ° be less than or equal to ± 10 ° (e.g., less than or equal to ± 5 °, be less than or equal to ± 4 °, be less than or equal to ± 3 °, be less than or Equal to ± 2 °, be less than or equal to ± 1 °, be less than or equal to ± 0.5 °, be less than or equal to ± 0.1 ° or be less than or equal to ± 0.05 °) angle change range.For example, " generally " vertically can refer to relative to 90 ° be less than or equal to ± 10 ° (such as Less than or equal to ± 5 °, be less than or equal to ± 4 °, be less than or equal to ± 3 °, be less than or equal to ± 2 °, be less than or equal to ± 1 °, it is small In or be equal to ± 0.5 °, be less than or equal to ± 0.1 ° or be less than or equal to ± 0.05 °) angle change range.
It also may include other components and process.It for example, may include test structure to help to 3D encapsulation or 3DIC dress Set carry out validation test.For example, test structure may include the testing cushion being formed in redistribution layer or on substrate, the substrate Allow to encapsulate 3D or the test of 3DIC, using etc. to probe and/or probe card.It can be to intermediate structure and final structure Execute validation test.In addition, structure disclosed herein and method are in combination with the middle verification being incorporated to known good bare die With increase qualification rate and reduce the test method of cost come using.
In some embodiments of this exposure, a kind of semiconductor device is provided, the semiconductor device includes covering substrate Surface and the edge of fenced electric conductor passivation layer.The passivation layer helps to enhance the robustness of electric conductor, and mitigates substrate Stress between electric conductor is to reduce the risk of rupture.
Fig. 1 is the side according to the manufacture semiconductor device of the diagram illustrating various aspects of one or more embodiments of this exposure The flow chart of method.Method 100 is started with operating 110, in operation 110, receives substrate.Method is continued with operating 120, It is rectangular at electric conductor on a surface of the substrate in operation 120.Method is continued with operating 130, in operation 130, in substrate Surface selectively apply with light curable material.Method is to operate 140 continuation, in operation 140, to light curable material Material is irradiated with rectangular at passivation layer on a surface of the substrate, and wherein passivation layer partly covers the edge of electric conductor.
Method 100 is only example, and is not intended to limit this exposures embodiment and exceeds in claims and be expressly recited Content.Can before method 100, during and after operation bidirectional is provided, and can for method Additional examples of composition and replace, Eliminate or move back and forth described some operations.
Fig. 2A, Fig. 2 B, Fig. 2 C, Fig. 2 D, Fig. 2 E, Fig. 2 F and Fig. 2 G are the manufactures according to one or more embodiments of this exposure The schematic diagram at one of the various operations of semiconductor device place, wherein Fig. 2A, Fig. 2 B, Fig. 2 C, Fig. 2 D, Fig. 2 E and Fig. 2 F are to show Meaning property part is through amplifying cross-sectional view, and Fig. 2 G is schematic cross section.It should be noted that the method for some embodiments can be chip Level approach.If described in Fig. 2A, substrate 10 is received.In some embodiments, substrate 10 may include chip, semiconductor lining Bottom, intermediary layer, package substrate etc..Substrate 10 includes a surface (for example, first surface 10A) and another surface (for example, with the One surface 10A opposite second surface 10B).In some embodiments, substrate 10 includes one or more through-holes for penetrating substrate 10 10H.In some embodiments, through-hole 10H can be formed from the first surface 10A of substrate 10.In some embodiments, through-hole 10H It can be formed from the second surface 10B of substrate 10.In some embodiments, through-hole 10H can be formed by following operation: make substrate One of 10 first surface 10A or second surface 10B are recessed without penetrating substrate 10, and then from first surface 10A or The other of second surface 10B is by 10 thinning of substrate.In some embodiments, substrate 10 is that have in micron-sized thickness Thin substrate.In some embodiments, the thickness of substrate 10 generally in the range of from about 5 microns to about 15 micron (such as About 10 microns), but not limited to this.In some embodiments, through-hole 10H can by isotropic etching, anisotropic etching, its Combination or it is other it is suitable operation and formed.In some embodiments, the side wall of through-hole 10H can be essentially perpendicular to first surface 10A or second surface 10B.In some embodiments, the side wall of through-hole 10H can be relative to first surface 10A or second surface 10B And it tilts.In some embodiments, close to the size of the through-hole 10H of second surface 10B than leading to close to first surface 10A The size of hole 10H is big.In some embodiments, close to the size ratio of the through-hole 10H of first surface 10A close to second surface The size of the through-hole 10H of 10B is big.
As depicted in fig. 2b, one or more electric conductors are formed above the first surface 10A of substrate 10 (for example, first Electric conductor 20).In some embodiments, the first electric conductor 20 may include, but are not limited to conductive bump, such as control collapsed chip Connect convex block (C4 convex block) etc..In some embodiments, the first electric conductor 20 may include first part 21 and be connected to first The second part 22 of part 21.In some embodiments, first part 21 is generally formed in through-hole 10H, and second part 22 are formed in above the first surface 10A of substrate 10 and outside through-hole 10H.First electric conductor 20 may include such as metal or alloy Equal conductive materials, but it is not limited to it.In some embodiments, the material of the first electric conductor 20 may include, but are not limited to copper, its conjunction Gold etc..First electric conductor 20 can be formed by plating, deposition or other suitable operations.In some embodiments, the first electricity The first part 21 of conductor 20 and second part 22 can be formed from the same material, but not limited to this.In some embodiments, first The first part 21 of electric conductor 20 and second part 22 can be separately formed.In some embodiments, first part 21 can be from lining The second surface 10B at bottom 10 is formed in through-hole 10H, and second part 22 can be formed in substrate after forming first part 21 Above 10 first surface 10A.In some embodiments, the first part 21 of the first electric conductor 20 and second part 22 can be from linings The first surface 10A at bottom 10 is formed.In some embodiments, the first part 21 of the first electric conductor 20 includes the first width W1, And first the second part 22 of electric conductor 20 include the second width W2 than the first width W1 wide.In some embodiments, second The height Ha of part 22 is greater than the height of first part 21, but not limited to this.Pass through way of example, the height Ha of second part 22 Generally in the range of from about 10 microns to about 50 micron, and the height Hb of first part 21 is generally between micro- from about 5 In the range of rice arrives about 20 microns (for example, about 10 microns), but not limited to this.
In some embodiments, conductive bump 26 can be formed in 22 top of second part of the first electric conductor 20.Conductive stud Block 26 can be configured to be electrically connected to package substrate or other electronic devices.In some embodiments, conductive bump 26 is by having Conductive material than the low-melting fusing point of the first electric conductor 20 is formed.In some embodiments, the material of conductive bump 26 can Including but not limited to tin (Sn), its alloy etc..
In some embodiments, passivation layer is formed above the first surface 10A of substrate 10.In some embodiments, blunt Changing layer can be formed by operation illustrated in Fig. 2 C and Fig. 2 D, but not limited to this.As depicted in fig. 2c, in substrate It selectively applies above 10 first surface 10A with light curable material 27.In some embodiments, light curable material 27 is wrapped Containing the polymeric material with light sensitive characteristic.In some embodiments, the polymeric material for light curable material 27 may include but It is not limited to epoxy resin, acrylic resin, polyimides (PI), polybenzoxazole (PBO) etc..In some embodiments, can lead to It crosses printing etc. and passes through nozzle 28 and selectively apply with light curable material 27.In some embodiments, light curable material 27 applied with while irradiated by light beam 29 (such as UV beam or other magnetic waves).In some embodiments, help is irradiated Reduce the mobility of light curable material 27 and solidifies light curable material 27.
As described in Fig. 2 D, passivation layer 30 can be formed in above the first surface 10A of substrate 10, thus in light curable Material 27 is cured and partly covers after solidifying the edge of the first electric conductor 20.In some embodiments, passivation layer 30 Divide the edge 22E of the second part 22 of the first electric conductor 20 of ground covering.In some embodiments, passivation layer 30 is not placed in Between the side wall of the edge 21E and through-hole 10H of the first part 21 of one electric conductor 20.In some embodiments, passivation layer 30 wraps Containing the first part 31 contacted with the edge 22E of the second part 22 of the first electric conductor 20, and the edge 22E with second part 22 The second part 32 separated, the second part 32 cover the first surface 10A of substrate 10 and are connected to first part 31.One In a little embodiments, the first part 31 of passivation layer 30 at least partly covers edge 22E and partially exposed first electric conductor 20 Second part 22 edge 22E.In some embodiments, the first part 31 of passivation layer 30 may include surrounding second part 22 Edge 22E circle shape (that is, annular) structure, and second part 32 is connected to first part 31 and covers the first table of substrate 10 Face 10A.In some embodiments, second part of the first height H1 of the first part 31 of passivation layer 30 than the first electric conductor 20 22 height Ha is low, as shown in Fig. 2 D.In some alternative embodiments, the first height of the first part 31 of passivation layer 30 H1 can be essentially equal to the height Ha of the second part 22 of the first electric conductor 20, as shown in Fig. 2 E.In some embodiments, The half that first height H1 of first part 31 is about the height Ha of second part 22 or the height Ha less than second part 22 Half, but not limited to this.In some embodiments, of the first height H1 of the first part 31 of passivation layer 30 than passivation layer 30 Second height H2 of two parts 32 is big.In some embodiments, the ratio of the first height H1 and the second height H2 are greater than 1 and substantially It goes up and is less than about 15, is substantially greater than about 1.5 and is generally less than about 15, or substantially greater than about 1.5 and be generally less than about 8, But not limited to this.In some embodiments, the first height H1 of first part 31 is generally between from about 5 microns to about 50 micron In the range of, generally in the range of from about 5 microns to about 40 micron or generally between from about 5 microns to about 30 micron In the range of, but not limited to this.In some embodiments, the second height H2 of second part 32 is generally between from about 2 microns To in the range of about 15 microns, but not limited to this.
In some embodiments, for example in the case where substrate 10 is relatively thin, the second part 32 of passivation layer 30 is helped Help protection substrate 10 from rupture.In some embodiments, the first part 31 with high height H1 of passivation layer 30 helps Enhance the robustness of the first electric conductor 20, and helps to mitigate the stress between substrate 10 and the first electric conductor 20.
In some embodiments, the material of light curable material 27 is hydrophilic, this is helped due to capillarity Light curable material 27 covers the edge 22E of the second part 22 of the first electric conductor 20.In this case, additional light can be not necessarily to Being formed in the case where carving operation has differently contoured passivation layer 30.In some embodiments, light curable material 27 can be through selecting It applies to selecting property with to avoid the residue on the first electric conductor 20, and can omit additionally except Slag treatment is (such as at plasma Reason).In some embodiments, the first part 31 of passivation layer 30 formed by hydrophilic material can have curved surface 31S.It is logical Way of example is crossed, curved surface 30S may include concave surface, as described in Fig. 2 F.
As described in Fig. 2 G, other components or layer can before or after forming the first electric conductor 20 and passivation layer 30 shape At above the second surface 10B of substrate.In some embodiments, circuit layer 40 is formed on the second surface 10B of substrate 10 Side and it is electrically connected to the first electric conductor 20.In some embodiments, circuit layer 40 may include, but are not limited to redistribution layer (RDL), lead Electric column (post), conductive column, a combination thereof etc..In some embodiments, at least one semiconductor bare chip 50 is formed in electricity 40 top of road floor.In some embodiments, at least one semiconductor bare chip 50 may include active semiconductor bare die, passive semiconductor Bare die or combinations thereof.By way of example, at least one semiconductor bare chip 50 may include systemonchip (SOC) bare die, storage Device bare die etc..In some embodiments, the second electric conductor 42 can be formed at least one semiconductor bare chip 50 and circuit layer 40 Between, and it is electrically connected at least one semiconductor bare chip 50 and circuit layer 40.In some embodiments, the second electric conductor 42 can wrap Containing conductive bump, conducting sphere, conductive paste etc..In some embodiments, primer layer 44 can be formed in the second surface of substrate 10 Above 10B, between at least one semiconductor bare chip 50 and circuit layer 40 and around the second electric conductor 42.In some embodiments In, primer layer 44 is configured to protect and fix at least one semiconductor bare chip 50 and the second electric conductor 42.In some embodiments In, encapsulant 46 can be formed in above the second surface 10B of substrate 10.In some embodiments, encapsulant 46 can be laterally fenced At least one semiconductor bare chip 50 and primer layer 44.In some embodiments, encapsulant 46 can further cover at least one partly The upper face of semiconductor die 50.In some embodiments, the material of encapsulant 46 may include, but are not limited to moulding compound, such as ring Oxygen resin etc..In some embodiments, semiconductor device 1 can be to cover chip (CoW) device on chip, but not limited to this.? In some embodiments, list granulating operation (such as cutting operation) can be performed to form semiconductor device 1.In some embodiments, Semiconductor device 1 can be electrically connected to package substrate by the first electric conductor 20 to form flip on piece on substrate and cover chip (chip- On-wafer-on-substrate) (CoWoS) is encapsulated.
In some embodiments of this exposure, the passivation layer 30 with thicker first part 31 seals the first electric conductor 20 The edge 22E of second part 22, and therefore help to enhance the robustness of the first electric conductor 20.Side with covering second part 22 The passivation layer 30 of the second part 32 of the first surface 10A of the first part 31 and covering substrate 10 of edge 22E can also help compensate for Or the stress between mitigation substrate 10 and the first electric conductor 20, and therefore can help to mitigate the warpage of substrate 10.In some implementations In example, passivation layer 30 is formed and being matched by selectively applying by light curable material 27.Light curable material 27 can be hydrophilic Property material, can be climbed due to capillarity to the first electric conductor 20 second part 22 edge 22E.In this respect In, can be formed in the case where being not necessarily to additional lithography operations has differently contoured passivation layer 30.In some embodiments, light can It applies to 27 property of can be chosen of curing materials and matches to avoid the residue on the first electric conductor 20, and can omit additionally except Slag treatment.
The semiconductor device and its manufacturing method of this exposure are not limited to embodiment referred to above, but can have other Different embodiments.To simplify the comparison between each of embodiment for describing and carrying out for convenience this exposure, with identical volume Number mark the same components in each of following embodiment.For the difference between more easily comparing embodiment, with Lower description will be described the difference in different embodiments and will not redundantly describe identical components.
Fig. 3 A and Fig. 3 B are according to the schematic diagram of the semiconductor device of one or more embodiments of this exposure, and wherein Fig. 3 A is Schematic cross section, and Fig. 3 B is schematic section through amplifying cross-sectional view.If described in Fig. 3 A and Fig. 3 B, it is different from figure The semiconductor device 1 of 2E, semiconductor device 2 can further include to be formed before the second part 22 for forming the first electric conductor 20 Insulating layer 24 above the first surface 10A of substrate 10.In some embodiments, insulating layer 24 may include passing through low-temperature operation And the polymeric material formed.In some embodiments, the material of insulating layer 24 may include, but are not limited to polyimides.In some realities Apply in example, the thickness of insulating layer 24 generally in the range of from about 0.5 micron to about 15 micron (for example, about 4 microns), but It is without being limited thereto.In some embodiments, the second part 22 of the first electric conductor 20 is formed in 24 top of insulating layer, and is electrically connected to First part 21.In some embodiments, passivation layer 30 is formed in 24 top of insulating layer, to partly cover the first electric conductor 20 edge.In some embodiments, the mode that passivation layer 30 can be similar with disclosed in Fig. 2 C is formed, but not limited to this. In some embodiments, passivation layer 30 includes to have the first height H1 and the edge with the second part 22 of the first electric conductor 20 The first part 31 of 22E contact, and separated with the second height H2 and with the edge 22E of the second part 22 of the first electric conductor 20 And it is connected to the second part 32 of first part 31.
Fig. 4 A and Fig. 4 B are according to the schematic diagram of the semiconductor device of one or more embodiments of this exposure, and wherein Fig. 4 A is Schematic cross section, and Fig. 4 B is schematic section through amplifying cross-sectional view.If described in Fig. 4 A and Fig. 4 B, it is different from figure The semiconductor device 2 of 3A and Fig. 3 B, the insulating layer 24 of semiconductor device 3 can in the first part 21 for forming the first electric conductor 20 and It is formed in front of second part 22 above the first surface 10A of substrate 10.In some embodiments, the first of the first electric conductor 20 Part 21 is formed in substrate 10, and insulating layer 24 extends the edge of the first part 21 of substrate 10 and the first electric conductor 20 Between 21E.In some embodiments, the second part 22 of the first electric conductor 20 is formed in 24 top of insulating layer, and is electrically connected to First part 21.In some embodiments, passivation layer 30 is formed in 24 top of insulating layer, to partly cover the first electric conductor 20 edge.In some embodiments, passivation layer 30 includes to have the first height H1 and the second part with the first electric conductor 20 The first part 31 of 22 edge 22E contact, and the side with the second height H2 and with the second part 22 of the first electric conductor 20 Edge 22E is separated and is connected to the second part 32 of first part 31.
Fig. 5 A, Fig. 5 B, Fig. 5 C and Fig. 5 D are according to each of the manufacture semiconductor devices of one or more embodiments of this exposure The schematic diagram at one of kind operation place, wherein Fig. 5 A, Fig. 5 B and Fig. 5 C are schematic cross sections, and Fig. 5 D is schematic portion Lease making amplifies cross-sectional view.As depicted in Figure 5 A, substrate 10 is received.In some embodiments, circuit layer 40 is formed in substrate Above 10 second surface 10B.In some embodiments, dielectric layer 41 (being shown in Fig. 5 D) can be formed in the second of substrate 10 Between surface 10B and circuit layer 40.In some embodiments, at least one semiconductor bare chip 50 is formed in 40 top of circuit layer. In some embodiments, the second electric conductor 42 can be formed between at least one semiconductor bare chip 50 and circuit layer 40, and be electrically connected It is connected at least one semiconductor bare chip 50 and circuit layer 40.In some embodiments, primer layer 44 can be formed in the of substrate 10 Above two surface 10B, between at least one semiconductor bare chip 50 and circuit layer 40 and around the second electric conductor 42.Some In embodiment, encapsulant 46 can be formed in above the second surface 10B of substrate 10.
In some embodiments, the first electric conductor 20 can be formed in above the first surface 10A of substrate 10.In some implementations In example, the first electric conductor 20 may include first part 21 and the second part 22 for being connected to first part 21.In some embodiments In, first part 21 is generally formed in through-hole 10H, and second part 22 is formed in above the first surface 10A of substrate 10 And outside through-hole 10H.In some embodiments, first part 21 and second part 22 can be formed by same conductive.One In a little embodiments, the material of the first electric conductor 20 may include, but are not limited to tin, its alloy etc..In some embodiments, second The width of part 22 is wider than the width of first part 21.
As described in Fig. 5 B, passivation layer 30 is formed in above the first surface 10A of substrate 10, to partly cover the The edge of one electric conductor 20.In some embodiments, the mode that passivation layer 30 can be similar with disclosed in Fig. 2 C is formed, but not It is limited to this.In some embodiments, passivation layer 30 include with the first height H1 (being shown in Fig. 5 D) and with the first electric conductor The first part 31 of the edge 22E contact of 20 second part 22, and there is the second height H2 (being shown in Fig. 5 D) and with the The edge 22E of the second part 22 of one electric conductor 20 is separated and is connected to the second part 32 of first part 31.In some implementations In example, passivation layer 30 can be around the edge 22E of the second part 22 of the first electric conductor 20.In some embodiments, insulating layer 24 (being shown in Fig. 5 D) can be formed before forming passivation layer 30.In some embodiments, the second part 32 of passivation layer 30 is helped Help protection substrate 10 from rupture.In some embodiments, the first part 31 with high height H1 of passivation layer 30 helps Enhance the robustness of the first electric conductor 20, and helps to mitigate the stress between substrate 10 and the first electric conductor 20.In some implementations In example, the second part 22 of the first electric conductor 20 may include the first subdivision 221 laterally covered by passivation layer 30, and from passivation 30 the second laterally exposed subdivision 222 of layer.
As shown in Fig. 5 C and Fig. 5 D, solder reflow operation is executed with shape to the first electric conductor 20 after forming passivation layer 30 At semiconductor device 4.In some embodiments, the first part 21 of the first electric conductor 20 during solder reflow operation by substrate 10 about Beam, and therefore there is the first width W1 substantially the same with the width before solder reflow operation.In some embodiments, first First subdivision 221 of the second part 22 of electric conductor 20 is constrained during solder reflow operation by the first part 31 of passivation layer 30, And therefore there is the second width W2 substantially the same with the width before solder reflow operation.In some embodiments, the first electricity Second subdivision 222 of the second part 22 of conductor 20 from the first part 31 of passivation layer 30 exposure, whereby solder reflow operation it After be laterally extended, and therefore have third width W3.After solder reflow operation, the second width W2 is than the first width W1 wide, third Width W3 is than the second width W2 wide, and the second subdivision 222 is laterally projecting with partly be overlapped with passivation layer 30.
Fig. 6 A, Fig. 6 B and Fig. 6 C are the various operations according to the manufacture semiconductor device of one or more embodiments of this exposure One of place schematic diagram, wherein Fig. 6 A and Fig. 6 B is schematic cross section, and Fig. 6 C is that schematic section is horizontal through amplification Sectional view.As depicted in fig. 6 a, different from the semiconductor device 4 of Fig. 5 C and Fig. 5 D, to first before forming passivation layer 30 Electric conductor 20 executes solder reflow operation.Due to the first electric conductor 20 second part 22 in the case where not having constraint by reflow, Therefore the second part 22 of the first electric conductor 20 is extended with generally spherical in shape shape.
As described in Fig. 6 B and Fig. 6 C, passivation layer 30 is formed in above the first surface 10A of substrate 10, thus partly The edge of the first electric conductor 20 is covered to form semiconductor device 5.In some embodiments, passivation layer 30 can be with institute in Fig. 2 C Similar mode is disclosed to be formed, but not limited to this.In some embodiments, passivation layer 30 includes with the first height H1 and with the The edge 22E of the second part 22 of one electric conductor 20 a part contact first part 31, and have the second height H2 and with The edge 22E of the second part 22 of first electric conductor 20 is separated and is connected to the second part 32 of first part 31.In some realities It applies in example, the second width W2 of the second part 22 of the first electric conductor 20 is first wider than the first part 21 of the first electric conductor 20 Spend W1 wide.
Fig. 7 A and Fig. 7 B are according to the schematic diagram of the semiconductor device of one or more embodiments of this exposure, and wherein Fig. 7 A is Schematic cross section, and Fig. 7 B is schematic section through amplifying cross-sectional view.If described in Fig. 7 A and Fig. 7 B, it is different from figure The semiconductor device 1 of 2E, the passivation layer 30 of semiconductor device 6 at least partly cover the edge 22E of second part 22, but exposure The first surface 10A of substrate 10.In some embodiments, passivation layer 30 may include the circle for surrounding the edge 22E of second part 22 Shape structure.Passivation layer 30 can have the height H of the height Ha of the second part 22 less than or equal to the first electric conductor 20.Some In embodiment, the passivation layer 30 with cast structural can be applied to the other embodiments of this exposure.
Fig. 8 A and Fig. 8 B are according to the schematic diagram of the semiconductor device of one or more embodiments of this exposure, and wherein Fig. 8 A is Schematic cross section, and Fig. 8 B is schematic section through amplifying cross-sectional view.As described in Fig. 8 A and Fig. 8 B, semiconductor dress Set 7 comprising substrate 10, adjacent to substrate 10 first surface 10A the first electric conductor 20 and positioned at the first surface of substrate 10 Passivation layer 30 above 10A.In some embodiments, each of first electric conductor 20 includes across first of substrate 10 Points 21 and above the first surface 10A of substrate 10 and it is connected to the second part 22 of first part 21.In some embodiments In, the first part 21 of the first electric conductor 20 includes the first width W1, and the second part 22 of the first electric conductor 20 includes than the The second width W2 of one width W1 wide.In some embodiments, passivation layer 30 includes the of the edge 21E of covering first part 21 A part 33, and the second part 34 between the surface 22B of second part 22 and the first surface 10A of substrate 10.One In a little embodiments, semiconductor device 7 can further include the circuit layer 40 being placed in above the second surface 10B of substrate 10, extremely A few semiconductor bare chip 50, the second electric conductor 42, primer layer 44 and encapsulant 46.
In some embodiments, the second part 34 of passivation layer 30 has the height H for being substantially greater than about 10 microns.One In a little embodiments, the height H of second part 34 is generally in the range of from about 10 microns to about 40 micron, or is generally situated between In the range of 10 microns of Yu Congyue to about 15 microns, but not limited to this.In some embodiments, passivation layer 30 may include that polymerization is blunt Change layer, and mode that can be similar with disclosed in Fig. 2 C is formed, but not limited to this.Second part 34 with thicker degree can It helps to provide buffer and mitigates the stress between substrate 10 and the first electric conductor 20, to reduce the rupture and first of substrate 10 The risk of the delamination of electric conductor 20.
In some embodiments of this exposure, there is the passivation layer help of the thicker portion at the edge of covering electric conductor to enhance The robustness of electric conductor, and help compensate for or mitigate the stress between substrate and electric conductor.In some embodiments of this exposure, Passivation layer between electric conductor and substrate helps to provide buffer and mitigates the stress between substrate and electric conductor.In this exposure In some embodiments, passivation layer is formed and being matched by selectively applying by hydrophily light curable material, and can be climbed to electricity The edge of conductor.
In in terms of the demonstration, a kind of semiconductor device includes substrate, the first electric conductor and passivation layer.The substrate Include first surface.Each of described first electric conductor includes the first part across the substrate, and is located at the lining The first surface top at bottom and the second part for being connected to the first part.The passivation layer is located at the institute of the substrate It states above first surface, wherein the passivation layer partly covers the second part of each of described first electric conductor Edge.
In another aspect, a kind of semiconductor device includes substrate, electric conductor and passivation layer.The substrate includes the first table Face.The electric conductor is located above the first surface of the substrate.The passivation layer is located at described the first of the substrate Surface.The passivation layer includes the first part with the EDGE CONTACT of the electric conductor, and is connected to the first part And the second part with the spaced from edges of the electric conductor.The first part of the passivation layer has curved surface.
In another aspect, a kind of method for manufacturing semiconductor device is provided.Receive substrate.In the table of the substrate Electric conductor is formed above face.It selectively applies in the surface of the substrate with light curable material.It can to the light Curing materials are irradiated to form passivation layer in the surface of the substrate, wherein the passivation layer partly covers The edge of the electric conductor.
Foregoing teachings summarize the component of several embodiments, so that those skilled in the art can preferably understand this exposure The aspect of embodiment.It will be understood by one of ordinary skill in the art that it can easily use this exposure embodiment as design or repair It uses instead in implementation and the identical purpose of embodiments described herein and/or realizes the other of the advantage identical as the embodiment The basis of process and structure.Those skilled in the art will also be appreciated that such equivalent constructions are implemented without departing from this exposure Example spirit and scope, and its can be made herein without departing substantially from the spirit and scope of this exposure embodiment it is various Change, replace and changes.

Claims (1)

1. a kind of semiconductor device comprising:
Substrate, it includes first surfaces；
Multiple first electric conductors, wherein each of the multiple first electric conductor includes across first of the substrate Point, and above the first surface of the substrate and it is connected to the second part of the first part；And
Passivation layer, be located at the substrate the first surface above, wherein the passivation layer partly cover it is the multiple The edge of the second part of each of first electric conductor.
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TWI741090B (en) 2021-10-01
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US10535591B2 (en) 2020-01-14
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US20200152560A1 (en) 2020-05-14
US20190051589A1 (en) 2019-02-14

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