CN109379180B - AES algorithm implementation method and device and solid state disk - Google Patents
AES algorithm implementation method and device and solid state disk Download PDFInfo
- Publication number
- CN109379180B CN109379180B CN201811565309.XA CN201811565309A CN109379180B CN 109379180 B CN109379180 B CN 109379180B CN 201811565309 A CN201811565309 A CN 201811565309A CN 109379180 B CN109379180 B CN 109379180B
- Authority
- CN
- China
- Prior art keywords
- key
- ciphertext
- temporary
- initial
- encryption
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Storage Device Security (AREA)
Abstract
The invention relates to the technical field of passwords, and provides an AES algorithm implementation method, an AES algorithm implementation device and a solid state disk, wherein the method comprises the following steps: performing round key addition on the input plaintext according to the input initial key to obtain an initial ciphertext; performing round key processing according to the initial key to obtain a first key; performing first encryption processing according to the initial ciphertext to obtain a first ciphertext, wherein the first encryption processing has N clock cycles, each clock cycle corresponds to M times of circulative iterative operation, and N is a positive integer greater than 1 and M is a positive integer greater than or equal to 2; and performing second encryption processing according to the first ciphertext and the first key to obtain a final ciphertext corresponding to the plaintext. The invention greatly reduces the clock period consumed by a complete AES encryption algorithm flow by finishing at least two iterations in the AES encryption algorithm flow in one clock period, thereby greatly improving the operation speed of a single AES operation unit.
Description
Technical Field
The invention relates to the technical field of passwords, in particular to an AES algorithm implementation method and device and a solid state disk.
Background
When an AES operation unit for implementing an AES encryption algorithm is implemented in a hardware circuit, a sequential control logic of the hardware circuit is considered, one iteration operation in the AES encryption algorithm is usually completed by one clock cycle, and a complete AES encryption algorithm flow requires at least 10 iterations, that is, at least 10 clock cycles are consumed. Taking the key length of 128 bits as an example, at a clock frequency of 200Mhz, the speed of a single AES core is 128 bits/(10 × 5ns), i.e., 0.32G/s. This speed is not sufficient for most current applications involving data storage. The existing solution usually adopts a plurality of AES operation units to increase the operation speed in an external pipeline manner, but the existing solution increases the number of AES operation units, thereby increasing the chip area and hardware resource cost.
Disclosure of Invention
The invention aims to provide an AES algorithm realization method, an AES algorithm realization device and a solid state disk, wherein at least two iterations in an AES encryption algorithm flow are completed in one clock cycle, so that the clock cycle consumed by a complete AES encryption algorithm flow is greatly reduced, and the operation speed of a single AES operation unit is greatly improved.
In order to achieve the above purpose, the embodiment of the present invention adopts the following technical solutions:
in a first aspect, an embodiment of the present invention provides an AES algorithm implementation method, which is applied to a solid-state disk, and the method includes: performing round key addition on the input plaintext according to the input initial key to obtain an initial ciphertext; performing round key processing according to the initial key to obtain a first key, wherein the round key processing has N clock cycles, each clock cycle corresponds to M rounds of key generation operation, wherein N is a positive integer greater than 1, and M is a positive integer greater than or equal to 2; performing first encryption processing according to the initial ciphertext to obtain a first ciphertext, wherein the first encryption processing has N clock cycles, each clock cycle corresponds to M times of circulative iterative operation, and N is a positive integer greater than 1 and M is a positive integer greater than or equal to 2; and performing second encryption processing according to the first ciphertext and the first key to obtain a final ciphertext corresponding to the plaintext.
In a second aspect, an embodiment of the present invention further provides an AES algorithm implementation apparatus, which is applied to a solid-state disk, and the apparatus includes an initial encryption module, a first key generation module, a first encryption module, and a second encryption module. The initial encryption module is used for performing round key addition on an input plaintext according to an input initial key to obtain an initial ciphertext; the first key generation module is used for performing round key processing according to the initial key to obtain a first key, wherein the round key processing has N clock cycles, each clock cycle corresponds to M rounds of key generation operation, N is a positive integer greater than 1, and M is a positive integer greater than or equal to 2; the first encryption module is used for carrying out first encryption processing according to the initial ciphertext to obtain a first ciphertext, wherein the first encryption processing has N clock cycles, each clock cycle corresponds to M times of circulative iterative operation, and N is a positive integer larger than 1 and M is a positive integer larger than or equal to 2; and the second encryption module is used for carrying out second encryption processing according to the first ciphertext and the first key to obtain a final ciphertext corresponding to the plaintext.
In a third aspect, an embodiment of the present invention further provides a solid state disk, where the solid state disk includes a microprocessor, a memory, a flash memory, and an AES operation unit, and the microprocessor is electrically connected to the memory, the flash memory, and the AES operation unit; the memory is used for storing an initial key; the flash memory is used for storing the final ciphertext; the microprocessor is used for receiving the plaintext, reading an initial key in the memory and inputting the initial key into the AES operation unit so as to execute the following steps: according to the input initial key and the input plaintext, the AES operation unit is controlled to perform round key addition to obtain an initial ciphertext, and according to the initial key, the AES operation unit is controlled to perform round key processing to obtain a first key, wherein, the round key processing has N clock cycles, each clock cycle corresponds to M rounds of key generation operation, wherein N is a positive integer greater than 1, M is a positive integer greater than or equal to 2, and the AES arithmetic unit is controlled to perform a first encryption process according to the initial ciphertext to obtain a first ciphertext, wherein the first encryption process has N clock cycles, each clock cycle corresponding to M circulative iterative operations, and controlling the AES operation unit to perform second encryption processing according to the first ciphertext and the first key to obtain a final ciphertext corresponding to the plaintext.
Compared with the prior art, the AES algorithm implementation method, the AES algorithm implementation device and the solid state disk provided by the embodiment of the invention have the advantages that firstly, the microprocessor receives a plaintext sent by the host; then, the microprocessor reads an initial key from the memory, round key addition is carried out according to the input initial key and an input plaintext to obtain an initial ciphertext, and next, round key processing is carried out according to the initial key to control the AES operation unit to obtain a first key, wherein the round key processing has N clock cycles, each clock cycle corresponds to M times of round key generation operation, wherein N is a positive integer greater than 1, and M is a positive integer greater than or equal to 2; and finally, controlling the AES operation unit to perform second encryption processing according to the first ciphertext and the first secret key to obtain a final ciphertext corresponding to the plaintext, and storing the final ciphertext into a flash memory. Compared with the prior art, the embodiment of the invention greatly reduces the clock period consumed by a complete AES encryption algorithm flow by finishing at least two iterations in the AES encryption algorithm flow in one clock period, thereby greatly improving the operation speed of a single AES operation unit.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 shows a block schematic diagram of a solid state disk provided in an embodiment of the present invention.
Fig. 2 shows a flowchart of an AES algorithm implementation method provided in the embodiment of the present invention.
Fig. 3 is a diagram illustrating an example of a first encryption process provided by an embodiment of the present invention.
Fig. 4 shows another AES algorithm implementation method provided by the embodiment of the present invention.
Fig. 5 is a block diagram illustrating an AES algorithm implementing apparatus according to an embodiment of the present invention.
Fig. 6 is a schematic diagram illustrating a unit of a first encryption module according to an embodiment of the present invention.
Fig. 7 is a schematic diagram illustrating a unit of a second encryption module according to an embodiment of the present invention.
FIG. 8 is a block diagram of a plurality of AES units
Icon: 100-solid state disk; 101-a microprocessor; 102-a memory; 103-flash memory; 104-AES operation unit; 200-AES algorithm realizing device; 201-initial encryption module; 202-a first key generation module; 203-a first cryptographic module; 2031 — a first encryption unit; 2032 — a first iteration unit; 204-a second encryption module; 2041-a key generation unit; 2042-a second encryption unit; 2043-a second iteration unit; 2044 — final ciphertext generation unit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present invention, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
Referring to fig. 1, fig. 1 shows a block schematic diagram of a solid state disk 100 according to an embodiment of the present invention, where the solid state disk 100 includes a microprocessor 101, a memory 102, a flash memory 103, and an AES operation unit 104, and the microprocessor 101 is electrically connected to the memory 102, the flash memory 103, and the AES operation unit 104.
The microprocessor 101 may be an application specific integrated circuit, a field programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components. The plaintext may be received from the host and the AES operation unit 104 may be controlled to implement or execute the methods, steps, and logic diagrams disclosed in the embodiments of the present invention.
The memory 102 is a non-volatile memory for storing the initial key, and the memory 102 is not visible to a host outside the solid state disk 100 and is dedicated to storing the initial key.
The flash memory 103 is a nonvolatile storage medium and stores a final ciphertext generated by encrypting a plaintext.
The AES operation unit 104 may be a logic circuit for AES-encrypting the input plaintext according to the input initial key.
First embodiment
Referring to fig. 2, fig. 2 is a flowchart illustrating an AES algorithm implementation method according to an embodiment of the present invention. The processing method comprises the following steps:
and 101, performing round key addition on the input plaintext according to the input initial key to obtain an initial ciphertext.
In the embodiment of the present invention, the plaintext is data that the user needs to store in the solid state disk 100, and in order to enhance the security of the data on the solid state disk 100, after receiving the plaintext issued by the user through the host, the microprocessor 101 of the solid state disk 100 first encrypts the plaintext by using the AES algorithm, and then stores the encrypted data in the flash memory 103 of the solid state disk 100. The encryption of the plaintext by the AES algorithm is implemented by the AES operation unit 104, and therefore, the microprocessor 101 first reads the initial key stored in the memory 102, then inputs the plaintext and the initial key to the AES operation unit 104 to perform the AES encryption operation, and then obtains the final ciphertext, and stores the final ciphertext into the flash memory 103.
The plaintext length of AES encryption is fixed and is 128 bits, a 4x4 byte matrix is formed, the length of each element in the matrix is one byte length, and the length of a key can be 128 bits, 192 bits or 256 bits. The AES encryption process comprises the first round of key addition, the intermediate multiple times of circulative iterative operation and the last non-circulation iterative operation, wherein before the circulative iterative operation, the first round of key addition is carried out on a plaintext according to an initial key to obtain an initial ciphertext, and then the initial ciphertext and the initial key are used as the input of the first circulative iterative operation to continue the subsequent operation.
And 102, performing round key processing according to the initial key to obtain a first key, wherein the round key processing has N clock cycles, each clock cycle corresponds to M times of round key generation operation, N is a positive integer greater than 1, and M is a positive integer greater than or equal to 2.
In the embodiment of the invention, M times of round key generation operation and M times of circulative iteration operation are performed in each clock cycle in one-to-one correspondence, an intermediate result obtained by each round key generation operation is used as an input of the corresponding circulative iteration operation to encrypt an input ciphertext of the circulative iteration operation, a generated key of the mth round key generation operation is used as an input of the M +1 th round key generation operation, a key obtained by the last round key generation operation of each clock cycle is used as an input of the round key generation operation of the next clock cycle, a key obtained by the mth round key generation operation is a first key, and the first key is used as one input of the second encryption operation.
And 103, performing first encryption processing according to the initial ciphertext to obtain a first ciphertext, wherein the first encryption processing has N clock cycles, each clock cycle corresponds to M times of circulative iterative operation, and N is a positive integer greater than 1 and M is a positive integer greater than or equal to 2.
In the embodiment of the present invention, the lengths of the keys are different, and the number of times of the loop iteration operation is different, for example, when the length of the key is 128 bits, the number of times of the loop iteration operation is 9, when the length of the key is 192 bits, the number of times of the loop iteration operation is 11, when the length of the key is 256 bits, the number of times of the loop iteration operation is 13, however, regardless of the length of the key, there will be one non-loop iteration operation at last, and the loop iteration operation includes 4 steps, which are: byte transformation (SubBytes), row shifting (ShiftRows), column mixing (Mixcolumns), and round key addition (AddRoundKey), wherein the byte transformation is to replace each byte by a lookup table method into a corresponding character string in the lookup table through a nonlinear replacement function, the row shifting is to circularly shift each horizontal column in a matrix, the column mixing is to multiply a constant matrix by a matrix obtained in the previous step, so that each element in the matrix is a weighted sum of all elements of the column where the element is located, the round key addition is to xor each byte in the matrix with the round key, each round key is generated by a key generation scheme, and the last operation including the preset step includes the steps of: byte conversion, row shift, and round key addition. In the embodiment of the invention, the number of round keys required to be generated in each clock cycle is equal to the number of times of the circulated iterative operation required to be performed in each clock cycle, the number of round keys required to be generated is equal to the number of times of the circulated iterative operation required to be performed in each clock cycle, the round key generated by the round key generation algorithm each time is used as the input of the next round key generation algorithm, and one round key can be obtained by performing the round key generation algorithm each time. The initial input of the first encryption process is an initial ciphertext and an initial key, and includes N × M circulatable iterative operations, where N is the number of clock cycles and is a positive integer greater than 1, M is the number of circulatable iterative operations completed in each clock cycle and is a positive integer greater than or equal to 2, the output of each circulatable iterative operation is used as the input of the next circulatable iterative operation, for example, N is 4, and M is 2, that is, the first encryption process includes 4 clock cycles in total, each clock cycle includes 2 circulatable iterative operations, fig. 3 shows an exemplary diagram of the first encryption process provided in the embodiment of the present invention, in fig. 3, the first encryption process includes 4 clock cycles in total, each clock cycle includes 2 circulatable iterative operations, the initial input of the first encryption process is an initial ciphertext and an initial key, each clock cycle is before 2 circulatable iterative operations are performed, and generating 2 round keys, namely firstly performing a round key generation algorithm on the initial key to obtain a first round key, then performing a round key generation algorithm on the first round key to obtain a second round key, inputting an initial ciphertext and the first round key when performing first recyclable iterative operation, taking the first temporary ciphertext and the second round key obtained by the first recyclable iterative operation as the input of the second recyclable iterative operation, finally obtaining a first temporary ciphertext output in a first clock period, and continuing to iterate the recyclable iterative operation in each clock period until completing the operation of N clock periods, wherein the first temporary ciphertext output in the Nth clock period is the first ciphertext, and the last round key generated in the Nth clock period is the first key.
It should be noted that the first encryption process lasts for N clock cycles, where a clock cycle is a time unit for the AES to complete one basic action, in the embodiment of the present invention, in each clock cycle, the AES logic operation unit completes at least two circulatable iterative operations, and in an actual application scenario, the AES logic operation unit may also be designed to complete three or more circulatable iterative operations in each clock cycle under the permission of hardware performance.
And 104, performing second encryption processing according to the first ciphertext and the first key to obtain a final ciphertext corresponding to the plaintext.
In the embodiment of the present invention, the operation involved in the second encryption process may include a round-robin iteration operation in addition to the last round-robin iteration operation, and the specific number of round-robin iteration operations may be calculated according to a difference between the total number of round-robin iteration operations of the AES algorithm and the number of round-robin iteration operations included in the first encryption process, for example, the AES algorithm includes 9 round-robin iteration operations and 1 round-robin iteration operation, the first encryption process has 4 clock cycles, and each clock cycle corresponds to 2 round-robin iteration operations, so that the first encryption process completes 4 × 2 to 8 round-robin iteration operations in total, and the remaining 9-8 to 1 round-robin iteration operations are not performed, and at this time, the second encryption process includes a round-robin iteration operation and a round-robin iteration operation in sequence, when the AES algorithm includes 9 circulatable iterative operations and 1 non-circulatable iterative operation, the first encryption process has 3 clock cycles, each clock cycle corresponds to 3 circulatable iterative operations, at this time, the second encryption process may not include a circulatable iterative operation and only includes the last non-circulatable iterative operation, and similarly, when the AES algorithm includes 11 circulatable iterative operations and 1 non-circulatable iterative operation, the first encryption process has 3 clock cycles, each clock cycle corresponds to 3 circulatable iterative operations, at this time, the second encryption process includes 2 circulatable iterative operations and the last non-circulatable iterative operation.
The AES algorithm implementation method provided by the embodiment of the invention greatly reduces the clock period consumed by a complete AES encryption algorithm process by completing at least two iterations in the AES encryption algorithm process within one clock period, thereby greatly improving the operation speed of a single AES operation unit 104.
Further, on the basis of fig. 2, a possible implementation is given below, and fig. 4 shows another AES algorithm implementation method provided in the embodiment of the present invention, please refer to fig. 4, in which step 103 includes a first encryption sub-step (step 103-1) and a first iteration sub-step (step 103-2, step 103-3, and step 103-4), specifically as follows:
103-1, performing a circulative iterative operation in the nth clock period and a round key generation operation in the nth clock period according to the initial ciphertext and the initial key to obtain an intermediate ciphertext obtained by the circulative iterative operation in the nth clock period and an intermediate key obtained by the round key generation operation in the nth clock period; and N is a positive integer less than or equal to N-1.
In an embodiment of the present invention, as an implementation manner, an implementation method for performing a round key generation operation in an nth clock period and a round key generation operation in an nth clock period according to an initial ciphertext and an initial key to obtain a middle ciphertext obtained by the round iterative operation in the nth clock period and a middle key obtained by the round key generation operation in the nth clock period may include a first key generation sub-step, a second encryption sub-step, and a second iteration sub-step, where the first key generation sub-step includes:
and performing M times of round key calculation by using a round key generation algorithm according to the initial key to obtain M first temporary keys, wherein each round key calculation obtains one first temporary key.
In the embodiment of the present invention, in order to complete M times of circulatable iterative operations in a clock cycle, M first temporary keys need to be generated in a clock cycle, so as to ensure that the corresponding first temporary key and the first temporary ciphertext can be input to obtain the result of the current circulatable iterative operation in each circulatable iterative operation in a clock cycle.
The second encryption sub-step comprises:
firstly, acquiring an mth first temporary key from the first temporary keys according to the generation sequence of the first temporary keys; m is a positive integer less than or equal to M-1;
and secondly, performing the circulated iterative operation on the initial ciphertext according to the mth first temporary secret key to obtain the first temporary ciphertext of the circulated iterative operation for the mth time.
In an embodiment of the invention, the order of the circulatable iterative operations in each clock cycle is identical to the order of the round key generation.
The second iteration sub-step comprises:
taking the first temporary ciphertext obtained by the mth time of the circulative iterative operation as the initial ciphertext of the (m + 1) th time of the circulative iterative operation; and when the iteration times reach M, taking a first temporary ciphertext obtained by the Mth time of the circulated iterative operation as an intermediate ciphertext, and taking a first temporary key generated by the Mth time of the key calculation as an intermediate key.
103-2, taking an intermediate ciphertext obtained by the circulating iterative operation in the nth clock period as an initial ciphertext input by the circulating iterative operation in the (n + 1) th clock period;
103-3, obtaining an initial key input by the round key generation operation in the (n + 1) th clock cycle based on the intermediate key of the round key generation operation in the nth clock cycle, and iterating the recyclable iterative operation in the (n + 1) th clock cycle based on the intermediate key obtained by the round key generation operation in the (n + 1) th clock cycle;
103-4, when the iteration number reaches N, taking an intermediate ciphertext obtained through the circulating iterative operation in the Nth clock period as a first ciphertext and taking an intermediate key obtained through the round key generation operation in the Nth clock period as a first key;
the step 104 includes a second key generation sub-step (step 104-1, step 104-2), a third encryption sub-step (step 104-3, step 104-4, step 104-5), a third iteration sub-step (step 104-6, step 104-7), and a final ciphertext generation sub-step (step 104-8), and specifically includes:
step 104-1, obtaining a total number K of keys required by the second encryption processing, wherein K is a preset value-M × N;
in the embodiment of the present invention, the default value is related to the key length, and when the key length is 128 bits, the default value is 10, when the key length is 192 bits, the default value is 12, and when the key length is 256 bits, the default value is 14.
104-2, performing K times of round key calculation by using a round key generation algorithm according to the first key, wherein each round key calculation obtains a second temporary key;
in the embodiment of the present invention, the algorithms used for the second temporary secret key and the first temporary secret key are round secret key generation algorithms, for convenience of description, the embodiment of the present invention refers to the secret key generated in each clock cycle in the first encryption processing step as the first temporary secret key, and refers to the secret key generated in each clock cycle in the second encryption processing step as the second temporary secret key, the number of the secret keys generated in each cycle in the first encryption processing step is the same, and the number of the secret keys generated in each cycle in the second encryption processing step may be different, for example, the AES algorithm includes 9 circulative iterative operations and 1 non-circulative iterative operation, the first encryption processing has 3 clock cycles, each clock cycle corresponds to 3 circulative iterative operations, the second encryption processing includes only the last non-circulative iterative operation, therefore, in the first encryption processing step, the number of the first temporary keys that need to be generated per clock cycle is 3, and in the second encryption processing step, the number of the second temporary keys that need to be generated per clock cycle is 1.
Step 104-3, when K is 1, taking the Kth second temporary key as a second key and taking the first ciphertext as a second ciphertext;
in the embodiment of the present invention, a value K of 1 means that the second encryption process only includes sequential non-circular iterative operations, but does not include circular iterative operations, and at this time, only one second temporary key needs to be generated, and the second temporary key is used as the second key, and the first ciphertext of the first encryption process is used as the second ciphertext.
Step 104-4, when K is larger than 1, acquiring a kth second temporary key from the second temporary keys according to the generation sequence of the second temporary keys; k is a positive integer less than or equal to K-1;
in the embodiment of the present invention, K is greater than 1, which means that the second encryption process includes K-1 circulatable iterative operations and one non-circulatable iterative operation.
104-5, performing the kth circulated iterative operation on the first ciphertext according to the kth second temporary key to obtain the kth second temporary ciphertext;
step 104-6, taking the second temporary ciphertext of the kth time as the first ciphertext of the kth +1 time, and iterating the circulative iterative operation of the kth +1 time;
step 104-7, until the iteration times reach K-1, taking the second temporary secret key of the K-1 time as a second secret key and taking the second temporary cryptograph of the K-1 time as a second cryptograph;
and step 104-8, performing non-loop iterative operation on the second ciphertext according to the second key to obtain a final ciphertext.
In the embodiment of the invention, at least two iterations in the AES encryption algorithm process are completed in one clock cycle, and the round key with the same iteration times as the corresponding iteration times is generated in one clock cycle, so that compared with the prior art, the method has the following beneficial effects:
the clock period consumed by a complete AES encryption algorithm flow is greatly reduced, and the operation speed of a single AES operation unit 104 is greatly improved.
Referring to fig. 5, fig. 5 is a block diagram illustrating an AES algorithm implementing apparatus 200 according to an embodiment of the present invention. The AES algorithm implementing apparatus 200 is applied to the solid state disk 100, and includes an initial encryption module 201; a first encryption module 203; a first encryption unit 2031; a first iteration unit 2032; a second encryption module 204; a key generation unit 2041; a second encryption unit 2042; a second iteration unit 2043; final ciphertext generation unit 2044.
In this embodiment of the present invention, the initial encryption module 201 is configured to perform step 101.
In this embodiment of the present invention, the first key generation module 202 is configured to execute step 102.
In this embodiment of the present invention, the first encryption module 203 is configured to perform step 103.
Referring to fig. 6, fig. 6 shows a schematic unit diagram of the first encryption module 203 according to an embodiment of the present invention, where the first encryption module 203 includes a first encryption unit 2031 and a first iteration unit 2032, where the first encryption unit 2031 is configured to perform step 103-1, and the first iteration unit 2032 is configured to perform steps 103-2 to 103-4.
In this embodiment of the present invention, the second encryption module 204 is used to execute step 104.
Referring to fig. 7, fig. 7 shows a schematic unit diagram of a second encryption module 204 provided in the embodiment of the present invention, where the second encryption module 204 includes a key generation unit 2041, a second encryption unit 2042, a second iteration unit 2043, and a final ciphertext generation unit 2044, where the key generation unit 2041 is configured to perform steps 104-1 to 104-2, the second encryption unit 2042 is configured to perform steps 104-3 to 104-5, the second iteration unit 2043 is configured to perform steps 104-6 to 104-7, and the final ciphertext generation unit 2044 is configured to perform step 104-8.
The AES algorithm implementing apparatus 200 provided in the embodiment of the present invention first controls the AES unit 104 to perform round key addition on the input plaintext according to the input initial key under the control of the microprocessor 101 to obtain an initial ciphertext, then controls the AES unit 104 to perform round key processing according to the initial key under the control of the microprocessor 101 to obtain a first key, then controls the AES unit 104 to perform first encryption processing according to the initial ciphertext to obtain a first ciphertext under the control of the microprocessor 101, and finally controls the AES unit 104 to perform second encryption processing according to the first ciphertext and the first key by the controller of the microprocessor 101 to obtain a final ciphertext corresponding to the plaintext, so as to implement the corresponding technical effect.
It should be noted that the encryption operation involved in all modules and units included in the AES algorithm implementing apparatus 200 is implemented by the microprocessor 101 controlling the AES operation unit 104.
In order to improve the efficiency of AES encryption operation in the prior art, a plurality of AES operation units 104 are usually used for pipeline operation, and further the operation speed of AES encryption operation is improved, for a scenario where a key is 128 bits and 9 times of circulatable iterative operation and 1 time of non-circulatable iterative operation are required, in the prior art, since the circulatable iterative operation is performed once per clock cycle, 10 AES operation units 104 are usually used, each AES operation unit 104 performs the circulatable iterative operation once, and the last AES operation unit 104 performs the last non-circulatable iterative operation, so that the plurality of AES operation units 104 can simultaneously operate, and further the operation speed is improved, however, in the prior art, 10 AES operation units 104 increase the occupied chip area, thereby increasing the cost, on the other hand, when a section of independent plaintext AES operation requiring encryption starts and ends, the AES operations 104 in the 10 AES operations 104 are idle to different degrees, which wastes resources, and the more AES operations 104, the more resources are wasted.
In the embodiment of the present invention, each AES operation unit 104 can complete more than 2 times of circulatable iterative operations in one clock cycle, so that, in the above scenario where 10 AES operation units 104 are required, the same effect is achieved, in the embodiment of the present invention, only 5 AES operation units 104 are required, please refer to fig. 8, fig. 8 is a structural block diagram of a plurality of AES operation units 104 provided in the embodiment of the present invention, in fig. 8, each AES operation unit 104 is individually electrically connected to the microprocessor 101, and the microprocessor 101 controls the 5 AES operation units 104 to perform pipeline operations, on one hand, the chip area occupied by the AES operation units 104 is reduced, and the cost is reduced, and on the other hand, the number of required AES operation units 104 is reduced, so that the waste of resources is also reduced.
In summary, the AES algorithm implementation method, apparatus and solid state disk provided by the present invention include: performing round key addition on the input plaintext according to the input initial key to obtain an initial ciphertext; performing first encryption processing according to the initial ciphertext and the initial key to obtain a first ciphertext and a first key, wherein the first encryption processing has N clock cycles, each clock cycle corresponds to M times of circulative iterative operation, and N is a positive integer greater than 1 and M is a positive integer greater than or equal to 2; and performing second encryption processing according to the first ciphertext and the first key to obtain a final ciphertext corresponding to the plaintext. Compared with the prior art, the embodiment of the invention greatly reduces the clock period consumed by a complete AES encryption algorithm flow by finishing at least two iterations in the AES encryption algorithm flow in one clock period, thereby greatly improving the operation speed of a single AES operation unit.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, the functional modules in the embodiments of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes. It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
Claims (8)
1. An AES algorithm implementation method, the method comprising:
performing round key addition on the input plaintext according to the input initial key to obtain an initial ciphertext;
performing round key processing according to the initial key to obtain a first key, wherein the round key processing has N clock cycles, and each clock cycle corresponds to M rounds of key generation operation, wherein N is a positive integer greater than 1, and M is a positive integer greater than or equal to 2;
performing first encryption processing according to the initial ciphertext to obtain a first ciphertext, wherein the first encryption processing has N clock cycles, each clock cycle corresponds to M times of circulative iterative operation, and N is a positive integer greater than 1 and M is a positive integer greater than or equal to 2;
performing second encryption processing according to the first ciphertext and the first key to obtain a final ciphertext corresponding to the plaintext, wherein the second encryption processing comprises last non-loop iteration operation and loop iteration operation;
the step of performing second encryption processing according to the first ciphertext and the first key to obtain a final ciphertext corresponding to the plaintext comprises a second key generation sub-step, a third encryption sub-step, a third iteration sub-step and a final ciphertext generation sub-step, wherein,
the second key generation sub-step includes:
acquiring a total number K of keys required by the second encryption processing, wherein K is a preset value-M N, and the preset value is related to the key length of the second key;
performing round key calculation for K times by using a round key generation algorithm according to the first key, wherein each round key calculation obtains a second temporary key;
the third encryption sub-step comprises:
when the K is 1, taking the Kth second temporary key as a second key and the first ciphertext as a second ciphertext;
when the K is larger than 1, acquiring a kth second temporary secret key from the second temporary secret keys according to the generation sequence of the second temporary secret keys; k is a positive integer less than or equal to K-1;
performing a kth circulated iterative operation on the first ciphertext according to the kth second temporary key to obtain a kth second temporary ciphertext;
the third iteration sub-step comprises:
taking the second temporary ciphertext of the kth time as a first ciphertext of the kth +1 time, and iterating the kth +1 time of circulated iterative operation;
until the iteration times reach K-1 times, taking the second temporary secret key of the K-1 th time as a second secret key and taking the second temporary cryptograph of the K-1 th time as a second cryptograph;
the final ciphertext generating sub-step comprises:
and performing non-circular iterative operation on the second ciphertext according to the second key to obtain a final ciphertext.
2. The AES algorithm implementation method of claim 1, wherein the step of obtaining a first ciphertext from the initial ciphertext by performing a first encryption process comprises a first encryption sub-step and a first iteration sub-step, wherein,
the first encryption sub-step comprises:
performing a circulative iterative operation in an nth clock period and a round key generation operation in the nth clock period according to the initial ciphertext and the initial key to obtain an intermediate ciphertext obtained by the circulative iterative operation in the nth clock period and an intermediate key obtained by the round key generation operation in the nth clock period; n is a positive integer less than or equal to N-1;
the first iteration sub-step comprises:
taking the intermediate ciphertext obtained by the circulating iterative operation in the nth clock period as an initial ciphertext input by the circulating iterative operation in the (n + 1) th clock period;
obtaining an initial key input by the round key generation operation in the (n + 1) th clock cycle based on an intermediate key of the round key generation operation in the nth clock cycle, and iterating the circulative iterative operation in the (n + 1) th clock cycle based on the intermediate key obtained by the round key generation operation in the (n + 1) th clock cycle;
and when the iteration times reach N, taking an intermediate ciphertext obtained by the circulating iterative operation in the Nth clock period as the first ciphertext and taking an intermediate key obtained by the round key generation operation in the Nth clock period as the first key.
3. The AES algorithm implementation method of claim 2, wherein the step of performing the round-robin iteration operation in the nth clock period and the round key generation operation in the nth clock period based on the initial cipher text and the initial key to obtain the intermediate cipher text obtained by the round-robin iteration operation in the nth clock period and the intermediate key obtained by the round key generation operation in the nth clock period comprises a first key generation sub-step, a second encryption sub-step and a second iteration sub-step, wherein,
the first key generation sub-step comprises:
performing M times of round key calculation by using a round key generation algorithm according to the initial key to obtain M first temporary keys, wherein each round key calculation obtains one first temporary key;
the second encryption sub-step comprises:
acquiring an mth first temporary key from the first temporary keys according to the generation sequence of the first temporary keys; m is a positive integer less than or equal to M-1;
performing a circulated iterative operation on the initial ciphertext according to the mth first temporary key to obtain a first temporary ciphertext of the mth circulated iterative operation;
the second iteration sub-step comprises:
taking the first temporary ciphertext obtained by the mth time of the circulative iterative operation as the initial ciphertext of the (m + 1) th time of the circulative iterative operation;
and when the iteration times reach M, taking a first temporary ciphertext obtained by the Mth time of the circulated iterative operation as an intermediate ciphertext, and taking a first temporary key generated by the Mth time of the key calculation as an intermediate key.
4. An AES algorithm implementing apparatus, the apparatus comprising:
the initial encryption module is used for performing round key addition on an input plaintext according to an input initial key to obtain an initial ciphertext;
a first key generation module, configured to perform round key processing according to the initial key to obtain a first key, where the round key processing has N clock cycles, and each clock cycle corresponds to M round key generation operations, where N is a positive integer greater than 1 and M is a positive integer greater than or equal to 2;
a first encryption module, configured to perform a first encryption process according to the initial ciphertext to obtain a first ciphertext, where the first encryption process has N clock cycles, and each clock cycle corresponds to M times of round-robin iteration operations, where N is a positive integer greater than 1 and M is a positive integer greater than or equal to 2;
the second encryption module is used for carrying out second encryption processing according to the first ciphertext and the first secret key to obtain a final ciphertext corresponding to the plaintext, wherein the second encryption processing comprises last non-circular iteration operation and circular iteration operation;
the second encryption module further comprises a key generation unit, a second encryption unit, a second iteration unit and a final ciphertext generation unit, wherein,
the key generation unit is used for:
acquiring a total number K of keys required by the second encryption processing, wherein K is a preset value-M N, and the preset value is related to the key length of the second key;
performing round key calculation for K times by using a round key generation algorithm according to the first key, wherein each round key calculation obtains a second temporary key;
the second encryption unit is configured to:
when the K is 1, taking the Kth second temporary key as a second key and the first ciphertext as a second ciphertext;
when the K is larger than 1, acquiring a kth second temporary secret key from the second temporary secret keys according to the generation sequence of the second temporary secret keys; k is a positive integer less than or equal to K-1;
performing a kth circulated iterative operation on the first ciphertext according to the kth second temporary key to obtain a kth second temporary ciphertext;
the second iteration unit is used for:
taking the second temporary ciphertext of the kth time as a first ciphertext of the kth +1 time, and iterating the kth +1 time of circulated iterative operation;
until the iteration times reach K-1 times, taking the second temporary secret key of the K-1 th time as a second secret key and taking the second temporary cryptograph of the K-1 th time as a second cryptograph;
the final ciphertext generating unit may include:
and performing non-circular iterative operation on the second ciphertext according to the second key to obtain a final ciphertext.
5. The AES algorithm implementation device of claim 4, wherein the first encryption module comprises a first encryption unit and a first iteration unit, wherein,
the first encryption unit is configured to:
performing a circulative iterative operation in an nth clock period and a round key generation operation in the nth clock period according to the initial ciphertext and the initial key to obtain an intermediate ciphertext of the circulative iterative operation in the nth clock period and a round key generation operation in the nth clock period to obtain an intermediate key; n is a positive integer less than or equal to N-1;
the first iteration unit is configured to:
taking the intermediate ciphertext capable of being subjected to the circular iterative operation in the nth clock period as an initial ciphertext input by the circular iterative operation in the (n + 1) th clock period;
obtaining an initial key of the round key generation operation in the (n + 1) th clock cycle based on an intermediate key of the round key generation operation in the nth clock cycle, and iterating the circulative iterative operation in the (n + 1) th clock cycle based on the intermediate key obtained by the round key generation operation in the (n + 1) th clock cycle;
and when the iteration times reach N, taking the intermediate ciphertext of the N-th time of the circulating iteration operation as the first ciphertext and taking the intermediate key of the N-th time of the circulating iteration operation as the first key.
6. The AES algorithm implementation apparatus of claim 5, wherein the first encryption unit is specifically configured to:
performing M times of round key calculation by using a round key generation algorithm according to the initial key to obtain M first temporary keys, wherein each round key calculation obtains one first temporary key;
acquiring an mth first temporary key from the first temporary keys according to the generation sequence of the first temporary keys; m is a positive integer less than or equal to M-1;
performing a circulated iterative operation on the initial ciphertext according to the mth first temporary key to obtain a first temporary ciphertext obtained by the mth circulated iterative operation;
taking the first temporary ciphertext obtained by the mth time of the circulative iterative operation as the initial ciphertext of the (m + 1) th time of the circulative iterative operation;
and when the iteration times reach M, taking a first temporary ciphertext obtained by the Mth time of the circulated iterative operation as an intermediate ciphertext, and taking a first temporary key generated by the Mth time of the key calculation as an intermediate key.
7. The solid state disk is characterized by comprising a microprocessor, a memory, a flash memory and an AES operation unit, wherein the microprocessor is electrically connected with the memory, the flash memory and the AES operation unit;
the memory is used for storing an initial key;
the flash memory is used for storing the final ciphertext;
the microprocessor is used for receiving plaintext, reading an initial key in a memory, inputting the initial key into the AES operation unit, and executing:
controlling the AES operation unit to perform round key addition according to the input initial key and the input plaintext to obtain an initial ciphertext;
controlling the AES operation unit to perform round key processing according to the initial key to obtain a first key, wherein the round key processing has N clock cycles, each clock cycle corresponds to M times of round key generation operation, and N is a positive integer greater than 1 and M is a positive integer greater than or equal to 2;
controlling the AES operation unit to perform first encryption processing according to the initial ciphertext to obtain a first ciphertext, wherein the first encryption processing has N clock cycles, each clock cycle corresponds to M times of circulative iterative operation, and N is a positive integer greater than 1 and M is a positive integer greater than or equal to 2;
controlling the AES operation unit to perform second encryption processing according to the first ciphertext and the first key to obtain a final ciphertext corresponding to the plaintext, wherein the second encryption processing comprises last non-circular iteration operation and circular iteration operation;
the step of performing second encryption processing according to the first ciphertext and the first key to obtain a final ciphertext corresponding to the plaintext comprises a second key generation sub-step, a third encryption sub-step, a third iteration sub-step and a final ciphertext generation sub-step, wherein,
the second key generation sub-step includes:
acquiring a total number K of keys required by the second encryption processing, wherein K is a preset value-M N, and the preset value is related to the key length of the second key;
performing round key calculation for K times by using a round key generation algorithm according to the first key, wherein each round key calculation obtains a second temporary key;
the third encryption sub-step comprises:
when the K is 1, taking the Kth second temporary key as a second key and the first ciphertext as a second ciphertext;
when the K is larger than 1, acquiring a kth second temporary secret key from the second temporary secret keys according to the generation sequence of the second temporary secret keys; k is a positive integer less than or equal to K-1;
performing a kth circulated iterative operation on the first ciphertext according to the kth second temporary key to obtain a kth second temporary ciphertext;
the third iteration sub-step comprises:
taking the second temporary ciphertext of the kth time as a first ciphertext of the kth +1 time, and iterating the kth +1 time of circulated iterative operation;
until the iteration times reach K-1 times, taking the second temporary secret key of the K-1 th time as a second secret key and taking the second temporary cryptograph of the K-1 th time as a second cryptograph;
the final ciphertext generating sub-step comprises:
and performing non-circular iterative operation on the second ciphertext according to the second key to obtain a final ciphertext.
8. The solid state disk of claim 7, wherein the AES operation units are a plurality of, each electrically connected to the microprocessor, the plurality of AES operation units performing the method of any of claims 1-3 in a pipelined manner under a controller of the microprocessor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811565309.XA CN109379180B (en) | 2018-12-20 | 2018-12-20 | AES algorithm implementation method and device and solid state disk |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811565309.XA CN109379180B (en) | 2018-12-20 | 2018-12-20 | AES algorithm implementation method and device and solid state disk |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109379180A CN109379180A (en) | 2019-02-22 |
| CN109379180B true CN109379180B (en) | 2022-04-19 |
Family
ID=65371042
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811565309.XA Active CN109379180B (en) | 2018-12-20 | 2018-12-20 | AES algorithm implementation method and device and solid state disk |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109379180B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111106935B (en) * | 2019-12-27 | 2023-05-16 | 天津芯海创科技有限公司 | Key management architecture supporting multi-terminal heterogeneous mode |
| CN112104450A (en) * | 2020-08-27 | 2020-12-18 | 广东技术师范大学天河学院 | Symmetric data encryption method and system and electronic equipment |
| CN112398641A (en) * | 2020-11-17 | 2021-02-23 | 上海桂垚信息科技有限公司 | Application method of AES encryption algorithm on encryption chip |
| CN114244510A (en) * | 2021-12-20 | 2022-03-25 | 深圳忆联信息***有限公司 | Hardware acceleration apparatus, method, device, and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1527531A (en) * | 2003-03-07 | 2004-09-08 | 华为技术有限公司 | Method of realizing data enciphering standard or double data enciphering standard |
| CN1677921A (en) * | 2004-03-31 | 2005-10-05 | 华为技术有限公司 | Method for enciphering data through programmable device |
| CN104639314A (en) * | 2014-12-31 | 2015-05-20 | 深圳先进技术研究院 | Device based on AES (advanced encryption standard) encryption/decryption algorithm and pipelining control method |
| CN108718317A (en) * | 2018-06-12 | 2018-10-30 | 飞天诚信科技股份有限公司 | A kind of method and device of personal identification number protection |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8155306B2 (en) * | 2004-12-09 | 2012-04-10 | Intel Corporation | Method and apparatus for increasing the speed of cryptographic processing |
| US8966279B2 (en) * | 2010-12-21 | 2015-02-24 | Apple Inc. | Securing the implementation of a cryptographic process using key expansion |
| US9843441B2 (en) * | 2013-09-24 | 2017-12-12 | Intel Corporation | Compact, low power advanced encryption standard circuit |
| US11809610B2 (en) * | 2014-06-16 | 2023-11-07 | Texas Instruments Incorporated | Hardware protection of inline cryptographic processor |
-
2018
- 2018-12-20 CN CN201811565309.XA patent/CN109379180B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1527531A (en) * | 2003-03-07 | 2004-09-08 | 华为技术有限公司 | Method of realizing data enciphering standard or double data enciphering standard |
| CN1677921A (en) * | 2004-03-31 | 2005-10-05 | 华为技术有限公司 | Method for enciphering data through programmable device |
| CN104639314A (en) * | 2014-12-31 | 2015-05-20 | 深圳先进技术研究院 | Device based on AES (advanced encryption standard) encryption/decryption algorithm and pipelining control method |
| CN108718317A (en) * | 2018-06-12 | 2018-10-30 | 飞天诚信科技股份有限公司 | A kind of method and device of personal identification number protection |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109379180A (en) | 2019-02-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109379180B (en) | AES algorithm implementation method and device and solid state disk | |
| US11055065B2 (en) | PUF-based true random number generation system | |
| JP4871944B2 (en) | Crypto system configured to extend the repetition period of a random number sequence | |
| TWI374649B (en) | Digital random number generator based on digitally-controlled oscillators | |
| KR101393806B1 (en) | Multistage physical unclonable function system | |
| KR20110004474A (en) | A closed galois field cryptographic system | |
| CN112422272B (en) | AES encryption method and circuit for preventing power consumption attack | |
| JP2006317802A (en) | Pseudo-random number generating system, encryption system, and decryption system | |
| US20130129088A1 (en) | Method and system for generating unpredictable pseudo-random numbers | |
| CN103299576A (en) | Bit generation device and bit generation method | |
| WO2011123575A1 (en) | Cryptographic processor with dynamic update of encryption state | |
| CN116663038A (en) | Data encryption method and device and electronic equipment | |
| WO2014013680A1 (en) | Universal hash function calculation device, method, and program | |
| Verma et al. | 3D-Playfair cipher with additional bitwise operation | |
| US20220085974A1 (en) | Method and circuit for performing a substitution operation | |
| CN112287333B (en) | Lightweight adjustable block cipher realization method, system, electronic equipment and readable storage medium | |
| Zhang et al. | Secure binary arithmetic coding based on digitalized modified logistic map and linear feedback shift register | |
| Deshpande et al. | AES encryption engines of many core processor arrays on FPGA by using parallel, pipeline and sequential technique | |
| JP5207153B2 (en) | Pseudo random number generation system | |
| US11347706B2 (en) | Rotor movement control and rotor wiring for rotor-based encryption machines and electronic equivalents | |
| Sireesha et al. | A novel approach of area optimized and pipelined FPGA implementation of AES encryption and decryption | |
| Qin et al. | On the cryptanalysis of two cryptographic algorithms that utilize chaotic neural networks | |
| US20180054307A1 (en) | Encryption device | |
| US11237800B2 (en) | Time-shifted seed for random number generator | |
| Kumar et al. | FPGA Implementation of High Performance Hybrid Encryption Standard |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |