CN109362238A - Photogenic voltage element and its manufacturing method - Google Patents
Photogenic voltage element and its manufacturing method Download PDFInfo
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- CN109362238A CN109362238A CN201780024559.XA CN201780024559A CN109362238A CN 109362238 A CN109362238 A CN 109362238A CN 201780024559 A CN201780024559 A CN 201780024559A CN 109362238 A CN109362238 A CN 109362238A
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- 238000002425 crystallisation Methods 0.000 claims abstract description 239
- 230000008025 crystallization Effects 0.000 claims abstract description 239
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- 239000010409 thin film Substances 0.000 claims abstract description 72
- 239000004065 semiconductor Substances 0.000 claims abstract description 58
- 238000010276 construction Methods 0.000 claims abstract description 46
- 239000001257 hydrogen Substances 0.000 claims abstract description 32
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 32
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 29
- 238000005036 potential barrier Methods 0.000 claims abstract description 15
- 239000010408 film Substances 0.000 claims description 197
- 238000000034 method Methods 0.000 claims description 140
- 230000008569 process Effects 0.000 claims description 98
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- 239000010410 layer Substances 0.000 description 333
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- 239000010703 silicon Substances 0.000 description 188
- 239000012528 membrane Substances 0.000 description 127
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- 238000009792 diffusion process Methods 0.000 description 48
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- 238000002161 passivation Methods 0.000 description 25
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- 238000010304 firing Methods 0.000 description 19
- 229910052698 phosphorus Inorganic materials 0.000 description 19
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- 239000000203 mixture Substances 0.000 description 17
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 10
- 238000000151 deposition Methods 0.000 description 9
- 230000005669 field effect Effects 0.000 description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 8
- 229910052796 boron Inorganic materials 0.000 description 8
- 230000004913 activation Effects 0.000 description 7
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- 229910052581 Si3N4 Inorganic materials 0.000 description 3
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
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- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
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- LVXIMLLVSSOUNN-UHFFFAOYSA-N fluorine;nitric acid Chemical compound [F].O[N+]([O-])=O LVXIMLLVSSOUNN-UHFFFAOYSA-N 0.000 description 1
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- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Life Sciences & Earth Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Sustainable Development (AREA)
- Photovoltaic Devices (AREA)
Abstract
Stepped construction (ST) has the multiple tunnel oxides (104) being arranged alternately on semiconductor substrate (100) and multiple system of crystallization thin film semiconductive layers (106).Multiple tunnel oxides (104) include the 1st to the n-th tunnel oxide (104a~104f) configured in order on semiconductor substrate (100).1st tunnel oxide (104a) is abutted with semiconductor substrate (100), and has potential barrier for the minority carrier of semiconductor substrate (100).Each layer of multiple system of crystallization thin film semiconductive layers (106) has the 1st conductivity type.Multiple system of crystallization thin film semiconductive layers (106) include the 1st to the n-th system of crystallization thin film semiconductive layer (106a~106f) configured in order on semiconductor substrate (100).Each layer of multiple system of crystallization thin film semiconductive layers (106) has 1 atom % average hydrogen content below in 50% or more thickness range, and with 50% or more percent crystallization in massecuite.
Description
Technical field
The present invention relates to photogenic voltage element and its manufacturing methods.
Background technique
As typical photogenic voltage element, there is the silicon solar cell of system of crystallization.System of crystallization silicon solar cell uses
Monocrystalline silicon or polysilicon have high transfer efficiency especially with the solar battery of monocrystal substrate.In the system of crystallization silicon sun
In energy battery, in order to improve its open-circuit voltage, passivating technique is widely applied.Specifically, very thin oxygen is formed in substrate surface
Change film, is formed on silicon doped layer.The thin oxidation film is functioned as tunnel oxide.Pass through tunnel oxide
The field effect that layer is formed by energy band potential barrier and doped layer generates, minority carrier is beaten back.Thus minority carrier is answered
Conjunction is suppressed.By passivating technique, can obtain be more than 700mV high open-circuit voltage.On the other hand, due to most current-carrying
The transmission of son can successfully be carried out by tunnel-effect, therefore can be avoided the series resistance as caused by tunnel oxide
Increase.According to the above, high open-circuit voltage and Fill factor can be taken into account by passivating technique.
In the method for following non-patent literatures 1, tunnel oxide/phosphorus doping is formed at the back side of n-type silicon substrate
After silicon layer, it is heat-treated at more than 600 DEG C and less than 1000 DEG C.Then, it is directly comprehensively formed on phosphorus doping silicon layer
Rear electrode.As formed electrode method, by after the seed layer hot evaporation of Ti/Pd/Ag, carry out plating Ag.
In the method for following patent documents 1, on tunnel oxide/semiconductor layer, be arranged transparent conductive film and
Comb-type electrode in the transparent conductive film.Transparent conductive film has as the protective film for protecting doped layer to damage from electrode formation
Function.In addition, transparent conductive film is due to conductive, tool different from the case where insulating layer is as protective film is used
Have that it is unnecessary to be arranged contact of the electrode with semiconductor layer and opening is arranged.
In the method for following patent documents 2, it is alternatively formed thin film semiconductive layer and insulating film at low temperature.On it
Form doped layer and passivating film.Then, such as by silk screen print method form electrode.Specifically, the silk using silver paste is carried out
The firing of wire mark brush and printed silver paste.
Existing technical literature
Patent document
Patent document 1: Japanese Unexamined Patent Publication 2012-60080 bulletin
Patent document 2: Japanese Unexamined Patent Application Publication 2015-526894 bulletin
Non-patent literature
Non-patent literature 1:F.Feldmann etc., " Passivated rear contacts for high-
efficiency n-type Si Solar Cells providing high interface passivation quality
And excellent transport characteristics ", Solar Energy Materials&Solar Cells
120(2014)270-274
Summary of the invention
Subject to be solved by the invention
In the method for above-mentioned non-patent literature 1, on the doped layer for constituting tunnel juntion together with tunnel oxide,
The electrode collected for photoelectric current is formed using vapour deposition method and plating.But if it is considered that productivity when mass production,
For electrode, such as the method for patent document 2, it is preferred to use formed using there is the print process of silver paste.If by print process,
High temperature firing technique is carried out, thus, it is possible to be formed: contact and low-resistance electrode with high reliablity.On the other hand, such as
By print process, the deterioration in characteristics of tunnel juntion layer can occur fruit for the thermal damage due to caused by firing process or the erosion of silver etc..
Caused by being burnt into for deterioration in characteristics, not only in the case where tunnel juntion layer side is using firing electrode, but also only with
The face of tunnel juntion layer opposite side can also occur in the case where using firing electrode.That is, pyroprocess when due to firing, can send out
The deterioration of the structure of raw tunnel oxide/doped layer.Using firing process the case where directly forming electrode on doped layer
Under, for deterioration in characteristics, electrode is broken through 100nm doped layer below due to burn-through and corrodes substrate and occur.In order to anti-
Only it, considers to reduce firing temperature and then the method using low temperature sintering silver paste.But this method incurs the increasing of resistance
Big and electrical contact deterioration.In addition, it is also to ask that physical damnification caused by friction when electrode print etc., which damages doped layer,
Topic.For the method for merely making doped layer thicken, the compound influence in doped layer cannot be inhibited to reach substrate interface,
It can lead to deterioration in characteristics sharply.
In the method for above patent document 1, transparent conductive film is set between doped layer and electrode.Think: burning as a result,
Physical damnification is generated when corroding substrate at electrode, printing to be suppressed.But transparent conductive film has high carrier dense
Degree, therefore be easy to absorb light.Therefore, current loss increases.In addition, transparent conductive film lacks heat resistance, therefore the electricity in firing
Characteristic or structure are easy deterioration.Therefore, technological temperature is restricted.Therefore, simple, mass production may not can be selected sometimes
And the technique of high reliablity.
In the method for patent document 2, the process that thin film semiconductive layer and insulating film alternately form a film is carried out at low temperature.
Therefore, the activation rate of the dopant in thin film semiconductive layer is low, therefore its field effect is weak.Therefore, the passivation effect obtained
It dies down.In turn, because film forming carries out at low temperature, containing a large amount of hydrogen, or big deformation is included.Therefore, if it is
The firing of electrode and carry out 800 DEG C or so of heat treatment, then as the disengaging of the hydrogen clamped by interlayer or releasing for deformation
It puts, is easy to happen film stripping.Film stripping can make the structure disturbance of high passivation effect in order to obtain.
The present invention completes to solve the above problem, and its purpose is to provide can more reliably obtain high passivation effect
The photogenic voltage element and its manufacturing method of fruit.
Means for solving the problems
Photogenic voltage element of the invention has semiconductor substrate, stepped construction and protective film.Semiconductor substrate has the 1st
Any one of conductivity type and the 2nd conductivity type opposite with the 1st conductivity type.Stepped construction has alternately to be set on a semiconductor substrate
The multiple tunnel oxides set and multiple system of crystallization thin film semiconductive layers.Protective film is arranged in stepped construction, by dielectric
Production.Multiple tunnel oxides include the 1st to the n-th tunnel oxide configured in order on a semiconductor substrate.1st tunnel
Oxide skin(coating) is abutted with semiconductor substrate, and has potential barrier for the minority carrier of semiconductor substrate.Multiple system of crystallization films
Each layer of semiconductor layer has the 1st conductivity type.Multiple system of crystallization thin film semiconductive layers include successively to match on a semiconductor substrate
The 1st to the n-th system of crystallization thin film semiconductive layer set.Thickness of each layer of multiple system of crystallization thin film semiconductive layers 50% or more
Range has 1 atom % average hydrogen content below, and with 50% or more percent crystallization in massecuite.
For the manufacturing method of photogenic voltage element according to an aspect of the present invention, there is process below.Shape
At stepped construction, the stepped construction is included with appointing in the 1st conductivity type and the 2nd conductivity type opposite with the 1st conductivity type
The multiple tunnel oxides being alternately arranged on the semiconductor substrate of one and multiple system of crystallization thin film semiconductive layers.It is tied in stacking
The protective film made by dielectric is formed on structure.Multiple tunnel oxides include the 1st configured in order on a semiconductor substrate
To the n-th tunnel oxide.1st tunnel oxide is abutted with semiconductor substrate, and for the minority carrier of semiconductor substrate
Son has potential barrier.Each layer of multiple system of crystallization thin film semiconductive layers has the 1st conductivity type.Multiple system of crystallization thin film semiconductive layers
Include the 1st to the n-th system of crystallization thin film semiconductive layer configured in order on a semiconductor substrate.1st to the n-th system of crystallization film is partly led
Body layer is respectively provided with the 1st to the n-th impurity concentration.The 1st impurity concentration is denseer than other any impurity in 1st to the n-th impurity concentration
It spends all low.For forming the process of stepped construction, the process comprising sequentially forming the 1st to the n-th system of crystallization thin film semiconductive layer,
In each layer of process for forming the 1st to the n-th system of crystallization thin film semiconductive layer, the system of crystallization film for forming the 2nd to the n-th is partly led
Temperature used in each process of the process of body layer is than forming used in the process of the 1st system of crystallization thin film semiconductive layer
Temperature is low.
For the manufacturing method of photogenic voltage element according to another aspect of the present invention, there is process below.Shape
At stepped construction, the stepped construction is included with appointing in the 1st conductivity type and the 2nd conductivity type opposite with the 1st conductivity type
The multiple tunnel oxides being alternately arranged on the semiconductor substrate of one and multiple system of crystallization thin film semiconductive layers.It is tied in stacking
The protective film made by dielectric is formed on structure.Multiple tunnel oxides include the 1st configured in order on a semiconductor substrate
To the n-th tunnel oxide.1st tunnel oxide is abutted with semiconductor substrate, and for the minority carrier of semiconductor substrate
Son has potential barrier.Each layer of multiple system of crystallization thin film semiconductive layers has the 1st conductivity type.Multiple system of crystallization thin film semiconductive layers
Include the 1st to the n-th system of crystallization thin film semiconductive layer configured in order on a semiconductor substrate.1st to the n-th system of crystallization film is partly led
Body layer is respectively provided with the 1st to the n-th impurity concentration.The impurity concentration of kth (n >=k >=2) is respectively than in 1st to the n-th impurity concentration
The impurity concentration of k-1 is high.For forming the process of stepped construction, comprising sequentially forming the 1st to the n-th system of crystallization thin film semiconductor
The process of layer.It is formed in each layer of process of the 1st to the n-th system of crystallization thin film semiconductive layer, forms the knot of kth (n >=k >=2)
System of crystallization thin film semiconductive layer of the temperature used in each process of the process of crystallographic system thin film semiconductive layer than forming kth -1
Process used in temperature it is low.
The effect of invention
Photogenic voltage element according to the present invention, the 1st, thickness model of each system of crystallization thin film semiconductive layer 50% or more
Enclosing has 1 atom % average hydrogen content below.Thereby, it is possible to the heat treatment procedures and burning in the manufacture of photogenic voltage element
At film stripping caused by the disengaging for inhibiting hydrogen in process.2nd, each system of crystallization thin film semiconductive layer has 50% or more crystallization
Rate.Thermally-induced deformation release as a result, becomes smaller.Therefore, film stripping can more reliably be inhibited.In turn, since percent crystallization in massecuite is high, because
Dopant in this system of crystallization thin film semiconductive layer is fully activated.System of crystallization thin film semiconductive layer is for tunnel oxygen as a result,
Compound layer plays forceful electric power field-effect, thus obtains high passivation effect.By high passivation effect, open-circuit voltage can be improved.
In addition, by inhibiting film stripping, the structure for obtaining high passivation effect is suitably maintained.It, can be more reliable by above
Ground obtains high passivation effect.Thereby, it is possible to more reliably obtain high open circuit voltage.
According to the manufacturing method of photogenic voltage element according to one aspect of the present invention, the 2nd to the n-th system of crystallization is formed
Temperature used in each process of the process of thin film semiconductive layer is than forming in the process of the 1st system of crystallization thin film semiconductive layer
Used temperature is low.Generable 1st system of crystallization film half when the 2nd to the n-th system of crystallization thin film semiconductive layer is formed as a result,
The heat deterioration of conductor layer is inhibited.Therefore it can be improved the performance of photogenic voltage element.
According to the manufacturing method of the photogenic voltage element of another aspect according to the invention, just kth (n >=k >=2) are being formed
System of crystallization thin film semiconductive layer process each process used in for temperature, than in the system of crystallization for forming kth -1
Temperature used in the process of thin film semiconductive layer is low.It is formed as a result, generable when the system of crystallization thin film semiconductive layer of kth
The heat deterioration of the system of crystallization thin film semiconductive layer of kth -1 is suppressed.Therefore, the 1st to the n-th system of crystallization thin film semiconductive layer is whole
Heat deterioration be suppressed.Therefore it can be improved the performance of photogenic voltage element.
The purpose of the present invention, feature, aspect and advantage will become more clear by detailed description below and attached drawing
Chu.
Detailed description of the invention
Fig. 1 is the sectional view that outlined the composition of the photogenic voltage element in embodiments of the present invention 1.
Fig. 2 is the flow chart that outlined the composition of the manufacturing method of photogenic voltage element of Fig. 1.
Fig. 3 is the sectional view that outlined a process of the manufacturing method of photogenic voltage element of Fig. 1.
Fig. 4 is the sectional view that outlined a process of the manufacturing method of photogenic voltage element of Fig. 1.
Fig. 5 is the sectional view that outlined a process of the manufacturing method of photogenic voltage element of Fig. 1.
Fig. 6 is the sectional view that outlined a process of the manufacturing method of photogenic voltage element of Fig. 1.
Fig. 7 is the sectional view that outlined a process of the manufacturing method of photogenic voltage element of Fig. 1.
Fig. 8 is the sectional view that outlined a process of the manufacturing method of photogenic voltage element of Fig. 1.
Fig. 9 is the sectional view that outlined a process of the manufacturing method of photogenic voltage element of Fig. 1.
Figure 10 is the sectional view that outlined a process of the manufacturing method of photogenic voltage element of Fig. 1.
Figure 11 is the sectional view that outlined a process of the manufacturing method of photogenic voltage element of Fig. 1.
Figure 12 is the sectional view that outlined a process of the manufacturing method of photogenic voltage element of Fig. 1.
Figure 13 is the stream that outlined the composition of manufacturing method of the photogenic voltage element in embodiments of the present invention 2
Cheng Tu.
Figure 14 is the sectional view that outlined the composition of the photogenic voltage element in embodiments of the present invention 3.
Figure 15 is the flow chart that outlined the composition of the manufacturing method of photogenic voltage element of Figure 14.
Figure 16 is the sectional view that outlined a process of the manufacturing method of photogenic voltage element of Figure 14.
Figure 17 is the sectional view that outlined a process of the manufacturing method of photogenic voltage element of Figure 14.
Figure 18 is the sectional view that outlined a process of the manufacturing method of photogenic voltage element of Figure 14.
Figure 19 is the sectional view that outlined a process of the manufacturing method of photogenic voltage element of Figure 14.
Figure 20 is the sectional view that outlined a process of the manufacturing method of photogenic voltage element of Figure 14.
Figure 21 is the sectional view that outlined a process of the manufacturing method of photogenic voltage element of Figure 14.
Figure 22 is the sectional view that outlined a process of the manufacturing method of photogenic voltage element of Figure 14.
Figure 23 is the sectional view that outlined a process of the manufacturing method of photogenic voltage element of Figure 14.
Figure 24 is the sectional view that outlined a process of the manufacturing method of photogenic voltage element of Figure 14.
Figure 25 is the sectional view that outlined a process of the manufacturing method of photogenic voltage element of Figure 14.
Figure 26 is relationship and the percent crystallization in massecuite one by the sheet resistance of N-shaped system of crystallization membrane silicon layer and potential open terminal voltage
Act the example for the evaluation result being indicated.
Specific embodiment
Hereinafter, based on attached drawing, embodiments of the present invention will be described.It should be noted that the present invention is not implemented by these
Mode limits.
1 > of < embodiment
(summary of composition)
Referring to Fig.1, the solar battery 201 (photogenic voltage element) of present embodiment includes N-shaped monocrystalline silicon substrate 100
(semiconductor substrate), stepped construction ST, n-type impurity diffusion layer 103 (emitter layer), protective film 107, light receiving side dielectric layer
108, antireflection film 109, light-receiving surface electrode 110 and rear electrode 111.
For stepped construction ST, it is set as n=6, there is the 1st to the n-th tunnel oxide 104a~104f and the 1st to the
N-shaped system of crystallization membrane silicon layer 106a~106f (system of crystallization thin film semiconductive layer) of n.Hereinafter, sometimes by the 1st to the n-th tunnel
Oxide skin(coating) 104a~104f be collectively referred to as " tunnel oxide 104 ", in addition, sometimes by N-shaped system of crystallization membrane silicon layer 106a~
106f is collectively referred to as " N-shaped system of crystallization membrane silicon layer 106 ".With regard to multiple tunnel oxides 104 and multiple N-shaped system of crystallization membrane silicon layers
For 106, n times are arranged alternately on the back side 100B of N-shaped monocrystalline silicon substrate 100.In the present embodiment, right as described above
The situation of n=6 is specifically illustrated, but n is not limited to 6, can be 2 or more arbitrary integer.
1st to the n-th tunnel oxide 104a~104f is sequentially located on N-shaped monocrystalline silicon substrate 100.1st tunnel oxidation
Nitride layer 104a is abutted with N-shaped monocrystalline silicon substrate 100.In addition, the 1st tunnel oxide 104a is for N-shaped monocrystalline silicon substrate 100
Minority carrier has potential barrier.
1st to the n-th N-shaped system of crystallization membrane silicon layer 106a~106f is sequentially located on N-shaped monocrystalline silicon substrate 100.Multiple n
Each layer of type system of crystallization membrane silicon layer 106 has 1 atom % average hydrogen content below in 50% or more thickness range.Separately
Outside, each layer of multiple N-shaped system of crystallization membrane silicon layers 106 has 50% or more percent crystallization in massecuite.
1st to the n-th N-shaped system of crystallization membrane silicon layer 106a~106f is respectively provided with the 1st to the n-th impurity concentration as doping
The concentration of agent.Preferably, the 1st impurity concentration in the 1st to the n-th impurity concentration is lower than other arbitrary impurity concentrations.It is preferred that
The impurity concentration on ground, the kth (n >=k >=2) in the 1st to the n-th impurity concentration is higher than the impurity concentration of kth -1 respectively.Preferably,
1st impurity concentration is 1 atom % or less.Preferably, each layer of the 1st to the n-th N-shaped system of crystallization membrane silicon layer 106a~106f
Contain phosphorus atoms as dopant.
Protective film 107 is arranged on stepped construction ST.Protective film 107 is made by dielectric.
N-type impurity diffusion layer 103 is arranged on the light-receiving surface 100A of N-shaped monocrystalline silicon substrate 100.Light receiving side dielectric layer
108 are arranged on n-type impurity diffusion layer 103.Antireflection film 109 is arranged via light receiving side dielectric layer 108 in n-type impurity
On diffusion layer 103.
Antireflection film 109 and light receiving side dielectric layer 108 are penetrated through and reach n-type impurity diffusion by light-receiving surface electrode 110
Layer 103.Light-receiving surface electrode 110 is electrically connected with n-type impurity diffusion layer 103 as a result,.Light-receiving surface electrode 110 may include gate electrode and
Bus electrode (not shown).
Protective film 107 is penetrated through and reaches stepped construction ST by rear electrode 111.Rear electrode 111 and stepped construction as a result,
ST electrical connection.Rear electrode 111 may include gate electrode and bus electrode (not shown).
(summary of manufacturing method)
Hereinafter, being illustrated for the summary of the manufacturing method of solar battery 201.
N-type impurity diffusion layer 103 (Fig. 2: step S100) is formed on the light-receiving surface 100A of N-shaped monocrystalline silicon substrate 100.
Next, forming stepped construction ST on the back side 100B of N-shaped monocrystalline silicon substrate 100.With regard to forming stepped construction ST
Process for, include: sequentially form the 1st to the n-th tunnel oxide 104a~104f process (Fig. 2: step S110) and
Sequentially form the process (Fig. 2: step S120) of the 1st to the n-th N-shaped system of crystallization membrane silicon layer 106a~106f.By step S110
And S120 is alternately.More specifically, carrying out step S110 in each circulation of n times circulation, step S120 is then carried out.
In each step of step S120, forming 1 will change as the N-shaped noncrystalline of N-shaped system of crystallization membrane silicon layer 106
Membrane silicon layer (Fig. 2: step S121).N-shaped amorphous film silicon layer contains the dopant for assigning N-shaped.In N-shaped amorphous thin
In film silicon layer, contain hydrogen atom used in its deposition procedures.Then, N-shaped amorphous film silicon layer is carried out by heat treatment
Crystallization step (Fig. 2: step S122).By the crystallization, make part or all of crystallization of N-shaped amorphous film silicon layer
Change.That is, the variation of N-shaped amorphous film silicon layer is N-shaped system of crystallization membrane silicon layer 106.At this point, above-mentioned dopant is activated.In addition,
It is detached from a part of the hydrogen atom in N-shaped amorphous film silicon layer.In the present embodiment, the temperature of the heat treatment is equivalent to
Temperature used in the formation of N-shaped system of crystallization membrane silicon layer 106.Forming N-shaped system of crystallization membrane silicon layer 106a~106f's
Temperature used in process needs not be identical temperature, can be adjusted to each process.
Preferably, with regard to formed the 1st to the n-th N-shaped system of crystallization membrane silicon layer 106a~106f process for, with the 1st to
The 1st impurity concentration in n-th impurity concentration becomes the mode lower than any other impurity concentration to carry out.In turn, make to be formed
In each process of 1st to the n-th N-shaped system of crystallization membrane silicon layer 106a~106f, formed the 2nd to the n-th N-shaped system of crystallization film
N-shaped system of crystallization membrane silicon layer 106a of the temperature used in each process of the process of silicon layer 106b~106f than formation the 1st
Process used in temperature it is low.
It is highly preferred that for the process for forming the 1st to the n-th N-shaped system of crystallization membrane silicon layer 106a~106f, with the 1st
Each concentration of the impurity concentration of kth (n >=k >=2) into the n-th impurity concentration becomes the side higher than the impurity concentration of kth -1
Formula carries out.In turn, make to be formed in the process of each layer of 106a~106f of the 1st to the n-th N-shaped system of crystallization membrane silicon layer, be formed
N-shaped knot of the temperature than forming kth -1 used in the process of the N-shaped system of crystallization membrane silicon layer 106 of kth (n >=k >=2) is each
Temperature used in the process of crystallographic system membrane silicon layer 106 is low.
After forming stepped construction ST, it is formed on protective film 107 (Fig. 2: step S130).Next, expanding in n-type impurity
It dissipates and forms light receiving side dielectric layer 108 and antireflection film 109 (Fig. 2: step S140) on layer 103.Next, printing light-receiving surface
Electrode 110 and rear electrode 111 (Fig. 2: step S150).Next, by light-receiving surface electrode 110 and the firing (figure of rear electrode 111
2: step S160).By burning caused by thus, light-receiving surface electrode 110 is by antireflection film 109 and light receiving side dielectric layer
108 penetrate through and reach n-type impurity diffusion layer 103.In addition, protective film 107 is penetrated through and reaches stepped construction by rear electrode 111
ST.By the above, manufacture solar battery 201.
(details of manufacturing method)
Place is repeated with above-mentioned general section although also having, hereinafter, the details to manufacturing method is said
It is bright.
Referring to Fig. 3, firstly, preparing N-shaped monocrystalline silicon substrate 100.For N-shaped monocrystalline silicon substrate 100, by using use
The mechanical cutting method of scroll saw etc., cuts silicon ingot and is sliced and manufactured.After mechanical cutting at once, on its surface, remaining has
Pollution or damage.Therefore, by using the wet etching process for there are the aqueous slkalis such as sodium hydroxide solution, the etching on surface is carried out.It is excellent
Selection of land forms the small concaveconvex structure (not shown) for being referred to as texture structure on surface in the etching.In texture structure
In formation, aqueous slkali and additive are used.By the small concaveconvex structure on surface, the light of incident N-shaped monocrystalline silicon substrate 100 exists
Multipath reflection occurs for surface, and thus, it is possible to reduce the reflection loss of light.Further, since light absorption caused by the increase of optical path length
Increase, it is contemplated that short circuit current improve.
After etching, by cleaning by it is on the surface of N-shaped monocrystalline silicon substrate 100, by organic matter or metallic pollution etc. generate
Attachment remove.For example, carrying out RCA cleaning, SPM (sulfuric acid hydrogen peroxide mixture, Sulfuric Acid Hydrogen
Peroxide Mixture) cleaning or HPM (hydrochloric acid hydrogen peroxide mixture, Hydrochloric Acid Hydrogen
Peroxide Mixture)。
Next, forming n-type impurity on the light-receiving surface 100A of N-shaped monocrystalline silicon substrate 100 in step S100 (Fig. 2)
Diffusion layer 103.As the example of its method, for using boron-doping silicon glass (Boron Silicate Glass:BSG) film
The situation of 101 (impurity diffusion sources) is illustrated.It, can be by using there is B for bsg film 1012H6Atmospheric pressure chemical deposition
(Air Pressure Chemical Vapor Deposition:APCVD) method is formed.N-shaped monocrystalline silicon substrate 100 by
Bsg film 101 is formed on smooth surface 100A.But, for BSG, detour to the back side of N-shaped monocrystalline silicon substrate 100 also a littlely
100B and end face.It is therefore preferable that not removed partially after the deposition of bsg film 101 by what is deposited due to detour.In the removing
In, such as 0.5~1.0% or so hydrofluoric acid can be used.Additionally, it is preferred that being formed on bsg film 101 as the non-of dielectric film
Doped silicon glass (Non doped Silicate Glass:NSG) film 102 (cap rock).NSG film 102 plays the role of cap rock, by
This prevents the boron in bsg film 101 to be detached from into gas phase.Therefore, effectively boron can be made to spread.In addition, for NSG film 102,
Later when being formed by the heat treatment of N-shaped system of crystallization membrane silicon layer 106 on the back side 100B of N-shaped monocrystalline silicon substrate 100,
It plays a role as the diffusion barrier of dopant.The film thickness of each film of bsg film 101 and NSG film 102 be, for example, 30nm with
Above and less than 150nm and 100nm or more and less than 500nm.For their film thickness, if excessively thin, its duty cannot be played
Can, if blocked up, formed and removing becomes difficult.
The boron of bsg film 101 is set to carry out thermal diffusion using diffusion furnace referring to Fig. 4.N-type impurity diffusion layer is formed as a result,
103.At this point, with regard to formed n-type impurity diffusion layer 103 sheet resistance for, be preferably set to such as 50 Ω/ or more and less than
150Ω/□.For sheet resistance, consider n-type impurity diffusion layer 103 in the compound of minority carrier, light absorption and with by
The contact resistance of smooth surface electrode 110 determines.
It is explained, BBr is used in the formation of bsg film 1013In the case where gas phase reaction, not only in light-receiving surface 100A
Above and overleaf bsg film is also formed on 100B.Therefore, formed on the bsg film 101 on light-receiving surface 100A by heat oxide film or
After barrier layer caused by nitride film (not shown), the bsg film on the 100B of the back side is removed with hydrofluoric acid.Then, with fluorine nitric acid
Or the inorganic agents such as sodium hydroxide carry out single side removing to the bsg film on the 100B of the back side.For above-mentioned nitride film, for example, can
It is formed by using there is the plasma CVD method of silane gas and nitrogen or ammonia.It is explained, the also conduct of these barrier layers
Barrier layer when subsequent dopant activation is heat-treated works, therefore is preferably formed with the thickness of 50nm or more.
Be explained, for n-type impurity diffusion layer 103, it is alternative using impurity diffusion source as bsg film 101 and
It is formed by ion implantation.Specifically, it can be incited somebody to action on the light-receiving surface 100A of N-shaped monocrystalline silicon substrate 100 by ion implanting
Boron is squeezed into, and then, by carrying out thermal diffusion in diffusion furnace, forms n-type impurity diffusion layer 103.
Next, being formed stepped construction ST (Fig. 1) by the way that the group of step S110 and S120 (Fig. 2) are repeated n times.
It is illustrated below for the process.
Referring to Fig. 5, in the 1st step S110 (Fig. 2), on the back side 100B of N-shaped monocrystalline silicon substrate 100, formed
1st tunnel oxide 104a.If only considering to constitute tunnel juntion, it is each to be able to use silicon oxide layer or pellumina etc.
Kind dielectric film.But, sufficient passivation effect, tunnel oxide 104a are needed for N-shaped monocrystalline silicon substrate in order to obtain
100 minority carrier has potential barrier.In the present embodiment, semiconductor-based due to using N-shaped monocrystalline silicon substrate 100
Minority carrier in plate is hole.Therefore, tunnel oxide 104a needs to have the hole of N-shaped monocrystalline silicon substrate 100
There is potential barrier.In other words, the material needs of tunnel oxide 104a are constituted on the back side 100B of N-shaped monocrystalline silicon substrate 100
The dielectric substance of potential barrier in valence band.Consider from the viewpoint, in the present embodiment, uses silicon oxide layer as tunnel
Oxide skin(coating) 104a.It is explained, as variation, in the case where the minority carrier of semiconductor substrate is electronics, tunnel
The material of oxide skin(coating) is necessary for constituting the dielectric substance of the potential barrier in conduction band on the back side of semiconductor substrate.Potential barrier
Highly preferred is 0.2eV or more, more preferably 0.5eV or more.If potential barrier is too low, the minority that tunnel oxide generates is carried
The passivation effect of stream reduces significantly.
As the forming method of silicon oxide layer, for example, carrying out the dipping in Ozone Water.With regard to silicon oxide layer film thickness and
Speech, is controlled by ozone concentration and dip time.As other methods, being able to use thermal oxide, nitric acid oxidation, plasma
Chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition:PECVD) method, atomic layer deposition
(Atomic Layer Deposition:ALD) the methods of method or UV/ ozone irradiation.With regard to the 1st tunnel oxide 104a
Film thickness for, for example, 0.5nm or more and less than 5nm.If film thickness is too small, not only majority carrier but also minority carrier
Son is also by the 1st tunnel oxide 104a, therefore compound increase.Therefore, open-circuit voltage reduces.If opposite film thickness is excessive,
Then the tunnel conveying of majority carrier is interfered, therefore series resistance increases.Therefore, electrical characteristics deteriorate.For the 1st tunnel oxygen
The high-precision control of the film thickness of compound layer 104a can be used hydrofluoric acid etc. pre- before the formation of the 1st tunnel oxide 104a
It will first be removed due to the established oxidation film such as heat treatment.
Referring to Fig. 6, as the 1st step S120 (Fig. 2), carries out step S121 and connect its step S122.
In step S121 (Fig. 2), the 1st N-shaped amorphous film silicon layer is formed on the 1st tunnel oxide 104a
105a.As forming method, using the sedimentation for using the unstrpped gas containing hydrogen atom.For example, using SiH is used4's
The chemical vapour deposition techniques such as PECVD.Therefore, the N-shaped amorphous film silicon layer 105a of the 1st of formation contains hydrogen, concentration example
For example 10 atom % or so.For in order to assign impurity added by N-shaped, i.e. donor, preferred phosphorus.For the addition of phosphorus,
It can be by using PH3It is carried out as impurity gas.PH3A part of the hydrogen atom of gas can be in the N-shaped amorphous of the 1st of formation
It is remained in matter membrane silicon layer 105a.The film thickness of 1st N-shaped amorphous film silicon layer 105a is preferably 5nm or more and less than 50nm,
More preferably 5nm or more and 20nm or less.If the film thickness of the 1st N-shaped amorphous film silicon layer 105a is too small, by making it
The film thickness of 1st N-shaped system of crystallization membrane silicon layer 106a obtained from crystallization also excessively becomes smaller.Therefore, field effect dies down, because
Resistance at this tunnel joint part increases, and the effect of beating back of minority carrier becomes smaller.Therefore, deterioration in characteristics.If opposite
Film thickness is excessive, and thermal deformation becomes larger, therefore becomes easy generation film stripping.In addition, exceedingly thick in the light that can help to power generation
The 1st N-shaped amorphous film silicon layer 105a absorb in the case where, decrease of power generation.
In turn, referring to Fig. 7, in step S122 (Fig. 2), one of the N-shaped amorphous film silicon layer 105a by making the 1st
Divide or entirety crystallizes, forms the 1st N-shaped system of crystallization membrane silicon layer 106a.It is crystallized by being heat-treated.For example, by n
Type monocrystalline silicon substrate 100 is imported into diffusion furnace, improves the temperature of N-shaped monocrystalline silicon substrate 100 while making nitrogen flow
To heat treatment temperature, which is kept into for certain time.In addition, making the 1st N-shaped amorphous thin by the heat treatment
N-type dopant activation in film silicon layer 105a, thus its sheet resistance reduces.At this point, the 1st N-shaped amorphous film silicon layer
The preferably 1 atom % or less of impurity concentration contained in 105a.If impurity concentration is excessively high, impurity breaks through the 1st tunnel oxide
Layer 104a and spread, silicon substrate can be reached in large quantities.As a result, passivation effect deteriorates.
Compared with the 1st N-shaped amorphous film silicon layer 105a, in the 1st N-shaped system of crystallization membrane silicon layer 106a, N-shaped is mixed
Miscellaneous dose of activation rate is high, field effect enhancing.Therefore, for the 1st tunnel oxide 104a and N-shaped monocrystalline silicon substrate 100, phase
Effect is adequately beaten back to minority carrier.In order to which that evaluates carrier beats back effect, by potential open terminal voltage
(Implied Open Circuit Voltage (so-called Implied VOC)) measurement result be shown in Figure 26.With N-shaped
The activation rate of dopant increases, and the sheet resistance of N-shaped system of crystallization membrane silicon layer is reduced.In this measurement result, Implied VOC
With its for the region smaller than 2000 Ω of sheet resistance/ or so degree increase, 500 Ω/ or so for the first time be saturated, from
Seeing in the region of 500 Ω/ or so to 300 Ω/ or so becomes substantially certain tendency.Investigate N-shaped system of crystallization at this time
The crystallinity of membrane silicon layer, as a result percent crystallization in massecuite is 50% or more in the former region, and percent crystallization in massecuite is in the region of the latter
80% or more.Therefore, the percent crystallization in massecuite of the 1st N-shaped system of crystallization membrane silicon layer 106a is 50% or more, preferably 80% or more.Just
For percent crystallization in massecuite mentioned here, for example, Raman diffused light spectrometry can be used to measure.In this case, 480cm is measured-1、
510cm-1And 520cm-1Everywhere in peak intensity I480, I510 and I520.Then, according to than (I510+I520)/(I480+
I510+I520) × 100 (%) calculates percent crystallization in massecuite.Just make the amorphous film crystallizing silicon layer added with the phosphorus as dopant
For optimal heat treatment temperature, it is strictly dependent on both phosphorus concentration and film thickness.But in the model of film thickness 5nm~50nm
It encloses, optimal heat treatment temperature is mainly determined by phosphorus concentration.Herein, it is preferable that the 1st N-shaped amorphous film silicon layer 105a's
Heat treatment temperature is 400 DEG C or more and less than 900 DEG C.If heat treatment temperature is too low, without fully promoting the 1st N-shaped
The crystallization of amorphous film silicon layer 105a.Therefore, back surface field effect reduces, therefore cannot get high passivation effect.In addition,
Since the reduction of resistance becomes inadequate, it is therefore possible to interfere the transmission of majority carrier.If heat treatment temperature is more than 400
DEG C, then it is detached from hydrogen is since the 1st N-shaped amorphous film silicon layer 105a, crystallization is promoted.On the other hand, if
Heat treatment temperature is more than 900 DEG C, then passivation effect and phosphorus concentration start to reduce independently significantly, leads to the drop of open-circuit voltage
It is low.This is because: due to the heat treatment of high temperature, n-type dopant in the 1st N-shaped amorphous film silicon layer 105a is by the 1st tunnel
Oxide skin(coating) 104a is penetrated through and is diffused into N-shaped monocrystalline silicon substrate 100, and the structure that the 1st tunnel oxide 104a thus occurs is broken
It is bad or the 1st N-shaped system of crystallization membrane silicon layer 106a field effect reduction.
Here, for the 1st N-shaped system of crystallization membrane silicon layer 106a, below by the 2nd tunnel oxide 104b and
2 N-shaped amorphous film silicon layer 105b (Fig. 8) obstruction.Therefore, if the 1st N-shaped system of crystallization membrane silicon layer 106a exceedingly contains
Have hydrogen, then by the crystallization carried out after the formation of the 1st N-shaped system of crystallization membrane silicon layer 106a and firing when heat, largely
Hydrogen be sharp detached from.The 1st N-shaped system of crystallization membrane silicon layer 106a is peelable at this time.Therefore, the 1st N-shaped system of crystallization thin film silicon
Average contained hydrogen concentration needs sufficiently low in layer 106a.On the other hand, with the 1st tunnel oxide 104a and the 2nd tunnel
Each layer of the interface of oxide skin(coating) 104b, hydrogen are difficult to be detached from, and in these interfaces, hydrogen concentration becomes relatively high.Due to interface
The hydrogen concentration at place is high, therefore dangling bonds is more fully blocked, and the advantage that passivation effect is enhanced is obtained.By making hot place
Reason temperature variation and find the minimum treatment temperature that film stripping does not occur, by secondary ion mass spectrometry to using the processing temperature
The hydrogen concentration in film when spending is evaluated.As a result, the 1st N-shaped amorphous film silicon layer 105a after film forming at once
In (Fig. 6) containing 10~20% hydrogen.After heat treatment, in the 1st N-shaped system of crystallization membrane silicon layer 106a (Fig. 8) with the 2nd tunnel
The region remaining that oxide skin(coating) 104b connects has the hydrogen of several % or so, and passivation effect is maintained.On the other hand, the 1st N-shaped
Near center on the thickness direction of system of crystallization membrane silicon layer 106a, hydrogen concentration is 1% or less.In addition, in view of will later into
The process margin of heat treatment temperature in the capable process for forming other N-shaped system of crystallization membrane silicon layers 106, it is desirable to form the 1st n
The temperature of the heat treatment of type system of crystallization membrane silicon layer 106a is as high as possible.It is determined likewise by secondary ion mass spectrometry
The hydrogen concentration of the N-shaped system of crystallization membrane silicon layer 106a of the 1st handled at high temperature, as a result known to for the measurement detection limit with
Under (0.1% or less).Therefore, with apart 50% or more and 99% below of the interface with the 2nd tunnel oxide 104b
Thickness range, average contained hydrogen concentration is preferably 1 atom % hereinafter, more preferably in the 1st N-shaped system of crystallization membrane silicon layer 106a
It is set as 0.1% or less.For other N-shaped system of crystallization membrane silicon layers 106 other than the 1st N-shaped system of crystallization membrane silicon layer 106a
Equally.
Referring to Fig. 8, next, as the 2nd step S110 (Fig. 2), in the 1st N-shaped system of crystallization membrane silicon layer 106a
The 2nd tunnel oxide 104b of upper formation.It, can N-shaped system of crystallization membrane silicon layer 106a with the 1st with regard to its forming method and film thickness
Situation it is same.
Next, carrying out the 2nd step S120 (Fig. 2).Specifically, firstly, on the 2nd tunnel oxide 104b,
In the 2nd step S121 (Fig. 2), the 2nd N-shaped amorphous film silicon layer 105b is formed.With regard to its forming method and film thickness
Speech, can be substantially the same with the situation of the 1st N-shaped amorphous film silicon layer 105a, but preferably make the 2nd N-shaped amorphous film
The n-type dopant of N-shaped amorphous film silicon layer 105a of the concentration of the n-type dopant of silicon layer 105b than the established 1st it is dense
Degree is high.
Referring to Fig. 9, then, in the 2nd step S122 (Fig. 2), by the N-shaped amorphous film silicon layer for making the 2nd
A part of 105b or all crystallizations, form the 2nd N-shaped system of crystallization membrane silicon layer 106b.In the same manner as the 1st situation,
It is crystallized by being heat-treated, activates n-type dopant at this time.The percent crystallization in massecuite of 2nd N-shaped system of crystallization membrane silicon layer 106b
It is preferably 50% or more, more preferably 80% or more in the same manner as the 1st N-shaped system of crystallization membrane silicon layer 106a.For other n
Type system of crystallization membrane silicon layer 106 is also the same.
In the case where heat treatment temperature is excessively high compared with optimum temperature needed for crystallization or heat treatment time and knot
Best Times needed for crystallization are compared in the case where too long, since the diffusion of extra heat, the phosphorus as dopant is excessive
Ground promotes.As a result, phosphorus with the interface of tunnel oxide 104 near occur segregation or phosphorus in tunnel oxide 104
Thus diffusion is possible to cause to generate heat deterioration as defect.Particularly, with regard to the 1st N-shaped system of crystallization membrane silicon layer 106a and
Speech, compared with other N-shaped system of crystallization membrane silicon layers 106, close to N-shaped monocrystalline silicon substrate 100, therefore above-mentioned extra heat
Caused heat deterioration tends to get bigger.Therefore, in order to be adequately suppressed the established 1st N-shaped system of crystallization membrane silicon layer 106a
Heat deterioration generation, it is necessary to make N-shaped amorphous thin of the heat treatment temperature than the 1st of the 2nd N-shaped amorphous film silicon layer 105b
The heat treatment temperature of film silicon layer 105a reduces.But if merely reducing heat treatment temperature, it is possible to the 2nd N-shaped noncrystalline
The crystallization of membrane silicon layer 105b becomes inadequate.In addition, big due to being remained in the 2nd N-shaped system of crystallization membrane silicon layer 106b
The hydrogen of amount, therefore the film stripping caused by causing to be detached from because of hydrogen sharply is possible in the heat treatment procedure or firing process below
From.It, makes the concentration of the n-type dopant of the 2nd N-shaped amorphous film silicon layer 105b than established 1st N-shaped in order to prevent
The concentration of the n-type dopant of amorphous film silicon layer 105a is high.As described above, optimal heat treatment temperature master needed for crystallization
It to be determined by phosphorus concentration, phosphorus concentration is higher, and optimal heat treatment temperature more reduces.Therefore, with the 2nd n of higher phosphorus concentration
The optimal heat treatment temperature of type amorphous film silicon layer 105b becomes the best of the N-shaped amorphous film silicon layer 105a than the 1st
Heat treatment temperature want low.It therefore, can be will not compared with the heat treatment temperature of the 1st N-shaped amorphous film silicon layer 105a
The heat treatment temperature of the 2nd N-shaped amorphous film silicon layer 105b is reduced in the case where incurring being greatly reduced of crystallinity.That is, energy
It is enough to obtain high-crystallinity while inhibiting thermal damage.
Referring to Fig.1 0, thereafter, in the case where n >=3, the group of step S110 and S120 are further repeated.For example, such as
In the case that Fig. 1 manufactures the solar battery 201 of n=6 like that, repetition that further progress is 4 times.As a result, by the 3rd~the 6th
N-shaped system of crystallization membrane silicon layer 106c~106f of tunnel oxide 104c~104f and the 3rd~the 6th is alternatively formed.Therefore, will
The group of step S110 and S120 are total to be carried out 6 times.6 groups of tunnel oxide 104 and N-shaped system of crystallization thin film silicon are formed as a result,
Layer 106.That is, forming entire stepped construction ST.It should be noted that n is not limited to 6, as long as being 2 or more.By making kth (n
>=k >=2) N-shaped system of crystallization membrane silicon layer 106 phosphorus concentration it is higher than the phosphorus concentration of the N-shaped system of crystallization membrane silicon layer 106 of kth -1,
The heat treatment temperature in crystallization step can be reduced in the insufficient situation without crystallinity.Thus, it is possible to inhibit heat bad
Change.
Preferably, the donor concentrations of the activation in the N-shaped system of crystallization membrane silicon layer 106 of kth are crystallized than the N-shaped of kth -1
It is the donor concentrations height of the activation in membrane silicon layer.As a result, further away from the surface of N-shaped monocrystalline silicon substrate 100, the N-shaped that is stacked
The current potential for hole in system of crystallization membrane silicon layer 106 more increases.Therefore, just in N-shaped system of crystallization membrane silicon layer 106 due to
Light is absorbed and for the minority carrier that generates, the electric field as caused by electric potential gradient, by N-shaped monocrystalline silicon substrate 100
A side pull.Therefore, which can also assist in power generation.Therefore it can be improved generating efficiency.
It is explained, for each layer of sheet resistance of multiple N-shaped system of crystallization membrane silicon layers 106, in addition to its phosphorus is dense
Other than degree, its film thickness is also relied on.Therefore, between multiple N-shaped system of crystallization membrane silicon layers 106, the size of above-mentioned phosphorus concentration
Relationship may not directly be reflected by the relationship of the size of sheet resistance.
In turn, referring to Fig.1 1, using hydrofluoric acid BSG will be formed by the light-receiving surface 100A of N-shaped monocrystalline silicon substrate 100
Film 101 and NSG film 102 (Figure 10) fully remove.It is explained, this process can be in the crystallization step (step that will carry out n times
S122 (Fig. 2)) arbitrary process before carry out.In this case, in the crystallization step after removing bsg film 101,
It will not be spread from the bsg film 101 as n-type impurity diffusion source into atmosphere for boron in the heat treatment of crystallization.It is therefore prevented that
The N-shaped system of crystallization membrane silicon layer 106 formed in the crystallization step is adhered to and be spread in boron atom.On the other hand, at this
In the case of kind, in the formation process of the N-shaped system of crystallization membrane silicon layer 106 after exposing n-type impurity diffusion layer 103, from N-shaped
The n-type dopant that system of crystallization membrane silicon layer 106 is spread into atmosphere is possible to spread into n-type impurity diffusion layer 103.Therefore,
For the removing of bsg film 101 and NSG film 102, preferably carried out after last crystallization step (step S122 (Fig. 2)).
Even if bsg film 101 exists in crystallization step, if it is covered by the NSG film 102 as cap rock, also substantially prevented from boron
It is spread from bsg film 101 into atmosphere.
Referring to Fig.1 1, in step S130 (Fig. 2), via stepped construction on the back side 100B of N-shaped monocrystalline silicon substrate 100
ST forms protective film 107.In other words, it is formed in N-shaped system of crystallization membrane silicon layer 106f (n-th N-shaped system of crystallization membrane silicon layer)
Protective film 107.For the material of protective film 107, for example, for silicon nitride, silica, silicon oxynitride, uncrystalline silicon or micro-
Crystal silicon.Protective film 107 can also have the stepped construction of multiple films.Wherein, protective film 107 preferably has than N-shaped system of crystallization film
The hardness with high hardness of silicon layer 106.This is because: the silk-screen printing of electrode is carried out on protective film 107 in a subsequent process step
When, protect N-shaped system of crystallization membrane silicon layer 106 from because of the physical damnification caused by the contact or friction etc. with version.In addition, protection
Hydrogen concentration in film 107 is preferably all higher than the average hydrogen concentration in all N-shaped system of crystallization membrane silicon layers 106.If protecting
Contain enough hydrogen in film 107, then in N-shaped system of crystallization membrane silicon layer 106 or N-shaped monocrystalline silicon in heat treatment and when electrode is burnt into
Dangling bonds present in interface of the substrate 100 with tunnel oxide 104 is fully sealed by the hydrogen spread from protective film 107
End.Passivation effect caused by stepped construction ST improves as a result,.In addition, the film thickness of protective film 107 is preferably 5nm or more and not
To 200nm.If film thickness is too small, in electrode firing below, electrode penetrates stepped construction ST, becomes easy erosion N-shaped
System of crystallization membrane silicon layer 106.In addition, the supply from protective film 107, above-mentioned hydrogen is easy to become inadequate.If opposite
Film thickness is excessive, is burnt into even across subsequent electrode, and electrode also becomes difficult to the N-shaped system of crystallization membrane silicon layer with stepped construction ST
106e contact.As a result, the contact resistance of electrode increases.
Referring to Fig.1 2, it is miscellaneous via p-type on the light-receiving surface 100A of N-shaped monocrystalline silicon substrate 100 in step S140 (Fig. 2)
Matter diffusion layer 103 sequentially forms light receiving side dielectric layer 108 and antireflection film 109.In other words, in n-type impurity diffusion layer 103
On, sequentially form light receiving side dielectric layer 108 and antireflection film 109.Light receiving side dielectric layer 108 can be oxidation film,
Preferably pellumina.It is known: for pellumina, due to having negative fixed charge, to n-type impurity diffusion layer
103 play excellent passivation effect.For pellumina, for example, can be formed by ALD method or CVD method.Pellumina
Film thickness is, for example, 2nm or more and less than 50nm.Antireflection film 109 is, for example, to be formed by silicon nitride by plasma CVD method
Film.For the film thickness of antireflection film 109, according to the film thickness of light receiving side dielectric layer 108, it is set as sunlight spectrum most
Good film thickness, such as it is set as 30nm or more and the degree less than 80nm.
Next, in step S150 (Fig. 2), N-shaped monocrystalline silicon substrate 100 light-receiving surface 100A and back side 100B it is each
On a, light-receiving surface electrode 110 and rear electrode 111 are printed via several components.Specifically, metallic and glass will be contained
The paste of particle is coated with as comb pattern shape by rubbing methods such as silk screen print methods.Then, the paste being applied is dry.Just
For the drying, for example, being carried out by the processing in 10 minutes or so at 200 DEG C in drying oven.It, will be by the moment
Smooth surface electrode 110 and rear electrode 111 are printed onto respectively on antireflection film 109 and protective film 107.
Referring again to Fig. 1, the electrode that light-receiving surface electrode 110 and rear electrode 111 are carried out in step S160 (Fig. 2) is burnt
At.Light-receiving surface electrode 110 and rear electrode 111 can be simultaneously burnt into.For the temperature of firing process, for example, being 800 DEG C
Left and right.In firing process, by the glass particle of light-receiving surface electrode 110 by light receiving side dielectric layer 108 and antireflection film
109 are etched, and light-receiving surface electrode 110 is corroded to n-type impurity diffusion layer 103.Thus make light-receiving surface electrode 110 and n-type impurity
Diffusion layer 103 is electrically connected.Similarly, protective film 107 is etched by the glass particle of rear electrode 111, rear electrode
111 corrode to N-shaped system of crystallization membrane silicon layer 106f.Rear electrode 111 is set to be electrically connected with N-shaped system of crystallization membrane silicon layer 106f as a result,
It connects.
By the above, obtaining solar battery 201.
(effect)
Solar battery 201 (Fig. 1) according to the present embodiment, the 1st, each layer of N-shaped system of crystallization membrane silicon layer 106 exists
50% or more thickness range has 1 atom % average hydrogen content below.As a result, in the manufacture of solar battery 201
In heat treatment procedure and firing process, it is able to suppress the film stripping as caused by the disengaging of hydrogen.2nd, N-shaped system of crystallization membrane silicon layer
106 each layer has 50% or more percent crystallization in massecuite.Thermally-induced deformation release as a result, tails off.Therefore, can more reliably press down
Film removing.In turn, because percent crystallization in massecuite is high, the dopant in N-shaped system of crystallization membrane silicon layer 106 is fully activated.Pass through as a result,
N-shaped system of crystallization membrane silicon layer 106 plays forceful electric power field-effect to tunnel oxide, obtains high passivation effect.By high blunt
Change effect, can be improved open-circuit voltage.In addition, suitably being maintained by the inhibition of film stripping for obtaining high passivation effect
Structure.By can more reliably obtain high passivation effect above.Thus, it is possible to more reliably obtain high open circuit voltage.
In addition, improving N-shaped knot by activating the dopant in N-shaped system of crystallization membrane silicon layer 106 fully
The electric conductivity of crystallographic system membrane silicon layer 106.Thus the performance of solar battery 201 is improved.
Preferably, the 1st impurity concentration impurity concentration more all than other is low in the 1st to the n-th impurity concentration.This means that
N-shaped system of crystallization membrane silicon layer 106a of the impurity concentration than the 1st of 2nd to the n-th N-shaped system of crystallization membrane silicon layer 106b~106f
Impurity concentration is high.By with higher impurity concentration, for making the 2nd to the n-th N-shaped system of crystallization membrane silicon layer 106b~106f
The heat treatment temperature that fully crystallizes of each layer become than for making the 1st N-shaped system of crystallization membrane silicon layer 106a fully
The heat treatment temperature of crystallization is low.Thereby, it is possible to make the 2nd to the n-th N-shaped system of crystallization thin while adequately being crystallized
The heat treatment temperature of N-shaped system of crystallization membrane silicon layer 106a of each layer of the heat treatment temperature of film silicon layer 106b~106f than the 1st
It is low.Therefore, the 1st n when forming the 2nd to the n-th N-shaped system of crystallization membrane silicon layer 106b~106f, as established layer
Producible heat deterioration is suppressed in type system of crystallization membrane silicon layer 106a.Therefore, it can be improved the property of solar battery 201
Energy.
Preferably, each concentration of the impurity concentration of kth (n >=k >=2) is more miscellaneous than kth -1 in the 1st to the n-th impurity concentration
Matter concentration is high.By with higher impurity concentration, for crystallizing the N-shaped system of crystallization membrane silicon layer 106 of kth fully
Heat treatment temperature becomes lower than the heat treatment temperature for crystallizing the N-shaped system of crystallization membrane silicon layer 106 of kth -1 fully.
Thereby, it is possible to make the heat treatment temperature of the N-shaped system of crystallization membrane silicon layer 106 of kth than while adequately being crystallized
The heat treatment temperature of the N-shaped system of crystallization membrane silicon layer 106 of k-1 is low.It is thin in the N-shaped system of crystallization for forming kth (n >=k >=2) as a result,
At each layer of film silicon layer 106, producible heat is bad in the N-shaped system of crystallization membrane silicon layer 106 of the kth -1 as established layer
Change is suppressed.Therefore it can be improved the performance of solar battery 201.In addition, by being utilized in N-shaped system of crystallization membrane silicon layer 106
The carrier taking-up generated of the light of absorption becomes easy.
If keeping each layer of impurity concentration of N-shaped system of crystallization membrane silicon layer 106 identical, due to each layer crystallization when
Heat treatment, to established layer apply necessity more than thermic load, therefore characteristic be easy significantly deteriorate.It is negative in order to mitigate heat
Lotus crystallizes and is not sufficiently carried out, thus field effect if reducing heat treatment temperature or reducing heat treatment number
The passivation effect of generation dies down.In addition, taking off the hydrogen in N-shaped system of crystallization membrane silicon layer 106 fully not over heat treatment
From.Therefore, carrying out behind, in the process of heating, be easy to happen film stripping.Therefore, as a result, become unable to remain high
Open-circuit voltage.
Preferably, each layer of the 1st to the n-th N-shaped system of crystallization membrane silicon layer 106a~106f contains phosphorus atoms conduct and mixes
Miscellaneous dose.As a result, by changing phosphorus concentration, optimal heat treatment temperature can be easily controlled.
Preferably, the 1st impurity concentration is 1 atom % or less.Thereby, it is possible to inhibit the 1st N-shaped system of crystallization membrane silicon layer
The dopant of 106a breaks through the phenomenon that the 1st tunnel oxide 104a.Therefore, it is able to suppress the 1st N-shaped system of crystallization membrane silicon layer
The dopant of 106a reaches N-shaped monocrystalline silicon substrate 100 in large quantities.
For rear electrode 111, it is set on the back side 100B of N-shaped monocrystalline silicon substrate 100 via stepped construction ST.
For stepped construction ST, not instead of only 1 group of tunnel oxide and N-shaped system of crystallization membrane silicon layer, the tunnel with multiple groups
Road oxide skin(coating) 104 and N-shaped system of crystallization membrane silicon layer 106.Thereby, it is possible to improve passivation effect.In addition, can further suppress
Rear electrode 111 is corroded to N-shaped monocrystalline silicon substrate 100.Therefore, the N-shaped monocrystalline silicon as caused by the erosion can be further suppressed
The damage of substrate 100.Therefore, high open-circuit voltage can more reliably be obtained.
If only 1 group of tunnel oxide 104 and N-shaped system of crystallization membrane silicon layer 106 is only arranged, only rely on by means of rear electrode
111 due to burn caused by rear electrode 111 erosion and break through 1 N-shaped system of crystallization membrane silicon layer 106, just reach and N-shaped list
The tunnel oxide 104 that crystal silicon substrate 100 directly connects.In turn, it only relies on and breaks through the tunnel oxide by means of rear electrode 111
104, just reach N-shaped monocrystalline silicon substrate 100.As a result, open-circuit voltage reduces due to compound increase.Even if rear electrode
The direct erosion of N-shaped monocrystalline silicon substrate 100 is suppressed caused by 111, the influence of the increase of recombination velocity is also easy wave
And to the interface of N-shaped monocrystalline silicon substrate 100, therefore, it is difficult to the deteriorations of rejection characteristic.In addition, it occurs in order to prevent, it is assumed that make n
Type system of crystallization membrane silicon layer 106 thickens, then the compound increase in N-shaped system of crystallization membrane silicon layer 106, therefore open-circuit voltage reduces.
It is explained, light-receiving surface electrode 110 is separated by with N-shaped monocrystalline silicon substrate 100 by n-type impurity diffusion layer 103.With regard to p-type
For the film thickness of impurity diffusion layer 103, film thickness of 106 each layers than N-shaped system of crystallization membrane silicon layer is big, and usually hundreds of nm are left
It is right.Therefore, because corrode, light-receiving surface electrode 110 reach N-shaped monocrystalline silicon substrate 100 a possibility that it is smaller.In addition, in light
Face electrode 110 contains the Al in the case where aluminium (Al) atom, spread from light-receiving surface electrode 110 into n-type impurity diffusion layer 103
Atom is functioned as receptor, and thus passivation effect is improved.Therefore, just for improving the stepped construction of passivation effect
For ST, it is preferably configured in opposite with face (being light-receiving surface 100A in present embodiment) of n-type impurity diffusion layer 103 is provided with
On face (being back side 100B in present embodiment).
The manufacturing method of solar battery 201 according to the present embodiment, it is preferable that just form the 2nd to the n-th N-shaped knot
For temperature used in the process of crystallographic system membrane silicon layer 106b~106f is each, than the N-shaped system of crystallization thin film silicon for forming the 1st
Temperature used in the process of layer 106a is low.It can be sent out when the 2nd to the n-th N-shaped system of crystallization membrane silicon layer 106b~106f as a result,
The heat deterioration of the N-shaped system of crystallization membrane silicon layer 106a of raw the 1st is suppressed.Therefore it can be improved the property of solar battery 201
Energy.
It is highly preferred that used in the process for just forming the N-shaped system of crystallization membrane silicon layer 106 of kth (n >=k >=2) is each
For temperature, temperature used in the process than the N-shaped system of crystallization membrane silicon layer 106 for forming kth -1 is low.Kth is formed as a result,
N-shaped system of crystallization membrane silicon layer 106 when generable kth -1 the heat deterioration of N-shaped system of crystallization membrane silicon layer 106 be suppressed.
Therefore, whole heat deteriorations of the 1st to the n-th N-shaped system of crystallization membrane silicon layer 106a~106f are suppressed.Therefore, Neng Gouti
The performance of high solar battery 201.
2 > of < embodiment
Referring to Fig.1 3, in the present embodiment, step 120V is carried out instead of the step S120 (Fig. 2) in embodiment 1.
In the step s 120, then the depositing n-type system of crystallization membrane silicon layer in tunnel oxide 104 makes its crystallization, thus shape
At N-shaped system of crystallization membrane silicon layer 106.On the other hand, in step 120V, the depositing n-type system of crystallization in tunnel oxide 104
Membrane silicon layer 106.That is, silicon layer is directly deposited with the state of system of crystallization.It therefore, will in the manufacturing method of present embodiment
Process is just transferred to the composition of Fig. 7 by the composition of Fig. 6 from being constructed without for Fig. 5, and then process does not pass through the composition of Fig. 8 just
It is transferred to the composition of Fig. 9.
For the direct deposition of above-mentioned N-shaped system of crystallization membrane silicon layer 106, such as can be by pressing chemical deposition
(Low Pressure Chemical Vapor Deposition:LPCVD) is carried out.N-shaped monocrystalline silicon substrate when with regard to deposition
For 100 temperature (depositing temperature), preferably 600 DEG C or more and 900 DEG C or less Zuo You.With regard to multiple N-shaped system of crystallization membrane silicon layers
For temperature used in 106 formation, do not need all it is identical, be preferably carried out similarly control with the situation of embodiment 1.
In the present embodiment, above-mentioned depositing temperature is equivalent to temperature used in the formation of N-shaped system of crystallization membrane silicon layer 106.
The effect substantially same with embodiment 1 is also obtained by present embodiment.In turn, it can omit for crystallizing
Heat treatment procedure (step S122 (Fig. 2)).In the case where omitting heat treatment procedure, in addition to N-shaped system of crystallization membrane silicon layer 106
In addition, tunnel oxide 104 is also formed by sedimentation, thus, it is possible to further increase productivity.With regard to utilizing sedimentation
For the formation of tunnel oxide 104, for example, SiH can be used4Gas and N2O gas carries out.
3 > of < embodiment
(composition)
Referring to Fig.1 4, in the solar battery 202 (photogenic voltage element) of present embodiment, stepped construction ST is configured
On the light-receiving surface 100A of N-shaped monocrystalline silicon substrate 100.Specifically, the 1st tunnel oxide 104a of stepped construction ST is configured
On the light-receiving surface 100A of N-shaped monocrystalline silicon substrate 100.In addition, configuring n-type impurity diffusion layer 103 (emitter layer) in N-shaped list
On the back side 100B of crystal silicon substrate 100.In other words, solar battery 202 is different from solar battery 201 (Fig. 1), has back hair
Emitter structure.
In addition, for solar battery 202, instead of light receiving side dielectric layer 108 and antireflection film 109 (Fig. 1)
With back side dielectric layer 108A and back side protective film 109A.In the present embodiment, light-receiving surface electrode 110 is by protective film
107 penetrate through and reach stepped construction ST.Light-receiving surface electrode 110 is electrically connected with stepped construction ST as a result,.In addition, rear electrode 111
Back side protective film 109A and back side dielectric layer 108A perforation is reached into n-type impurity diffusion layer 103.Back side electricity as a result,
Pole 111 is electrically connected with n-type impurity diffusion layer 103.
It should be noted that about composition other than the above, due to roughly the same with the above-mentioned composition of embodiment 1,
Same appended drawing reference is marked for same or corresponding element, its explanation is not repeated.
(manufacturing method)
Next, for the manufacturing method of solar battery 202, it is being illustrated referring to flow chart (Figure 15).
6 and Figure 17 referring to Fig.1 forms n-type impurity diffusion layer 103 in step S100 (Figure 15).In addition to what is formed
Face is not the light-receiving surface 100A of N-shaped monocrystalline silicon substrate 100 but other than the 100B of the back side, carries out process (Fig. 3 with embodiment 1
And Fig. 4) same process.
8~Figure 23 referring to Fig.1 is repeated by the n times of the group of step S110 and S120 (Figure 15), forms stepped construction ST.
In addition to the face formed be not the back side 100B of N-shaped monocrystalline silicon substrate 100 but other than light-receiving surface 100A, carry out and embodiment party
The same process of process (Fig. 5~Figure 10) of formula 1.It is explained, as variation, step S120 can be replaced and carry out step
S120V (Figure 13: embodiment 2).That is, by that can omit silicon layer Direct precipitation for crystallizing in the state of system of crystallization
Heat treatment procedure.
Next, using hydrofluoric acid by n-type impurity diffusion layer 103 bsg film 101 and NSG film 102 (Figure 10) remove.
Removing method and embodiment 1 are same.
Referring to Figure 24, next, forming protective film 107 on stepped construction ST in step S130 (Figure 13).In this reality
It applies due to configuring protective film 107 in light receiving side in mode, therefore, it is desirable to protective films 107 to be made by low light absorption material.Choosing
The material and film thickness for selecting protective film 107 are so that obtain optimal reflection for sunlight spectrum as single layer or laminate structure
Rate.For example, making film thickness 60nm or more and less than 100nm or so using the monofilm of silicon nitride.
Referring to Figure 25, next, sequentially forming back side on n-type impurity diffusion layer 103 in step S140W (Figure 13)
Dielectric layer 108A and back side protective film 109A.
Next, in step S150 (Figure 15), substantially samely with embodiment 1 (Figure 12), in N-shaped monocrystalline silicon substrate
Light-receiving surface electrode 110 and rear electrode 111 are printed via several components respectively on 100 light-receiving surface 100A and back side 100B.
In the present embodiment, at the moment, light-receiving surface electrode 110 and rear electrode 111 are respectively printed at protective film 107 and the back side
On the protective film 109A of side.
Referring again to Figure 14, in step S160 (Figure 15), substantially samely with embodiment 1 (Fig. 1), light-receiving surface electricity is carried out
The firing of the electrode of pole 110 and rear electrode 111.In the present embodiment, in firing process, pass through light-receiving surface electrode 110
Protective film 107 is etched by glass particle, and thus light-receiving surface electrode 110 is corroded to N-shaped system of crystallization membrane silicon layer 106f.By
This, light-receiving surface electrode 110 is electrically connected with N-shaped system of crystallization membrane silicon layer 106f.Similarly, pass through the glass grain of rear electrode 111
Back side protective film 109A and back side dielectric layer 108A are etched by son, and rear electrode 111 is to n-type impurity diffusion layer
103 corrode.Rear electrode 111 is electrically connected with n-type impurity diffusion layer 103 as a result,.
By the above, obtaining solar battery 202.
(effect)
The effect substantially same with embodiment 1 is also obtained by present embodiment.In turn, in n-type impurity diffusion layer 103
The electrode of upper setting is not light-receiving surface electrode 110 but rear electrode 111.For rear electrode 111, shading can not be made to damage
It loses and increases and the gate electrode with thin space.Allow to further increase the resistance of n-type impurity diffusion layer 103 as a result,.It therefore can
Improve passivation effect.
In the respective embodiments described above, each layer as multiple system of crystallization thin film semiconductive layers, using there is N-shaped system of crystallization
Membrane silicon layer.Therefore, if each layer of conductivity type of system of crystallization thin film semiconductive layer is defined as " the 1st conductivity type ", the 1st
Conductivity type is N-shaped.But the 1st conductivity type is not limited to N-shaped, is also possible to p-type.In addition, in the respective embodiments described above,
As semiconductor substrate, using there is N-shaped monocrystalline silicon substrate.Therefore, the conductivity type of semiconductor substrate is N-shaped.But it is semiconductor-based
The conductivity type of plate is not limited to N-shaped, is also possible to p-type.In other words, the conductivity type of semiconductor substrate can be the 1st conductivity type
Any one of the 2nd opposite conductivity type with the 1st conductivity type.
For the present invention, it within the scope of the invention can freely combine each embodiment or by each embodiment
It deforms, omit as one sees fit.The present invention is illustrated in detail, but above-mentioned explanation is all in all aspects illustration, this
It's not limited to that for invention.It should be understood that the countless changes not yet illustrated can be envisioned in the case where not departing from the scope of the present invention
Shape example.
The explanation of appended drawing reference
201,202 solar batteries (photogenic voltage element), ST stepped construction, 100n type monocrystalline silicon substrate are (semiconductor-based
Plate), 100A light-receiving surface, the back side 100B, 101BSG film (impurity diffusion source), 102NSG film (cap rock), 103p type impurity diffusion layer
(emitter layer), 104 tunnel oxides, the 1st~the 6th tunnel oxide of 104a~104f, 105a, 105b's the 1st and the 2nd
N-shaped amorphous film silicon layer, 106n type system of crystallization membrane silicon layer (system of crystallization thin film semiconductive layer), 106a~106f the 1st~the 6th
N-shaped system of crystallization membrane silicon layer (the 1st~the 6th system of crystallization thin film semiconductive layer), 107 protective films, 108 light receiving side dielectrics
Layer, 108A back side dielectric layer, 109 antireflection films, 109A back side protective film, 110 light-receiving surface electrodes, 111 rear electrodes.
Claims (7)
1. a kind of photogenic voltage element (201,202), has:
Semiconductor substrate (100), with any in the 1st conductivity type and the 2nd conductivity type opposite with the 1st conductivity type
Person；
Stepped construction (ST) has the multiple tunnel oxides (104) being arranged alternately on the semiconductor substrate (100)
And multiple system of crystallization thin film semiconductive layers (106)；With
Protective film (107) is arranged on the stepped construction (ST), is made by dielectric,
The multiple tunnel oxide (104) includes the 1st to the n-th tunnel configured in order on the semiconductor substrate (100)
Road oxide skin(coating), the 1st tunnel oxide are abutted with the semiconductor substrate (100), and for the semiconductor substrate
(100) minority carrier has potential barrier；
Each layer of the multiple system of crystallization thin film semiconductive layer (106) has the 1st conductivity type, and the multiple system of crystallization is thin
Film semiconductor layer (106) includes the 1st to the n-th system of crystallization thin film semiconductor configured in order on the semiconductor substrate (100)
Layer；
Each layer of the multiple system of crystallization thin film semiconductive layer (106) has 1 atom % in 50% or more thickness range
Average hydrogen content below, and with 50% or more percent crystallization in massecuite.
2. photogenic voltage element (201,202) according to claim 1, which is characterized in that the 1st to the n-th system of crystallization
Thin film semiconductive layer is respectively provided with the 1st to the n-th impurity concentration, the 1st impurity concentration ratio described in the 1st to the n-th impurity concentration
Other arbitrary impurity concentrations are all low.
3. photogenic voltage element (201,202) according to claim 1, which is characterized in that the 1st to the n-th system of crystallization
Thin film semiconductive layer is respectively provided with the 1st to the n-th impurity concentration, the impurity of kth (n >=k >=2) in the 1st to the n-th impurity concentration
Concentration is higher than the impurity concentration of kth -1 respectively.
4. photogenic voltage element (201,202) according to any one of claim 1-3, wherein the 1st to the n-th knot
Each layer of crystallographic system thin film semiconductive layer contains phosphorus atoms as dopant.
5. photogenic voltage element (201,202) described in any one of -4 according to claim 1, which is characterized in that the described 1st is miscellaneous
Matter concentration is 1 atom % or less.
6. a kind of manufacturing method of photogenic voltage element (201,202), has:
The process for forming stepped construction (ST), the stepped construction (ST), which includes, to be had the 1st conductivity type and is leading with the described 1st
The multiple tunnel oxides being alternately arranged on the semiconductor substrate (100) of any one of the 2nd opposite conductivity type of electric type
(104) and multiple system of crystallization thin film semiconductive layers (106)；With
The process that the protective film (107) made by dielectric is formed on the stepped construction (ST),
The multiple tunnel oxide (104) includes the 1st to the n-th tunnel configured in order on the semiconductor substrate (100)
Road oxide skin(coating), the 1st tunnel oxide are abutted with the semiconductor substrate (100), and for the semiconductor substrate
(100) minority carrier has potential barrier；
Each layer of the multiple system of crystallization thin film semiconductive layer (106) has the 1st conductivity type, and the multiple system of crystallization is thin
Film semiconductor layer (106) includes the 1st to the n-th system of crystallization thin film semiconductor configured in order on the semiconductor substrate (100)
Layer, the 1st to the n-th system of crystallization thin film semiconductive layer are respectively provided with the 1st to the n-th impurity concentration, and the 1st to the n-th impurity is dense
1st impurity concentration described in degree is all lower than other arbitrary impurity concentrations；
The process for forming the stepped construction (ST) includes to sequentially form the work of the 1st to the n-th system of crystallization thin film semiconductive layer
Sequence is formed in each layer of process of the 1st to the n-th system of crystallization thin film semiconductive layer, and the system of crystallization of formation the 2nd to the n-th is thin
Process of the temperature used in each process of the process of film semiconductor layer than forming the 1st system of crystallization thin film semiconductive layer
Used in temperature it is low.
7. a kind of manufacturing method of photogenic voltage element (201,202), has:
The process for forming stepped construction (ST), the stepped construction (ST), which includes, to be had the 1st conductivity type and is leading with the described 1st
The multiple tunnel oxides being alternately arranged on the semiconductor substrate (100) of any one of the 2nd opposite conductivity type of electric type
(104) and multiple system of crystallization thin film semiconductive layers (106)；With
The process that the protective film (107) made by dielectric is formed on the stepped construction (ST),
The multiple tunnel oxide (104) includes the 1st to the n-th tunnel configured in order on the semiconductor substrate (100)
Road oxide skin(coating), the 1st tunnel oxide are abutted with the semiconductor substrate (100), and for described semiconductor-based
The minority carrier of plate (100) has potential barrier,
Each layer of the multiple system of crystallization thin film semiconductive layer (106) has the 1st conductivity type, and the multiple system of crystallization is thin
Film semiconductor layer (106) includes the 1st to the n-th system of crystallization thin film semiconductor configured in order on the semiconductor substrate (100)
Layer, the 1st to the n-th system of crystallization thin film semiconductive layer are respectively provided with the 1st to the n-th impurity concentration, and the 1st to the n-th impurity is dense
The impurity concentration of kth (n >=k >=2) is higher than the impurity concentration of kth -1 respectively in degree,
The process for forming the stepped construction (ST) includes to sequentially form the work of the 1st to the n-th system of crystallization thin film semiconductive layer
Sequence is formed in each layer of process of the 1st to the n-th system of crystallization thin film semiconductive layer, and the crystallization of kth (n >=k >=2) is formed
It is system of crystallization thin film semiconductive layer of the temperature used in each process of the process of thin film semiconductive layer than forming kth -1
Temperature used in process is low.
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| PCT/JP2017/017339 WO2017208729A1 (en) | 2016-06-01 | 2017-05-08 | Photovoltaic element and method for manufacturing same |
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| CN110071182A (en) * | 2019-05-23 | 2019-07-30 | 泰州中来光电科技有限公司 | A kind of the passivation solar battery and preparation method of multiple tunnel junction layer |
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| CN114551606A (en) | 2021-09-16 | 2022-05-27 | 晶科能源(海宁)有限公司 | Solar cell and photovoltaic module |
| CN113838641A (en) * | 2021-10-18 | 2021-12-24 | 江西明正变电设备有限公司 | Transformer with auxiliary mounting structure |
| KR102499055B1 (en) * | 2022-01-05 | 2023-02-13 | 청주대학교 산학협력단 | Solar cell with tunneling quantum wells structures directly connected to semiconductor pn junction structures |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101461602B1 (en) * | 2012-06-25 | 2014-11-20 | 청주대학교 산학협력단 | Quantum well structured solar cells and method for manufacturing same |
| KR102219804B1 (en) * | 2014-11-04 | 2021-02-24 | 엘지전자 주식회사 | Solar cell and the manufacturing mathod thereof |
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2017
- 2017-05-08 WO PCT/JP2017/017339 patent/WO2017208729A1/en active Application Filing
- 2017-05-08 JP JP2018520739A patent/JP6537722B2/en not_active Expired - Fee Related
- 2017-05-08 CN CN201780024559.XA patent/CN109362238A/en not_active Withdrawn
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110071182A (en) * | 2019-05-23 | 2019-07-30 | 泰州中来光电科技有限公司 | A kind of the passivation solar battery and preparation method of multiple tunnel junction layer |
| CN110071182B (en) * | 2019-05-23 | 2024-01-30 | 泰州中来光电科技有限公司 | Passivation solar cell with multilayer tunnel junction and preparation method |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201804628A (en) | 2018-02-01 |
| JP6537722B2 (en) | 2019-07-03 |
| JPWO2017208729A1 (en) | 2018-08-30 |
| TWI632691B (en) | 2018-08-11 |
| WO2017208729A1 (en) | 2017-12-07 |
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Application publication date: 20190219 |