CN109361397A - A kind of DAC applied to self-tolerant TP controlling of sampling - Google Patents
A kind of DAC applied to self-tolerant TP controlling of sampling Download PDFInfo
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- CN109361397A CN109361397A CN201811504304.6A CN201811504304A CN109361397A CN 109361397 A CN109361397 A CN 109361397A CN 201811504304 A CN201811504304 A CN 201811504304A CN 109361397 A CN109361397 A CN 109361397A
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- nand gate
- dac
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- input terminal
- tolerant
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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- Theoretical Computer Science (AREA)
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Abstract
The invention discloses a kind of DAC applied to self-tolerant TP controlling of sampling, it includes 6 two input nand gate NAND1~NAND6, a phase inverter INV, an adjustable resistance R, three switch S1~S3 that self-tolerant TP sample circuit, which includes CA, ADC, CB capacitor, switch P1~P10, the DAC,.Circuit framework of the invention is more succinct, corresponding to chip area it is smaller.
Description
Technical field
The present invention relates to electronic circuit fields, and in particular to a kind of DAC applied to self-tolerant TP controlling of sampling.
Background technique
Self-tolerant TP passes through CA to touch panel by using highly sensitive capacitance sensing technology, in conjunction with the control of timing
On touch point carry out real-time acquisition and treatment.CA is in the process for carrying out real-time acquisition and treatment to the touch point on touch panel
In, need the control for carrying out charge and discharge to CB capacitor by DAC then to pass through ADC to realize to the Quantitative yield of sampled point
The CA analog quantity converted is changed into digital quantity.
It is by inputting digital control signal that the function of DAC, which is realized in traditional sense, and then DAC is according to corresponding number
Signal is controlled by corresponding analog output.It is then to need to carry out CB capacitor by DAC in the TP sampling process of self-tolerant
The function of charge and discharge, for basic function as shown in Figure 1, by taking the DAC of a 5-bits as an example, the input signal of DAC is DAC < 4:0
>, according to the locating operating mode of self-tolerant TP sampling, DAC is needed to export a slope analog signal from 0V to VREF (at this time
Switch P4 closure, switch P5 are disconnected, and also just the anode of corresponding CA input at this time meets VREF), or DAC is needed to export one
(switch P5 is closed slope analog signal from VREF to 0V at this time, and switch P4 is disconnected, the anode that also just corresponding CA at this time is inputted
Meet VSS).Based on this demand, numerical portion just needs to carry out the DAC<4:0>of 5-bits traversal input, that is, opens when being in
It closes P4 to be closed, under the operating mode that switch P5 is disconnected, needs gradually to traverse the DAC<4:0>of 5-bits from " 00000 "
" 11111 " amount to 31 steps；And be closed when in switch P5, under the operating mode that switch P4 is disconnected, then need to 5-bits's
DAC<4:0>gradually traverses " 00000 " from " 11111 ", equally total 31 steps.
However traditional DAC can be seen that from overall architecture such as Fig. 2, mainly include three parts: resistance string partial pressure
(generate 2nA dividing point), decoding logic (generates 2nA control signal), MUX selection (passes through 2nA control signal behavior 2nA point
One of them in pressure point passes out to DAC_OUT), control signal is as follows:
The making of DAC_EN --- DAC can control signal, indicate enabled for " 1 "；
The reference voltage of VREF --- DAC；
The reference ground of VSS --- DAC；
DAC<n-1,0>--- the DAC digital code value of n-bits inputs；
The output signal of DAC_OUT --- DAC；
The DAC of conventional architectures needs first to carry out voltage division processing according to the digit of DAC to reference voltage, then also needs to pass through
The numeral input signal of n DAC is decoded as 2 by logic decodingnThe internal control signal of position passes through MUX selection 2 laternA point
A dividing point in pressure point is sent to the output of DAC.And for the sampling application scenarios of self-tolerant TP, the reality of such DAC
Existing its circuit design of mode is complex.
Summary of the invention
Problem to be solved by this invention is under the premise of realizing DAC function using a kind of more succinct more efficiently
Mode realizes the function, proposes a kind of DAC applied to self-tolerant TP controlling of sampling.
The technical solution adopted by the present invention is that:
A kind of DAC applied to self-tolerant TP controlling of sampling, self-tolerant TP sample circuit include CA, ADC, CB capacitor,
Switch P1~P10, it is characterised in that: the DAC includes NAND gate NAND1~NAND6 of 6 two inputs, a phase inverter
INV, an adjustable resistance R, three switch S1~S3；
The input terminal of the phase inverter INV connects DAC_EN signal, and the output end of phase inverter INV is DAC_ENB, and even
It is connected to one of input terminal of NAND gate NAND1 and one of input terminal of NAND gate NAND5, NAND gate NAND1's
Another input terminal is then connected with switch P5, and another input terminal of NAND gate NAND5 is then connected with switch P4, NAND gate
One of input terminal of NAND2 is connected with switch P4, and another input terminal of NAND gate NAND2 is then connected with DAC_EN, with
One of input terminal of NOT gate NAND4 is connected with switch P5, another input terminal of NAND gate NAND4 then with DAC_EN phase
Even, the output end of NAND gate NAND1 is then connected with one of input terminal of NAND gate NAND3, and other the one of NAND gate NAND3
A input terminal is then connected with the output end of NAND gate NAND2, the output end of NAND gate NAND4 then with NAND gate NAND6 wherein
One input terminal is connected, and another input terminal of NAND gate NAND6 is then connected with the output end of NAND gate NAND5, NAND gate
The output end of NAND3 then directly controls switch S1, and the output end of NAND gate NAND6 then directly controls switch S2, and the one of switch S1
One end of the other end connection adjustable resistance of end connection VREF, switch S1, while being connect with one end of switch S2, switch S2's
Other end connects VSS, and the other end of adjustable resistance is then wherein one end of DAC_OUT and connection switch S3, switch S3's
Other end then connects one end of CB capacitor, and switch S3 is controlled by DAC_EN.
The invention has the advantages that
Circuit framework of the invention is more succinct, corresponding to chip area it is smaller.
Detailed description of the invention
Fig. 1 is functional schematic of traditional DAC in self-tolerant TP sampling process.
Fig. 2 is the integrated stand composition of traditional DAC.
Fig. 3 is the connection schematic diagram that DAC of the invention is applied to self-tolerant TP sample circuit.
Fig. 4 is the equivalent schematic of adjustable resistance R.
Fig. 5 is self-tolerant TP sample circuit DAC output waveform figure.
Specific embodiment
As shown in figure 3, a kind of DAC applied to self-tolerant TP controlling of sampling, self-tolerant TP sample circuit include CA,
ADC, CB capacitor, switch P1~P10, DAC include 6 two input NAND gate NAND1~NAND6, a phase inverter INV,
One adjustable resistance R, three switch S1~S3；The input terminal of phase inverter INV connects DAC_EN signal, the output of phase inverter INV
End is DAC_ENB, and be connected to NAND gate NAND1 one of input terminal and NAND gate NAND5 one of them is defeated
Enter end, another input terminal of NAND gate NAND1 is then connected with switch P5, another input terminal of NAND gate NAND5 then with open
It closes P4 to be connected, one of input terminal of NAND gate NAND2 is connected with switch P4, and another input terminal of NAND gate NAND2 is then
It is connected with DAC_EN, one of input terminal of NAND gate NAND4 is connected with switch P5, another input of NAND gate NAND4
End is then connected with DAC_EN, and the output end of NAND gate NAND1 is then connected with one of input terminal of NAND gate NAND3, and non-
Door NAND3 another input terminal be then connected with the output end of NAND gate NAND2, the output end of NAND gate NAND4 then with
One of input terminal of NOT gate NAND6 is connected, and another input terminal of NAND gate NAND6 is then defeated with NAND gate NAND5
Outlet is connected, and the output end of NAND gate NAND3 then directly controls switch S1, and the output end of NAND gate NAND6 then directly controls out
S2 is closed, one end of switch S1 connects VREF, and the other end of switch S1 connects one end of adjustable resistance, while one with switch S2
End connection, the other end of switch S2 connect VSS, and the other end of adjustable resistance is then its of DAC_OUT and connection switch S3
Middle one end, the other end of switch S3 then connect one end of CB capacitor, and switch S3 is controlled by DAC_EN.
It is illustrated in figure 4 the equivalent schematic of adjustable resistance R, it can be seen that by the number for configuring n DAC<n-1:0>
Word logic signal to realize the function of configuration adjustable resistance resistance value, and controls the charge/discharge speed of CB capacitor in turn.
In the TP sampling process of self-tolerant, it is desirable to which the output waveform of obtained DAC is as shown in Figure 5, it can be seen that when certainly
Appearance formula TP sampling is closed in P4, and when P5 disconnects this mode, also just the anode of corresponding CA input at this time meets VREF, in DAC_
When EN is low level, DAC_OUT 0V, after DAC_EN becomes high level, DAC_OUT start gradually to get higher from 0V to
VREF.The function is that the circuit that patent is proposed through the invention is realized, can be with from the circuit that the invention patent is proposed
Find out, work as P4=1, when P5=0, DAC_EN=0, switch S1 is disconnected at this time, switch S2 closure, switch S3 disconnection, correspondence DAC_
OUT is 0V.Working as P4=1, after P5=0, DAC_EN become high level from low level, switch S1 is closed at this time, switch S2 disconnection,
Simultaneous Switching S3 closure, DAC_OUT voltage start to gradually rise to VREF voltage from 0V, fill to realize to CB capacitor
Electricity, and TP sampling is realized in turn.Furthermore the charging rate of CB capacitor can be realized by configuring the resistance value of adjustable resistance.
When self-tolerant TP sampling is closed in P5, when P4 disconnects this mode, also with regard to the anode of corresponding CA input at this time
Meet VSS, DAC_EN be low level when, DAC_OUT VREF, after DAC_EN becomes high level, DAC_OUT start from
VREF is gradually lower to 0V.The function is that the circuit that patent is proposed through the invention is realized, is proposed from the invention patent
Circuit in as can be seen that work as P4=0, when P5=1, DAC_EN=0, switch S2 is disconnected at this time, and switch S1 is closed, and switch S3 breaks
It opens, corresponding DAC_OUT is pulled high to VREF.Work as P4=0, after P5=1, DAC_EN become high level from low level, opens at this time
S2 closure is closed, switch S1 is disconnected, and Simultaneous Switching S3 closure, DAC_OUT voltage starts to gradually decrease to 0V voltage from VREF, thus
Realization discharges to CB capacitor, and realizes TP sampling in turn.Furthermore the velocity of discharge of CB capacitor can also be adjustable by configuring
The resistance value of resistance is realized.
Term involved in the present invention is explained:
TP --- touch panel；
DAC --- digital analog converter；
CA --- charge amplifier；
The base capacitor of CB capacitor --- CA；
ADC --- analog-digital converter.
Claims (1)
1. a kind of DAC applied to self-tolerant TP controlling of sampling, self-tolerant TP sample circuit includes CA, ADC, CB capacitor, opens
Close P1~P10, it is characterised in that: the DAC includes NAND gate NAND1~NAND6 of 6 two inputs, a phase inverter
INV, an adjustable resistance R, three switch S1~S3；
The input terminal of the phase inverter INV connects DAC_EN signal, and the output end of phase inverter INV is DAC_ENB, and is connected to
One of input terminal of NAND gate NAND1 and one of input terminal of NAND gate NAND5, NAND gate NAND1's is another
A input terminal is then connected with switch P5, and another input terminal of NAND gate NAND5 is then connected with switch P4, NAND gate NAND2's
One of input terminal is connected with switch P4, and another input terminal of NAND gate NAND2 is then connected with DAC_EN, NAND gate
One of input terminal of NAND4 is connected with switch P5, and another input terminal of NAND gate NAND4 is then connected with DAC_EN, with
The output end of NOT gate NAND1 is then connected with one of input terminal of NAND gate NAND3, and another of NAND gate NAND3 is defeated
Enter end be then connected with the output end of NAND gate NAND2, the output end of NAND gate NAND4 then with NAND gate NAND6 one of them
Input terminal is connected, and another input terminal of NAND gate NAND6 is then connected with the output end of NAND gate NAND5, NAND gate NAND3
Output end then directly control switch S1, the output end of NAND gate NAND6 then directly controls switch S2, one end connection of switch S1
One end of the other end connection adjustable resistance of VREF, switch S1, while being connect with one end of switch S2, other the one of switch S2
End connection VSS, the other end of adjustable resistance are then wherein one end of DAC_OUT and connection switch S3, other the one of switch S3
End then connects one end of CB capacitor, and switch S3 is controlled by DAC_EN.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811504304.6A CN109361397B (en) | 2018-12-10 | 2018-12-10 | DAC applied to self-contained TP sampling control |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811504304.6A CN109361397B (en) | 2018-12-10 | 2018-12-10 | DAC applied to self-contained TP sampling control |
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| CN109361397A true CN109361397A (en) | 2019-02-19 |
| CN109361397B CN109361397B (en) | 2022-04-19 |
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| CN201811504304.6A Active CN109361397B (en) | 2018-12-10 | 2018-12-10 | DAC applied to self-contained TP sampling control |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012169860A (en) * | 2011-02-14 | 2012-09-06 | Hitachi High-Technologies Corp | High resolution digital-analog conversion device and method |
| US20130162613A1 (en) * | 2011-12-23 | 2013-06-27 | Semiconductor Energy Laboratory Co., Ltd. | Signal Converter Circuit, Display Device, and Electronic Device |
| CN104796148A (en) * | 2015-05-19 | 2015-07-22 | 中国电子科技集团公司第二十四研究所 | High-speed low-power-loss successive approximation type analog-digital converter |
| CN105141313A (en) * | 2015-09-28 | 2015-12-09 | 成都领芯微电子科技有限公司 | SAR ADC adopting low resolution DAC capacitor array and application method thereof |
| CN107835021A (en) * | 2017-11-24 | 2018-03-23 | 西安交通大学 | A kind of asynchronous sequential control circuit of Variable delay and control method |
-
2018
- 2018-12-10 CN CN201811504304.6A patent/CN109361397B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012169860A (en) * | 2011-02-14 | 2012-09-06 | Hitachi High-Technologies Corp | High resolution digital-analog conversion device and method |
| US20130162613A1 (en) * | 2011-12-23 | 2013-06-27 | Semiconductor Energy Laboratory Co., Ltd. | Signal Converter Circuit, Display Device, and Electronic Device |
| CN104796148A (en) * | 2015-05-19 | 2015-07-22 | 中国电子科技集团公司第二十四研究所 | High-speed low-power-loss successive approximation type analog-digital converter |
| CN105141313A (en) * | 2015-09-28 | 2015-12-09 | 成都领芯微电子科技有限公司 | SAR ADC adopting low resolution DAC capacitor array and application method thereof |
| CN107835021A (en) * | 2017-11-24 | 2018-03-23 | 西安交通大学 | A kind of asynchronous sequential control circuit of Variable delay and control method |
Non-Patent Citations (1)
| Title |
|---|
| 刘海南等: "基于DVS的动态电压转换器设计", 《电子器件》 * |
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