CN109347352B - Cascaded converter submodule capacitor voltage balance control method - Google Patents

Abstract

The invention provides a method for controlling the capacitance-voltage balance of a submodule of a cascaded converter, which comprises the following steps: determining an asynchronous switch period dividing mode of each submodule in the cascaded converter; sequencing the trigger pulses according to the capacitance voltage disturbance quantity of each submodule in the cascaded converter obtained through sampling calculation; sequencing the sampled capacitor voltages of the cascaded converter sub-modules; calculating the unbalance degree of the capacitor voltage of the submodule of the cascade converter; and finally, redistributing the trigger pulses of the cascaded converter submodule. The invention is suitable for various cascade type converters and corresponding working conditions thereof, can efficiently realize the balance control of the sub-module capacitor voltage, and has simple realization and better balance effect.

Description

Cascaded converter submodule capacitor voltage balance control method

Technical Field

The invention relates to the technical field of power electronics, in particular to a method for controlling the capacitance-voltage balance of a submodule of a cascaded converter.

Background

The cascade type converter has good expandable and better output characteristics, and is widely applied to various medium-voltage and high-voltage high-power electric energy conversion occasions, such as flexible direct-current transmission, reactive power compensation devices, energy storage, new energy power generation, motor driving and the like. Due to the fact that the working condition of the cascade converter is complex, the charge-discharge energy, the loss, the capacitance value and the like of the sub-module capacitor are different, the voltage of each sub-module capacitor is prone to being unbalanced, the output performance of the cascade converter is reduced, and even the system cannot work safely and reliably in severe cases, the capacitor voltage must be subjected to balance control.

The modulation method suitable for the cascade converter mainly comprises nearest level approximation modulation (NLC), carrier phase shift pulse width modulation (CPS-PWM) and carrier stack pulse width modulation (PD-PWM). Compared with NLC modulation and PD-PWM modulation, CPS-PWM carrier phase shift modulation has the advantages of better harmonic characteristic, higher response speed, fixed switching frequency and the like, is widely adopted, and is particularly applied to cascaded converters with relatively few modules.

The sub-module capacitance voltage balance control technology suitable for the CPS-PWM carrier phase-shift modulation method at present mainly comprises two types:

1. adding external circuits

According to the method, a common direct current or alternating current bus and an external balancing circuit are constructed, and the capacitor voltages of all the sub-modules are connected to the common bus, so that the sub-module capacitor voltages are automatically balanced. However, each sub-module requires additional hardware circuits, which increases the cost of the device.

2. Trimming voltage modulated wave

According to the method, an additional component obtained by a capacitor voltage balance feedback control loop is superposed on a voltage modulation wave generated by a current control loop to realize balance control of capacitor voltage. However, the superimposed additional component may cause distortion of the modulation wave, which affects the output performance of the device; the parameter setting of the capacitor voltage feedback controller is difficult because of no clear mathematical model; on the other hand, since each submodule needs to be provided with a separate voltage balance controller, the hardware requirement of the controller is increased, and when the number of cascaded converter submodules is increased, the complexity of the control of the cascaded converter submodules is increased.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide a high-efficiency balancing control method for capacitor voltage of submodule of a cascaded converter.

The invention provides a method for controlling the capacitance-voltage balance of submodule of a cascaded converter, which comprises the following steps:

determining an asynchronous switch period dividing mode of each submodule in the cascaded converter;

according to the asynchronous switching period dividing mode of each sub-module in the cascade type converter, carrying out corresponding parameter sampling calculation to obtain the capacitance voltage disturbance quantity of each sub-module, and sequencing the capacitance voltage disturbance quantity of each sub-module in the cascade type converter;

according to the obtained capacitance voltage obtained by parameter sampling calculation of each sub-module in the cascaded converter, sequencing the capacitance voltage of each sub-module in the cascaded converter;

redistributing the trigger pulse of each submodule in the cascaded converter according to a preset judgment condition; wherein the preset judgment condition comprises: any one or any combination of the sorting result of the capacitance voltage disturbance quantities of the sub-modules, the sorting result of the capacitance voltages of the sub-modules, the capacitance voltage unbalance degree of the sub-modules and the difference value of the capacitance voltage disturbance quantities of the sub-modules.

Optionally, determining a non-synchronous switching cycle division manner of each sub-module in the cascaded converter includes:

supposing that one bridge arm of a cascade converter adopting carrier phase shift modulation comprises N cascade submodules, the phase angle difference of adjacent cascade submodules is 2 pi/N, one submodule is arbitrarily selected from the N cascade submodules to be used as a first module, the carrier of the first module is used as a reference carrier and is marked as Tri₁Defining the phase shift angle of the first module as 0; the carriers corresponding to N-1 modules with the phases lagging by 2 pi/N in sequence are respectively marked as Tri₂、Tri₃、…、Tri_N(ii) a The voltage modulation wave corresponding to each submodule is respectively marked as u_m1、u_m2、…、u_mNThe voltage modulation coefficient corresponding to each submodule is recorded as d₁、d₂、…、d_N(ii) a The bridge arm current or the input current of the submodule is marked as I_arm(ii) a The capacitor voltage of each submodule is respectively marked as u_c1、u_c2、…、u_cN(ii) a Defining the switching period of the corresponding sub-module with the time between two adjacent peak values of the respective carrier of each sub-module as; wherein the switching cycles of the sub-modules are synchronous or asynchronous.

Optionally, according to the asynchronous switching cycle division manner of each sub-module in the cascaded converter, performing corresponding parameter sampling calculation to obtain the capacitance voltage disturbance amount of each sub-module, and sorting the capacitance voltage disturbance amounts of each sub-module in the cascaded converter, including:

when the carrier corresponding to each submodule reaches a peak value or a trough, sampling to obtain parameter data of each submodule, and calculating to obtain the capacitance-voltage disturbance quantity of each submodule;

comparing the capacitance voltage disturbance quantities of any two sub-modules in the same bridge arm, determining the sequence of the capacitance voltage disturbance quantities, and defining P_{ertur_i}The capacitance voltage disturbance quantity of the ith sub-module; p_{ertur_j}The capacitance voltage disturbance quantity of the jth sub-module; i is not less than 1<j is less than or equal to N, and N is the number of the same bridge arm cascade submodules;

when P is present_{ertur_i－}P_{ertur_j}When not less than 0, the same bridgeThe ordering rule of the capacitance and voltage disturbance quantities of the sub-modules in the arm is as follows:

P_{ertur_1}≥P_{ertur_2}≥P_{ertur_3}≥…≥P_{ertur_N}

when P is present_{ertur_i－}P_{ertur_j}When the capacitance and voltage disturbance quantity of the sub-modules in the same bridge arm is less than or equal to 0, the sequencing rule is as follows:

P_{ertur_1}≤P_{ertur_2}≤P_{ertur_3}≤…≤P_{ertur_N}。

optionally, the step of sequencing the capacitor voltages of the sub-modules in the cascaded converter according to the capacitor voltages obtained by parameter sampling calculation of the sub-modules in the cascaded converter includes:

for u is paired_{c1_sam}、u_{c2_sam}、…、u_{cN_sam}Performing ascending or descending arrangement; wherein u is_{c1_sam}For the value of the sampled capacitive voltage of the 1 st submodule, u_{c2_sam}The value of the capacitor voltage sample u for the 2 nd submodule_{cN_sam}And sampling the capacitance voltage of the Nth sub-module, wherein subscripts 1, 2, … and N are serial numbers of the sub-modules.

Optionally, before redistributing the trigger pulses of each sub-module in the cascaded converter according to a preset judgment condition, the method further includes:

calculating the capacitance voltage unbalance degree of the cascaded converter submodule according to the parameter data of the cascaded converter submodule; wherein, the capacitance voltage unbalance degree D of the cascade type converter submodule_{eg_unbal}The calculation formula of (a) is as follows:

D_{eg_unbal}＝MAX{u_{c1_sam}～u_{cN_sam}}_－MIN{u_{c1_sam}～u_{cN_sam}}；

wherein: MAX { } denotes taking the maximum value, MIN { } denotes taking the minimum value.

Optionally, redistributing the trigger pulses of each sub-module in the cascaded converter according to a preset judgment condition, including:

defining the electricity of the ith sub-modulePressure modulation factor d_iSum carrier Tri_iGenerating the ith trigger pulse S_wiAnd the trigger pulses of N cascaded sub-modules in the same bridge arm are respectively recorded as: s_w1、S_w2、…、S_wN；

The trigger pulse of each submodule in the cascade type converter is redistributed by adopting any one or any plurality of the following modes:

the first method is as follows:

at the beginning of the switching cycle of the first submodule,

calculating D_{perturi-perturj}(t)＝P_{ertur_i}(t)-P_{ertur_j}(t) wherein 1. ltoreq. i<j is less than or equal to N, and N is the number of cascaded sub-modules in one bridge arm;

calculating D_{perturi-perturj}(t-T₁)＝P_{ertur_i}(t-T₁)-P_{ertur_j}(t-T₁) Wherein, 1 is less than or equal to i<j is less than or equal to N, and N is the number of cascaded sub-modules in one bridge arm; t is₁For a sampling period, T₁＝T_s/2 or T₁＝T_s；T_sIs a switching cycle; d_{perturi-perturj}(t) is the difference value of the capacitance voltage disturbance quantities of the ith sub-module and the jth sub-module in the current sampling period, P_{ertur_i}(t) is the capacitance voltage disturbance quantity of the ith sub-module in the current sampling period, P_{ertur_j}(t) is the capacitance voltage disturbance quantity of the jth sub-module in the current sampling period, D_{perturi-perturj}(t-T₁) The difference value P of the voltage disturbance quantities of the ith sub-module and the jth sub-module in the last sampling period_{ertur_i}(t-T₁) The disturbance amount of the capacitor voltage of the ith sub-module in the last sampling period, P_{ertur_j}(t-T₁) The capacitance voltage disturbance quantity of the jth sub-module in the last sampling period is obtained;

obtaining SIGN { D_{perturi-perturj}(t) } and SIGN { D }_{perturi-perturj}(t-T₁) }, wherein: SIGN { } denotes a SIGN function; operand x in parentheses>0, then SIGN { x } ═ 1; when x is 0, SIGN { x }, is 0; when x is<0, then SIGN { x } ═ 1;

if SIGN { D_{perturi-perturj}(t)}*SIGN{D_{perturi-perturj}(t-T₁) The value is more than or equal to 0; then the current pulse distribution mode is kept; symbol denotes a multiplication operation;

if SIGN { D_{perturi-perturj}(t)}*SIGN{D_{perturi-perturj}(t-T₁)}<0, and SIGN { D_{perturi-perturj}(t)}>0; s is determined according to the sequence of the sub-module capacitor voltages_w1、S_w2、…、S_wNSequentially distributing the sub-modules with the lowest to the highest capacitor voltage;

if SIGN { D_{perturi-perturj}(t)}*SIGN{D_{perturi-perturj}(t-T₁)}<0, and SIGN { D_{perturi-perturj}(t)}<0; s is determined according to the sequence of the sub-module capacitor voltages_w1、S_w2、…、S_wNSequentially distributing the sub-modules with the highest to the lowest capacitor voltage;

the second method comprises the following steps:

at the beginning of the switching cycle of the first submodule,

calculating D_{perturi-perturj}(t)＝P_{ertur_i}(t)-P_{ertur_j}(t) wherein 1. ltoreq. i<j is less than or equal to N, and N is the number of cascaded sub-modules in one bridge arm;

calculating D_{perturi-perturj}(t-T₁)＝P_{ertur_i}(t-T₁)-P_{ertur_j}(t-T₁) Wherein, 1 is less than or equal to i<j is less than or equal to N, and N is the number of cascaded sub-modules in one bridge arm;

obtaining SIGN { D_{perturi-perturj}(t) } and SIGN { D }_{perturi-perturj}(t-T₁)}；

Obtaining ABS { P_{ertur_1}(t)-P_{ertur_N}(t) }, wherein: ABS { } denotes an absolute value function; when the calculation object x in the parenthesis is larger than or equal to 0, ABS { x } ═ x; when x is<0, ABS { x } ═ x;

setting P_{ertur_ref}，P_{ertur_ref}A threshold for a given capacitance-voltage perturbation amount difference;

if ABS { P_{ertur_1}(t)-P_{ertur_N}(t)}≥P_{ertur_ref}And SIGN { D_{perturi-perturj}(t)}*SIGN{D_{perturi-perturj}(t-T₁)}<0 and SIGN { D_{perturi-perturj}(t)}>0; s is determined according to the sequence of the sub-module capacitor voltages_w1、S_w2、…、S_wNSequentially distributing the sub-modules with the lowest to the highest capacitor voltage;

if ABS { P_{ertur_1}(t)-P_{ertur_N}(t)}≥P_{ertur_ref}And SIGN { D_{perturi-perturj}(t)}*SIGN{D_{perturi-perturj}(t-T₁)}<0 and SIGN { D_{perturi-perturj}(t)}<0; s is determined according to the sequence of the sub-module capacitor voltages_w1、S_w2、…、S_wNSequentially distributing the sub-modules with the highest to the lowest capacitor voltage;

the third method comprises the following steps:

at the beginning of the switching cycle of the first submodule,

calculating D_{perturi-perturj}(t)＝P_{ertur_i}(t)-P_{ertur_j}(t) wherein 1. ltoreq. i<j is less than or equal to N, and N is the number of cascaded sub-modules in one bridge arm;

calculating D_{perturi-perturj}(t-T₁)＝P_{ertur_i}(t-T₁)-P_{ertur_j}(t-T₁) Wherein, 1 is less than or equal to i<j is less than or equal to N, and N is the number of cascaded sub-modules in one bridge arm;

obtaining SIGN { D_{perturi-perturj}(t) } and SIGN { D }_{perturi-perturj}(t-T₁)}；

Set D_{eg_unbal_ref}，D_{eg_unbal_ref}A given capacitance voltage imbalance threshold; d_{eg_unbal}The voltage unbalance of the sub-module capacitor is obtained;

if D is_{eg_unbal}≥D_{eg_unbal_ref}And SIGN { D_{perturi-perturj}(t)}*SIGN{D_{perturi-perturj}(t-T₁)}<0 and SIGN { D_{perturi-perturj}(t)}>0; s is determined according to the sequence of the sub-module capacitor voltages_w1、S_w2、…、S_wNSequentially distributing the sub-modules with the lowest to the highest capacitor voltage;

if D is_{eg_unbal}≥D_{eg_unbal_ref}And SIGN { D_{perturi-perturj}(t)}*SIGN{D_{perturi-perturj}(t-T₁)}<0 and SIGN { D_{perturi-perturj}(t)}<0; s is determined according to the sequence of the sub-module capacitor voltages_w1、S_w2、…、S_wNAnd sequentially distributing the submodules with the highest to lowest capacitor voltage.

Optionally, redistributing the trigger pulses of each sub-module in the cascaded converter according to a preset judgment condition, including: and redistributing the trigger pulses of each sub-module in any one or more modes of exchanging carriers, exchanging voltage modulation coefficients, exchanging carriers and exchanging voltage modulation coefficients.

Optionally, the trigger pulses of each sub-module in the cascaded converter are redistributed, and the trigger pulse redistribution period of the sub-module includes: one switching cycle, a plurality of switching cycles, a number of switching cycles that are not fixed as determined by the degree of imbalance or/and the amount of disturbance.

Optionally, the switching period of each sub-module in the cascaded converter starts at a peak or a peak-valley of the corresponding carrier and ends at a next peak or a peak-valley of the corresponding carrier. Compared with the prior art, the invention has the following beneficial effects:

the method for controlling the balance of the capacitor voltage of the submodule of the cascaded converter can be suitable for various converter operating conditions; the response speed is high, the balance control of the sub-module capacitance voltage can be efficiently and accurately realized, and a better balance effect is achieved; the equalization control algorithm is simple and does not need to use complex external circuits and additional closed-loop controllers.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

fig. 1 is a schematic structural diagram of a modular multilevel cascaded converter (MMC) using half-bridge sub-modules according to an embodiment of the present invention; in FIG. 1 u denotes the submodule output voltage, u_{_ap1}～u_{_apN}Respectively representing the outputs of the submodules of the A-phase upper bridge armVoltage output u_{_an1}～u_{_anN}Respectively representing the output voltage i of each submodule of the A-phase lower bridge arm_{arm_ap}Representing bridge arm current, i, of the A-phase upper bridge arm_{arm_bp}Representing the bridge arm current, i, representing the bridge arm in phase B_{arm_cp}Representing bridge arm current, i, of the C-phase upper bridge arm_{arm_an}Bridge arm current, i, of the A-phase lower bridge arm_{arm_bn}Representing the bridge arm current, i, of the B-phase lower bridge arm_{arm_cn}Bridge arm current, I, of the C-phase lower bridge arm_dcRepresenting the current flowing through the DC bus, V_dcRepresents the dc bus voltage;

FIG. 2 is a schematic diagram of a sub-module capacitor voltage balance control method according to an embodiment of the present invention; t in FIG. 2_ri1～T_riNRespectively represents the carrier wave, u, corresponding to each sub-module_m1～u_mNRespectively representing voltage modulated waves, d, corresponding to the respective submodules₁～d_NRespectively representing the voltage modulation factor, I, of each sub-module_armIndicating bridge arm current, I_{arm_sam1}～I_{arm_samN}Representing bridge-arm current sample values, P, of each submodule respectively_{ertur_1}～P_{ertur_N}Respectively representing the capacitance voltage disturbance quantity u of each submodule_c1～u_cNRespectively representing the capacitor voltage, u, of each submodule_{c1_sam}～u_{cN_sam}Respectively representing the values of the capacitor voltage samples of the individual submodules, D_{eg_unbal}Representing the voltage unbalance of the sub-module capacitor;

FIG. 3 is a schematic diagram of the switch period definition and division of each sub-module in the same bridge arm under the conventional carrier phase shift modulation;

FIG. 4 is a schematic diagram illustrating the switch cycle definition and division of each sub-module in the same bridge arm according to an embodiment of the present invention;

FIG. 5 is a diagram showing simulation results of sorting and calculating the capacitor voltage disturbance quantities of each sub-module in the same bridge arm according to the embodiment of the present invention; p_ertur1～P_{ertur 4}Representing the amount of capacitive voltage disturbance, D, of each submodule_{pertur1-pertur 4}Representing the difference value of the capacitance voltage disturbance quantities of the first submodule and the last submodule;

FIG. 6(a) is a diagram showing a simulation result of capacitor-voltage balance control when no balance control is applied to sub-modules in the same bridge arm according to the embodiment of the present invention;

fig. 6(b) is a diagram illustrating a simulation result of the capacitor voltage balance control when the sub-modules in the same bridge arm are subjected to the balance control according to the embodiment of the present invention.

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.

The embodiment of the invention provides a method for controlling the capacitance-voltage balance of sub-modules in a bridge arm of a cascaded converter by adopting carrier phase shift modulation. The method for controlling the capacitance and voltage balance of the sub-modules in the Bridge arm of the Cascaded H-Bridge Converter using carrier phase shift modulation in the embodiment can be applied to the sub-module capacitance and voltage balance control of a half-Bridge, a full-Bridge Modular Multilevel Converter (MMC) and a Cascaded H-Bridge Converter (CHB).

Fig. 1 is a schematic structural diagram of a Modular Multilevel Converter (MMC) using half-bridge sub-modules according to an embodiment of the present invention, as shown in fig. 1. In the modular multilevel converter of fig. 1, six legs are included, each leg having 4 sub-modules (SMn)₁～SMn_N) The rated power of the bridge arm is 10MW, and each bridge arm is formed by cascading 4 sub-modules. The reference value of the capacitor voltage of each submodule is 2000V, the carrier frequency is 1000Hz, the total direct current bus voltage is 8000V, the peak value of the line voltage of the alternating current network side is 2400V, and the fundamental frequency is 50 Hz. Fig. 2 is a schematic diagram of a sub-module capacitor voltage balance control method according to an embodiment of the present invention. As shown in fig. 2, the method specifically includes the following steps:

and (3) link 1: determining a division mode of a submodule switch period;

for traditional carrier phase shift modulation, the phase shift angle of each sub-module carrier in one bridge arm of the converter is sequentially different by 2 pi/N (rad/s) (N is the number of the sub-modules cascaded in the bridge arm under the condition of not considering redundancy), one sub-module in the bridge arm is arbitrarily selected as a module 1, the corresponding carrier is taken as a reference carrier and is marked as Tri₁Defining the phase shift angle to be 0; the carriers corresponding to N-1 modules with the phases lagging by 2 pi/N in sequence are respectively marked as Tri₂、Tri₃、…、Tri_N. The division of the synchronous switching period in the conventional carrier phase shift modulation is shown in fig. 3, and the same bridge arm of the cascaded converter in fig. 3 comprises 4 sub-modules, S_W1～S_W4Representing the switching pulses, T, corresponding to 4 submodules_SWIndicating a switching cycle, the switching cycles of all sub-modules in the same leg start and end simultaneously, as shown in fig. 3. The non-synchronous switching period division in the method of the present invention is shown in fig. 4, and the switching period of each module starts at the peak of the corresponding carrier and ends at the next peak of the carrier. Therefore, the switching period of each module is not started and ended simultaneously, the starting time and the ending time of the switching period of two adjacent modules are different by 1/N switching periods.

When the carrier wave corresponding to each sub-module reaches the peak value or the trough, the capacitance voltage of each sub-module is obtained through sampling, and the sub-module capacitance voltage disturbance quantity is obtained through sampling calculation.

Calculating the voltage disturbance quantity of the sub-module capacitor in an asynchronous switching period for 2 times:

1, time: after sampling at the carrier peak value of the Nth module is completed, calculating the capacitance voltage disturbance quantity of each sub-module, wherein the calculation method of the capacitance voltage disturbance quantity of the ith sub-module comprises the following steps:

P_{ertur_ip}＝d_ip*I_{arm_samip}

and 2, time: after sampling at the carrier wave trough of the Nth module is completed, calculating the capacitance voltage disturbance quantity of each submodule, wherein the capacitance voltage disturbance quantity of the ith submodule is as follows:

P_{ertur_iv}＝d_iv*I_{arm_samiv}

and (2) link: sequencing the sub-module capacitance voltage disturbance quantity;

sequencing the capacitance and voltage disturbance quantities of the sub-modules in the same bridge arm, selecting the first sub-module and the last sub-module to calculate the disturbance quantities and calculate the difference,

when D is present_{pertur1-perturN}＝P_{ertur_1p－}P_{ertur_Np}When the capacitance voltage disturbance quantity sequencing rule in the same bridge arm is larger than or equal to 0, the sequence rule is as follows:

P_{ertur_1p}≥P_{ertur_2p}≥P_{ertur_3p}≥…≥P_{ertur_Np}

when D is present_{pertur1-perturN}＝P_{ertur_1p－}P_{ertur_Np}When the capacitance voltage disturbance quantity is less than or equal to 0, the ordering rule of the capacitance voltage disturbance quantity in the same bridge arm can be obtained from small to large:

P_{ertur_1p}≤P_{ertur_2p}≤P_{ertur_3p}≤…≤P_{ertur_Np}

can be derived from P_{ertur_1p}And P_{ertur_Np}The positive and negative difference values can directly obtain the sequencing result of the capacitance-voltage disturbance quantity of each submodule in the same bridge arm, and a sequencing algorithm is not needed, so that the static sequencing is realized.

The sorting method of the submodule capacitor voltage disturbance quantity obtained by calculating the sampling value at the carrier wave trough is the same as the above, and is not described herein again.

The simulation results of the sub-module capacitance-voltage disturbance amount calculation and sorting are shown in fig. 5.

And (3) link: and (4) sequencing the capacitor voltage of the sub-modules and calculating the degree of unbalance.

The sequencing and the unbalance degree of the capacitor voltages in the bridge arms are calculated and updated for 2 times in one asynchronous switching period:

1, time: after the sampling at the carrier peak of the Nth module is finished, u is measured_{c1_samp}、u_{c2_samp}、…、u_{cN_samp}Sequencing is carried out, and the imbalance degree of the sub-module capacitor voltage is calculated as follows:

D_{eg_unbal}＝MAX{u_{c1_samp}～u_{cN_samp}}_－MIN{u_{c1_samp}～u_{cN_samp}}

and 2, time: when the sampling at the wave trough of the carrier wave of the Nth module is finished, u is measured_{c1_samv}、u_{c2_samv}、…、u_{cN_samv}Sequencing is carried out, and the imbalance degree of the sub-module capacitor voltage is calculated as follows:

D_{eg_unbal}＝MAX{u_{c1_samv}～u_{cN_samv}}_－MIN{u_{c1_samv}～u_{cN_samv}}

wherein D is_{eg_unbal}Obtaining the unbalance degree of the capacitance and the voltage of the sub-modules in the same bridge arm by simulation calculation

And 4, link 4: the sub-module triggers the redistribution of the pulses.

When the switching period of the first submodule starts, the disturbance quantity of the first submodule and the disturbance quantity of the last submodule are subjected to difference calculation, and the obtained difference value D is compared_{pertur1-perturN}(t) difference D from last calculation_{pertur1-perturN}(t-T_sWhether the positive and negative of/2) are the same.

If D is_{pertur1-perturN}(t)*D_{pertur1-perturN}(t-T_s/2) is not less than 0; the current burst allocation scheme is maintained.

If D is_{pertur1-perturN}(t)*D_{pertur1-perturN}(t-T_s/2)<0 and D_{pertur1-perturN}(t)>0；

The sub-module capacitance voltages are sorted and S is_w1、S_w2、…、S_wNSequentially distributing the sub-modules with the lowest to the highest capacitor voltage;

if D is_{pertur1-perturN}(t)*D_{pertur1-perturN}(t-T_s/2)<0 and D_{pertur1-perturN}(t)<0；

The sub-module capacitance voltages are sorted and S is_w1、S_w2、…、S_wNSequentially distributing the sub-modules with the highest to the lowest capacitor voltage;

the simulation results of the sub-module capacitor voltage balance control are shown in fig. 6. It can be seen that after the balance control is added, the sub-module capacitor voltage is well controlled, and the imbalance degree of the sub-module capacitor voltage is reduced. Meanwhile, the divergence degree of the capacitor voltage can be well represented by the imbalance degree of the capacitor voltage.

The invention is suitable for various cascade type converters and corresponding working conditions thereof, can quickly realize the balance control of the sub-module capacitance voltage, and has better balance effect; the equalization control algorithm is simple and does not need to be assisted by a complex external circuit.

The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.

Claims (8)

1. A method for controlling the capacitance-voltage balance of submodule of a cascade converter is characterized by comprising the following steps:

determining an asynchronous switch period dividing mode of each submodule in the cascaded converter;

according to the asynchronous switching period dividing mode of each sub-module in the cascade type converter, carrying out corresponding parameter sampling calculation to obtain the capacitance voltage disturbance quantity of each sub-module, and sequencing the capacitance voltage disturbance quantity of each sub-module in the cascade type converter;

according to the obtained capacitance voltage obtained by parameter sampling calculation of each sub-module in the cascaded converter, sequencing the capacitance voltage of each sub-module in the cascaded converter;

redistributing the trigger pulse of each submodule in the cascaded converter according to a preset judgment condition; wherein the preset judgment condition comprises: any one or any combination of the sorting result of the capacitance-voltage disturbance quantities of the sub-modules, the sorting result of the capacitance-voltage of the sub-modules, the capacitance-voltage unbalance of the sub-modules and the difference value of the capacitance-voltage disturbance quantities of the sub-modules;

redistributing the trigger pulses of each submodule in the cascaded converter according to a preset judgment condition, wherein the redistributing comprises the following steps:

defining the voltage modulation coefficient d of the ith sub-module_iSum carrier Tri_iGenerating the ith trigger pulse S_wiAnd the trigger pulses of N cascaded sub-modules in the same bridge arm are respectively recorded as: s_w1、S_w2、…、S_wN；

The trigger pulse of each submodule in the cascade type converter is redistributed by adopting any one or any plurality of the following modes:

the first method is as follows:

at the beginning of the switching cycle of the first submodule,

calculating D_{perturi-perturj}(t)＝P_{ertur_i}(t)-P_{ertur_j}(t) wherein 1. ltoreq. i<j is less than or equal to N, and N is the number of cascaded sub-modules in one bridge arm;

calculating D_{perturi-perturj}(t-T₁)＝P_{ertur_i}(t-T₁)-P_{ertur_j}(t-T₁) Wherein, 1 is less than or equal to i<j is less than or equal to N, and N is the number of cascaded sub-modules in one bridge arm; t is₁For a sampling period, T₁＝T_s/2 or T₁＝T_s；T_sIs a switching cycle; d_{perturi-perturj}(t) is the difference value of the capacitance voltage disturbance quantities of the ith sub-module and the jth sub-module in the current sampling period, P_{ertur_i}(t) is the capacitance voltage disturbance quantity of the ith sub-module in the current sampling period, P_{ertur_j}(t) is the capacitance voltage disturbance quantity of the jth sub-module in the current sampling period, D_{perturi-perturj}(t-T₁) The difference value P of the voltage disturbance quantities of the ith sub-module and the jth sub-module in the last sampling period_{ertur_i}(t-T₁) The disturbance amount of the capacitor voltage of the ith sub-module in the last sampling period, P_{ertur_j}(t-T₁) The capacitance voltage disturbance quantity of the jth sub-module in the last sampling period is obtained;

obtaining SIGN { D_{perturi-perturj}(t) } and SIGN { D }_{perturi-perturj}(t-T₁) }, wherein: SIGN { } denotesA sign function; operand x in parentheses>0, then SIGN { x } ═ 1; when x is 0, SIGN { x }, is 0; when x is<0, then SIGN { x } ═ 1;

if SIGN { D_{perturi-perturj}(t)}*SIGN{D_{perturi-perturj}(t-T₁) The value is more than or equal to 0; then the current pulse distribution mode is kept; symbol denotes a multiplication operation;

if SIGN { D_{perturi-perturj}(t)}*SIGN{D_{perturi-perturj}(t-T₁)}<0, and SIGN { D_{perturi-perturj}(t)}>0; s is determined according to the sequence of the sub-module capacitor voltages_w1、S_w2、…、S_wNSequentially distributing the sub-modules with the lowest to the highest capacitor voltage;

if SIGN { D_{perturi-perturj}(t)}*SIGN{D_{perturi-perturj}(t-T₁)}<0, and SIGN { D_{perturi-perturj}(t)}<0; s is determined according to the sequence of the sub-module capacitor voltages_w1、S_w2、…、S_wNSequentially distributing the sub-modules with the highest to the lowest capacitor voltage;

the second method comprises the following steps:

at the beginning of the switching cycle of the first submodule,

calculating D_{perturi-perturj}(t)＝P_{ertur_i}(t)-P_{ertur_j}(t) wherein 1. ltoreq. i<j is less than or equal to N, and N is the number of cascaded sub-modules in one bridge arm;

calculating D_{perturi-perturj}(t-T₁)＝P_{ertur_i}(t-T₁)-P_{ertur_j}(t-T₁) Wherein, 1 is less than or equal to i<j is less than or equal to N, and N is the number of cascaded sub-modules in one bridge arm;

obtaining SIGN { D_{perturi-perturj}(t) } and SIGN { D }_{perturi-perturj}(t-T₁)}；

Obtaining ABS { P_{ertur_1}(t)-P_{ertur_N}(t) }, wherein: ABS { } denotes an absolute value function; when the calculation object x in the parenthesis is larger than or equal to 0, ABS { x } ═ x; when x is<0, ABS { x } ═ x;

setting P_{ertur_ref}，P_{ertur_ref}A threshold for a given capacitance-voltage perturbation amount difference;

if ABS { P_{ertur_1}(t)-P_{ertur_N}(t)}≥P_{ertur_ref}And SIGN { D_{perturi-perturj}(t)}*SIGN{D_{perturi-perturj}(t-T₁)}<0 and SIGN { D_{perturi-perturj}(t)}>0; s is determined according to the sequence of the sub-module capacitor voltages_w1、S_w2、…、S_wNSequentially distributing the sub-modules with the lowest to the highest capacitor voltage;

if ABS { P_{ertur_1}(t)-P_{ertur_N}(t)}≥P_{ertur_ref}And SIGN { D_{perturi-perturj}(t)}*SIGN{D_{perturi-perturj}(t-T₁)}<0 and SIGN { D_{perturi-perturj}(t)}<0; s is determined according to the sequence of the sub-module capacitor voltages_w1、S_w2、…、S_wNSequentially distributing the sub-modules with the highest to the lowest capacitor voltage;

the third method comprises the following steps:

at the beginning of the switching cycle of the first submodule,

calculating D_{perturi-perturj}(t)＝P_{ertur_i}(t)-P_{ertur_j}(t) wherein 1. ltoreq. i<j is less than or equal to N, and N is the number of cascaded sub-modules in one bridge arm;

calculating D_{perturi-perturj}(t-T₁)＝P_{ertur_i}(t-T₁)-P_{ertur_j}(t-T₁) Wherein, 1 is less than or equal to i<j is less than or equal to N, and N is the number of cascaded sub-modules in one bridge arm;

obtaining SIGN { D_{perturi-perturj}(t) } and SIGN { D }_{perturi-perturj}(t-T₁)}；

Set D_{eg_unbal_ref}，D_{eg_unbal_ref}A given capacitance voltage imbalance threshold; d_{eg_unbal}The voltage unbalance of the sub-module capacitor is obtained;

if D is_{eg_unbal}≥D_{eg_unbal_ref}And SIGN { D_{perturi-perturj}(t)}*SIGN{D_{perturi-perturj}(t-T₁)}<0 and SIGN { D_{perturi-perturj}(t)}>0; s is determined according to the sequence of the sub-module capacitor voltages_w1、S_w2、…、S_wNSequentially assigned to the lowest to highest capacitor voltageA sub-module;

if D is_{eg_unbal}≥D_{eg_unbal_ref}And SIGN { D_{perturi-perturj}(t)}*SIGN{D_{perturi-perturj}(t-T₁)}<0 and SIGN { D_{perturi-perturj}(t)}<0; s is determined according to the sequence of the sub-module capacitor voltages_w1、S_w2、…、S_wNAnd sequentially distributing the submodules with the highest to lowest capacitor voltage.

2. The method for controlling the capacitance-voltage balance among the sub-modules of the cascaded converter according to claim 1, wherein the step of determining the asynchronous switching cycle division mode of each sub-module of the cascaded converter comprises the steps of:

supposing that one bridge arm of a cascade converter adopting carrier phase shift modulation comprises N cascade submodules, the phase angle difference of adjacent cascade submodules is 2 pi/N, one submodule is arbitrarily selected from the N cascade submodules to be used as a first module, the carrier of the first module is used as a reference carrier and is marked as Tri₁Defining the phase shift angle of the first module as 0; the carriers corresponding to N-1 modules with the phases lagging by 2 pi/N in sequence are respectively marked as Tri₂、Tri₃、…、Tri_N(ii) a The voltage modulation wave corresponding to each submodule is respectively marked as u_m1、u_m2、…、u_mNThe voltage modulation coefficient corresponding to each submodule is recorded as d₁、d₂、…、d_N(ii) a The bridge arm current or the input current of the submodule is marked as I_arm(ii) a The capacitor voltage of each submodule is respectively marked as u_c1、u_c2、…、u_cN(ii) a And defining the switching period of the corresponding sub-module as the time between two adjacent peak values of the respective carrier of each sub-module.

3. The method according to claim 1, wherein the step of performing corresponding parametric sampling calculation according to the asynchronous switching cycle division manner of each submodule in the cascaded converter to obtain the capacitance-voltage disturbance amount of each submodule, and the step of sorting the capacitance-voltage disturbance amounts of each submodule in the cascaded converter comprises:

when the carrier corresponding to each submodule reaches a peak value or a trough, sampling to obtain parameter data of each submodule, and calculating to obtain the capacitance-voltage disturbance quantity of each submodule;

comparing the capacitance voltage disturbance quantities of any two sub-modules in the same bridge arm, determining the sequence of the capacitance voltage disturbance quantities, and defining P_{ertur_i}The capacitance voltage disturbance quantity of the ith sub-module; p_{ertur_j}The capacitance voltage disturbance quantity of the jth sub-module; i is not less than 1<j is less than or equal to N, and N is the number of the same bridge arm cascade submodules;

when P is present_{ertur_i}－P_{ertur_j}When the capacitance voltage disturbance quantity of the sub-modules in the same bridge arm is more than or equal to 0, the sequencing rule of the capacitance voltage disturbance quantities of the sub-modules in the same bridge arm is as follows:

P_{ertur_1}≥P_{ertur_2}≥P_{ertur_3}≥…≥P_{ertur_N}

when P is present_{ertur_i}－P_{ertur_j}When the capacitance and voltage disturbance quantity of the sub-modules in the same bridge arm is less than or equal to 0, the sequencing rule is as follows:

P_{ertur_1}≤P_{ertur_2}≤P_{ertur_3}≤…≤P_{ertur_N}。

4. the method according to claim 1, wherein the step of sequencing the capacitor voltages of the submodules in the cascaded converter according to the capacitor voltages obtained by parametric sampling and calculating the submodules in the cascaded converter comprises:

for u is paired_{c1_sam}、u_{c2_sam}、…、u_{cN_sam}Performing ascending or descending arrangement; wherein u is_{c1_sam}For the value of the sampled capacitive voltage of the 1 st submodule, u_{c2_sam}The value of the capacitor voltage sample u for the 2 nd submodule_{cN_sam}And sampling the capacitance voltage of the Nth sub-module, wherein subscripts 1, 2, … and N are serial numbers of the sub-modules.

5. The method according to claim 4, before redistributing the trigger pulses of the sub-modules of the cascaded converter according to a preset judgment condition, further comprising:

calculating the capacitance voltage unbalance degree of the cascaded converter submodule according to the parameter data of the cascaded converter submodule; wherein, the capacitance voltage unbalance degree D of the cascade type converter submodule_{eg_unbal}The calculation formula of (a) is as follows:

D_{eg_unbal}＝MAX{u_{c1_sam}～u_{cN_sam}}－MIN{u_{c1_sam}～u_{cN_sam}}；

wherein: MAX { } denotes taking the maximum value, MIN { } denotes taking the minimum value.

6. The method according to claim 1, wherein redistributing the trigger pulses of each submodule in the cascaded converter according to a preset judgment condition includes: and redistributing the trigger pulses of each sub-module in any one or more modes of exchanging carriers, exchanging voltage modulation coefficients, exchanging carriers and exchanging voltage modulation coefficients.

7. The cascaded converter submodule capacitor voltage balance control method of claim 1, wherein the trigger pulse of each submodule in the cascaded converter is redistributed, and the trigger pulse redistribution period of the submodule comprises: one switching cycle, a plurality of switching cycles, a number of switching cycles that are not fixed as determined by the degree of imbalance or/and the amount of disturbance.

8. The cascaded converter sub-module capacitance-voltage balance control method according to any one of claims 1 and 3-7, wherein the switching period of each sub-module in the cascaded converter starts at the peak value or peak-valley of the corresponding carrier wave and ends at the next peak value or peak-valley of the corresponding carrier wave.

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