CN109346524B - Super-junction VDMOS device with stepped-concentration polysilicon side wall structure - Google Patents
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 77
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 70
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 29
- 238000002955 isolation Methods 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 235000012239 silicon dioxide Nutrition 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 6
- 230000015556 catabolic process Effects 0.000 abstract description 16
- 230000005684 electric field Effects 0.000 abstract description 11
- 230000000779 depleting effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 9
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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Abstract
The invention discloses a super-junction VDMOS device with a step-concentration polysilicon side wall structure. And secondly, a P-type column is introduced on the basis of the novel super-junction VDMOS device, and when the device is in an off state, a series of reverse PN junction structures are formed with an N-type drift region in the drift region to bear part of withstand voltage, so that an electric field of the device is introduced into the device, the electric field distribution in the whole active top layer silicon is optimized, and the breakdown voltage of the device is improved. On the other hand, the super junction structure formed in the drift region assists in depleting the drift region, so that the doping concentration of the drift region is improved, and the purpose of reducing the on-resistance of the device in an on state is achieved. In conclusion, the structure of the invention can improve the breakdown voltage of the device, reduce the on-resistance of the device and relieve the contradiction between the breakdown voltage and the on-resistance of the power device.
Description
Technical Field
The invention belongs to the technical field of semiconductor power devices, and particularly relates to a super-junction VDMOS device with a stepped-concentration polysilicon side wall structure.
Background
A power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device is widely used in the Field of power integration, and a contradiction between a breakdown voltage and an on-resistance is one of the focus problems of long-term attention, and thus a series of solutions for alleviating the contradiction are proposed, in which a Super junction structure (Super junction) is considered to be one of the structures capable of effectively alleviating the contradiction. A typical conventional super-junction VDMOS device is shown in fig. 1, where 1 is an N-type substrate, 2 is a P-column region, 3 is an N-type drift region, active top silicon includes 7 is a P + source region, 8 is an N + source region, 9 is a P-base region, 10 is a gate oxide region, and electrodes include a source electrode 11, a gate electrode 12, and a drain electrode 13. Compared with a non-super-junction structure, the structure utilizes a charge compensation theory to replace a single-doped (P-type or N-type) drift region with a series of alternately arranged P column regions and N-type drift regions. When the device is in an off state, a longitudinal electric field and a transverse electric field formed by the P column region and the N-type drift region exist in the super junction structure device. If the P column region and the N type drift region are completely exhausted before breakdown, the critical electric field of the super junction structure can be fixed at a constant value. Therefore, the withstand voltage of the device depends only on the thickness of the drift region, so that the doping concentration of the drift region can be greatly increased, and the on-resistance of the device can be greatly reduced under the condition of keeping the same breakdown voltage. Relevant contents are found in references: semiconductor power devices with alternating conductivity type high-voltage breakdown regions, US5216275[ P ]. 1993. On the basis, a Poly-thinned VDMOS device is proposed, as shown in fig. 2, 1 is an N-type substrate, 3 is an N-type drift region, 4 is an oxidation isolation layer, active top silicon includes 7 is a P + source region, 8 is an N + source region, 9 is a P-base region, 10 is a gate oxide region, 14 is a polysilicon side wall, and the electrodes include a source electrode 11, a gate electrode 12 and a drain electrode 13. The structure adopts a thin oxide layer structure grown on the interface between the P area and the N area, thereby playing an isolation role, overcoming the problem of mutual diffusion of different impurity dopings and increasing the stability of the device. Meanwhile, the widths of the N-type epitaxial layer and the P-type polycrystalline silicon can be reduced, so that the doping concentration of the epitaxial layer of the device is improved, and the on-resistance of the device is reduced. However, this structure still has a problem of charge imbalance. Relevant contents are found in references: GanK P, Liang Y C, Samudra G S, et al.Poly swept VDMOS (PFVDMOS): a Experimental technology for Experimental devices [ J ] 2001,4: 2156-. In order to further relieve the contradiction between the on-resistance and the breakdown voltage and solve the problem of charge balance. Yuan c, liang et al propose an edge-Oxide-diffused OBVDMOS (Oxide-diffused OBVDMOS), as shown in fig. 3, 1 is an N + type substrate, 3 is an N type drift region, 10 is a gate Oxide region, active top silicon includes 7P + source region, 8N + source region, 9P-base region, 14 polysilicon sidewall, 15 is a metal Oxide layer (MTO), and the electrode includes a source electrode 11, a gate electrode 12, and a drain electrode 13. The structure is characterized in that: the thick oxide layer wall replaces a P column region in the traditional super-junction VDMOS, and the oxide layer can bear withstand voltage in the off state of the device; meanwhile, the transverse depletion of the N-type drift region is accelerated by the electric field effect caused by the added metal oxide layer, and the doping concentration of the drift region needs to be increased in order to prevent the device from being broken down in advance, so that the on-resistance of the device is greatly reduced. The related contents are as follows: liang Y C, Gan K P, Samdra GS. oxide-bypass VDMOS (OBVDMOS) an alternative to superior junction high voltage MOS power devices [ J ]. Electron Device Letters IEEE,2001,22(8): 407-.
In summary, research on a super junction VDMOS device having a low on-resistance remains a worldwide research focus.
Disclosure of Invention
In view of the above, the present invention provides a super junction VDMOS device having a step-concentration polysilicon sidewall structure.
In order to achieve the above purpose, the invention provides the following technical scheme:
1. a super-junction VDMOS device with a stepped concentration polysilicon side wall structure comprises an N + type substrate 1, a P column region 2, an N type drift region 3, a silicon dioxide isolation wall 4, a stepped concentration polysilicon side wall column, active top layer silicon, a source electrode 11, a gate electrode 12 and a drain electrode 13, wherein the active top layer silicon comprises a P + source region 7, an N + source region 8, a P-base region 9 and a gate oxide region 10; the N + type substrate is sequentially provided with a P column region 2, an N type drift region 3, a silicon dioxide isolation column 4 and stepped concentration polysilicon side wall columns 5 and 6; the leakage electrode 13 is located below the N + type substrate 1, the step concentration polycrystalline silicon side wall column is vertically partitioned according to different concentrations, and the step number of the step concentration polycrystalline silicon side wall structure is larger than or equal to 2 according to needs.
Preferably, the P column region 2 and the N type drift region 3 are in parallel contact with the P-base region 9.
Preferably, the P + source region 7 is located in the P-base region 9 after being juxtaposed with the N + source region 8, and the P + source region 7 is in contact with the source electrode 11 after being juxtaposed with the N + source region 8.
Preferably, the gate oxide region 10 is located above the P-base region 9, and the gate electrode 12 is located in the gate oxide region 9.
Preferably, the step-concentration polysilicon sidewall pillar is juxtaposed with the silicon dioxide isolation wall 4 and then contacts the source electrode 11.
Preferably, the N-type drift region 3, the P-base region 9 and the silicon dioxide isolation wall 4 are juxtaposed and then contact the gate oxide region 10.
Preferably, the gate oxide region 10 is located below the source electrode 11.
Preferably, the material of the step-concentration polysilicon side wall column is P-type doped polysilicon.
Preferably, the step-concentration polysilicon side wall column is divided into a step-concentration polysilicon side wall column II 6 and a step-concentration polysilicon side wall column I5 according to different doping concentrations, and the step-concentration polysilicon side wall column I5 is located under the step-concentration polysilicon side wall column II 6.
Preferably, the material of the active top layer silicon is one or more of Si, SiC and GaN semiconductor materials.
The invention has the beneficial effects that:
1. the super-junction VDMOS device is provided with a thin silicon oxide wall and a polysilicon side wall structure with step concentration on the basis of the conventional super-junction VDMOS device. The silicon oxide thin wall plays a role in isolation and voltage resistance increasing, and the polycrystalline silicon side wall structure with the step concentration can effectively solve the problem of charge imbalance.
2. Compared with some novel super-junction VDMOS device structures, on the basis of the polysilicon and silicon oxide structures, the structure provided by the invention introduces a P-type column into a drift region to form a super-junction structure in the drift region. When the device is in an off state, the N-type drift region and the P-type column in the drift region form a series of reverse PN junction structures, and the reverse PN junctions bear part of withstand voltage, so that an electric field of the device is introduced into the device, the electric field distribution in the whole active top layer silicon is optimized, and the breakdown voltage of the device is improved. On the other hand, the super junction structure formed in the drift region assists in depleting the drift region, so that the doping concentration of the drift region is improved, and the purpose of reducing the on-resistance of the device in an on state is achieved.
Drawings
In order to make the purpose, technical scheme and beneficial effect of the invention more clear, the invention provides the following drawings:
fig. 1 is a diagram of a typical conventional super junction VDMOS device;
FIG. 2 is a diagram of a Poly Flanked VDMOS device;
FIG. 3 is a diagram of a VDMOS device with an edge oxygen channel structure;
FIG. 4 is a diagram of a super junction VDMOS device with a step concentration polysilicon sidewall structure according to the present invention;
fig. 5 is a graph comparing the electric field distribution of the cross section of the super junction VDMOS device with the step concentration polysilicon sidewall structure and the cross section of the Poly Flanked VDMOS device at the middle position (y is 15 μm) inside the device in the off state;
fig. 6 is a graph comparing the I-V curves of a super junction VDMOS device having a step concentration polysilicon sidewall structure with a typical conventional super junction VDMOS device in an on state;
FIG. 7 is an equipotential line distribution diagram of a super-junction VDMOS device with a stepped-concentration polysilicon side wall in an off-state breakdown state;
FIG. 8 is a current density line distribution diagram of a super junction VDMOS device with a step concentration polysilicon side wall in an on state;
the silicon-based epitaxial wafer is characterized in that 1 is an N + type substrate, 2 is a P column region, 3 is an N type drift region, 4 is a silicon dioxide isolation wall, 5 is a first step concentration polysilicon side wall column, 6 is a second step concentration polysilicon side wall column, 7 is a P + source region, 8 is an N + source region, 9 is a P-base region, 10 is a gate oxide region, 11 is a source electrode, 12 is a gate electrode, 13 is a drain electrode, 14 is a polysilicon side wall, and 15 is a metal oxide layer (MTO).
Detailed Description
The preferred embodiments of the present invention will be described in detail below. The experimental procedures, in which specific conditions are not specified in the examples, are generally carried out under conventional conditions or under conditions recommended by the manufacturers.
Example 1
The invention provides a super-junction VDMOS device structure diagram with a step concentration polysilicon side wall structure, which comprises an N + type substrate 1, a P column region 2, an N type drift region 3, a silicon dioxide isolation wall 4, a step concentration polysilicon side wall column, active top layer silicon, a source electrode 11, a gate electrode 12 and a drain electrode 13, wherein the active top layer silicon comprises a P + source region 7, an N + source region 8, a P-base region 9 and a gate oxide region 10; the N + type substrate is sequentially provided with a P column region 2, an N type drift region 3, a silicon dioxide isolation column 4 and a stepped concentration polysilicon side wall column 5; the drain electrode is positioned under the N + type substrate 13; the material of the step concentration polysilicon side wall column is P-type doped, and is vertically partitioned according to different concentrations, as shown in fig. 4, the step concentration polysilicon side wall column is divided into a step concentration polysilicon side wall column II 6 and a step concentration polysilicon side wall column I5, and the step concentration polysilicon side wall column I5 is positioned under the step concentration polysilicon side wall column II 6; the P column region 2 and the N type drift region 3 are in parallel contact with a P-base region 9; the P + source region 7 is positioned in the P-base region 9 after being parallel to the N + source region 8, and the upper part of the P + source region 7 is contacted with the source electrode 11 after being parallel to the N + source region 8; the gate oxide region 10 is positioned above the P-base region 9, and the gate electrode 12 is positioned in the gate oxide region 9; the step concentration polysilicon side wall column is in parallel with the silicon dioxide isolation wall 4 and then is in contact with the source electrode 11; the N-type drift region 3, the P-base region 9 and the silicon dioxide isolation wall 4 are in parallel and then are in contact with the gate oxide region 10; the gate oxide region 10 is located below the source electrode 11; the material of the active top layer silicon is one or more of Si, SiC and GaN semiconductor materials.
The working principle of the super-junction VDMOS device with the stepped concentration polysilicon side wall structure provided by the invention is described in detail by taking the super-junction VDMOS device structure with the stepped concentration polysilicon side wall structure provided by the figure 4 as an example: when the device is in an off-state voltage withstanding state, the N-type column and the P-type column in the drift region form a series of reverse PN junction structures, and the reverse PN junctions bear part of voltage withstanding, so that an electric field of the device is introduced into the device, the surface electric field distribution of the whole device is optimized, and the breakdown voltage of the device is improved; secondly, when the device is in an on state, the P column region and the P-type polycrystalline silicon side wall in the drift region play a role in auxiliary depletion on the N-type drift region, so that the corresponding optimal drift region is higher in doping concentration; the polysilicon side wall structure equivalently increases the width of the P column region, destroys the charge balance condition in the super junction structure (namely the P type region and the N type drift region have the same width and the same doping concentration), and the polysilicon side wall structure with the step concentration enables the charges in the P type region and the N type region to be balanced by accurately adjusting the concentration difference of the doped polysilicon, thereby further improving the doping concentration of the drift region and greatly reducing the on-resistance of the device.
Fig. 5 is a comparison graph of the electric field distribution of the cross section of the middle position (y is 15 μm) inside the super-junction VDMOS device with the stepped-concentration polysilicon side wall structure in the off-state condition between the super-junction VDMOS device with the stepped-concentration polysilicon side wall structure provided by the present invention and the Poly thinned VDMOS device shown in fig. 2.
Fig. 6 is a comparison graph of I-V curves of the VDMOS device with the super-junction VDMOS having the stepped-concentration polysilicon side wall structure according to the present invention and the VDMOS device with the conventional structure in an on state. Compared with a typical conventional super junction VDMOS device, the breakdown voltage is increased by 35%, and meanwhile, the on-resistance is reduced by 92%; compared with a Poly Flanked VDMOS device, the on-resistance is reduced by 54% under the condition of ensuring the same breakdown voltage.
By combining the equipotential line distribution diagram of the super-junction VDMOS device with the stepped-concentration polysilicon side wall shown in fig. 7 in the off-state breakdown state and the current density line distribution diagram of the super-junction VDMOS device with the stepped-concentration polysilicon side wall shown in fig. 8 in the on-state, it can be seen that the super-junction VDMOS device of the present invention can improve the breakdown voltage of the device, reduce the on-resistance of the device, and alleviate the contradiction between the breakdown voltage and the on-resistance of the power device.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and it is apparent that those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such modifications and variations of the present invention fall within the scope of the present invention and its equivalent technology, it is intended that the present invention also include such modifications and variations.
Claims (10)
1. A super-junction VDMOS device with a stepped concentration polysilicon side wall structure is characterized by comprising an N + type substrate (1), a P column region (2), an N type drift region (3), a silicon dioxide isolation wall (4), a stepped concentration polysilicon side wall column, active top layer silicon, a source electrode (11), a gate electrode (12) and a drain electrode (13), wherein the active top layer silicon comprises a P + source region (7), an N + source region (8), a P-base region (9) and a gate oxide region (10); a P column region (2), an N type drift region (3), a silicon dioxide isolation column (4), a first stepped concentration polysilicon side wall column (5) and a second stepped concentration polysilicon side wall column (6) are sequentially arranged on the N + type substrate; the drain electrode (13) is located below the N + type substrate (1), the step concentration polycrystalline silicon side wall column is vertically partitioned according to different concentrations, and the step number of the step concentration polycrystalline silicon side wall structure is larger than or equal to 2 according to requirements.
2. The super-junction VDMOS device with the stepped-concentration polysilicon sidewall structure as claimed in claim 1, wherein the P column region (2) and the N-type drift region (3) are juxtaposed and in contact with the P-base region (9).
3. The super-junction VDMOS device with the graded-concentration polysilicon sidewall structure as claimed in claim 1, wherein the P + source region (7) is located in the P-base region (9) after being juxtaposed with the N + source region (8), and the P + source region (7) is in contact with the source electrode (11) after being juxtaposed with the N + source region (8).
4. The super-junction VDMOS device with the stepped-concentration polysilicon sidewall structure as claimed in claim 1, wherein the gate oxide region (10) is located above the P-base region (9), and the gate electrode (12) is located in the gate oxide region (9).
5. The super-junction VDMOS device with the step-concentration polysilicon sidewall structure as claimed in claim 1, wherein the step-concentration polysilicon sidewall pillar is juxtaposed with the silicon dioxide isolation wall (4) and then contacts the source electrode (11).
6. The super-junction VDMOS device with the stepped concentration polysilicon side wall structure as claimed in claim 1, wherein the N-type drift region (3), the P-base region (9) and the silicon dioxide isolation wall (4) are juxtaposed and then contact with the gate oxide region (10).
7. The super-junction VDMOS device with the stepped-concentration polysilicon sidewall structure as claimed in claim 1, wherein the gate oxide region (10) is located below the source electrode (11).
8. The super-junction VDMOS device having the step-concentration polysilicon sidewall structure as claimed in claim 1, wherein the material of the first step-concentration polysilicon sidewall pillar (5) and the second step-concentration polysilicon sidewall pillar (6) is P-type doped polysilicon.
9. The super-junction VDMOS device having the step-concentration polysilicon side wall structure as claimed in claim 1, wherein the step-concentration polysilicon side wall pillar is divided into a second step-concentration polysilicon side wall pillar (6) and a first step-concentration polysilicon side wall pillar (5) according to the doping concentration, and the first step-concentration polysilicon side wall pillar (5) is located right below the second step-concentration polysilicon side wall pillar (6).
10. The super-junction VDMOS device with the stepped-concentration polysilicon sidewall structure of claim 1, wherein the active top layer silicon is made of one or more of Si, SiC and GaN semiconductor materials.
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| CN109768090A (en) * | 2019-02-20 | 2019-05-17 | 重庆大学 | A kind of silicon carbide groove profile field oxygen power MOS (Metal Oxide Semiconductor) device with embedded heterojunction diode self-shield |
| CN110034175A (en) * | 2019-03-07 | 2019-07-19 | 电子科技大学 | Longitudinal direction can integrated power device |
| CN115172466B (en) * | 2022-09-05 | 2022-11-08 | 深圳市威兆半导体股份有限公司 | Novel super-junction VDMOS structure and preparation method thereof |
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| US6635544B2 (en) * | 2001-09-07 | 2003-10-21 | Power Intergrations, Inc. | Method of fabricating a high-voltage transistor with a multi-layered extended drain structure |
| JP4939760B2 (en) * | 2005-03-01 | 2012-05-30 | 株式会社東芝 | Semiconductor device |
| JP2007019289A (en) * | 2005-07-08 | 2007-01-25 | Sanken Electric Co Ltd | Semiconductor device |
| KR20130132085A (en) * | 2012-05-25 | 2013-12-04 | 극동대학교 산학협력단 | Super junction power mosfet using deep trench filling |
| CN103681779A (en) * | 2012-09-11 | 2014-03-26 | 无锡华润上华半导体有限公司 | Field effect transistor structure and manufacturing method thereof |
| CN105957896B (en) * | 2016-06-24 | 2019-02-05 | 上海华虹宏力半导体制造有限公司 | Super junction power device and its manufacturing method |
| CN107799419A (en) * | 2016-08-31 | 2018-03-13 | 无锡华润华晶微电子有限公司 | Super junction power device and preparation method thereof |
| CN108550621A (en) * | 2018-04-28 | 2018-09-18 | 重庆大学 | It is a kind of that there is the superjunction silicon carbide VDMOS device for becoming K media slots |
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- 2018-09-30 CN CN201811159206.3A patent/CN109346524B/en active Active
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