CN109346019B - Overcurrent protection control circuit for level shift circuit - Google Patents
Overcurrent protection control circuit for level shift circuit Download PDFInfo
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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Abstract
The invention discloses an overcurrent protection control circuit for a level shift circuit, which can judge whether a detected large current is a stable large current caused by short circuit of a wire of a liquid crystal display panel or a changed large current generated by rapid startup and shutdown, thereby effectively avoiding false triggering of an overcurrent protection circuit and further ensuring the safety and reliability of the whole liquid crystal display device.
Description
Technical Field
The invention relates to the technical field of liquid crystal panels, in particular to an overcurrent protection control circuit for a level shift circuit.
Background
An Active Matrix liquid Crystal Display device (Active Matrix L acquired Crystal Display, AM L CD) is currently the most commonly used Display device, and includes a plurality of pixels, each pixel having a Thin Film Transistor (TFT), a gate of the TFT being connected to a scan line extending in a horizontal direction, a drain of the TFT being connected to a data line extending in a vertical direction, and a source of the TFT being connected to a corresponding pixel electrode.
Compared with the traditional driving method of manufacturing Integrated Circuits (ICs) outside the liquid crystal display panel through a cmos process, the adoption of the GOA architecture can reduce the process steps, reduce the cost, improve the integration of the liquid crystal display panel, and facilitate the realization of ultra-narrow frames and thinness of the panel, but the adoption of the GOA architecture can increase one level Shift chip (L ev Shift IC) on a circuit driving board (PCBA) to boost a low-voltage driving signal to a high-voltage driving signal so as to Drive TFTs in the liquid crystal panel to work.
A Timing Controller (TCON) disposed on a circuit driving board PCBA, the TCON being used for generating and transmitting control signals such as a start signal and a timing signal; and the level shifting chip is arranged on the circuit driving board PCBA and is used for boosting the voltages of the initial signal and the time sequence signal sent by the time sequence controller. And driving the TFT in the GOA framework liquid crystal display panel by the initial signal and the time sequence signal after the voltage is boosted by the level shift chip.
In addition, the level shift circuit is provided with an Over Current Protection (OCP) circuit to prevent a short circuit between clock signals caused by floating dust particles (particles) in the GOA-architecture liquid crystal display panel, and accordingly, the current increases, the corresponding routing lines also heat, the temperature of the pixel units increases, and the polarizer may be melted.
In order to prevent the above situation, it is common to perform an over-current protection using a Power Management integrated circuit (Power Management IC) terminal or a level shift circuit terminal, wherein the Power Management IC terminal mainly performs the over-current protection for the Voltage (VGH) of the gate driver turning on the TFT and the voltage (VG L) of the gate driver turning off the TFT, and the level shift circuit terminal mainly performs a real-time detection of the current level for each channel, and when a large current occurs, directly turns off the output of the level shift circuit to protect the entire liquid crystal display panel.
However, the currently known overcurrent protection circuit of the power management integrated circuit has insufficient accuracy, and may not protect some micro-short-circuited areas. The level shift circuit protects the whole channel in real time. However, due to the design of the liquid crystal display panel, when the liquid crystal display panel is turned on quickly, the output signal CK generates a large current which changes from small to large or from large to small, and although the display of the liquid crystal display panel is not affected, the overcurrent protection circuit is triggered by mistake.
Therefore, it is desirable to provide a new overcurrent protection control circuit for a level shift circuit.
Disclosure of Invention
The invention aims to provide an overcurrent protection control circuit for a level shift circuit, which can judge whether a detected large current is a stable large current caused by short circuit of a liquid crystal display panel wire or a changed large current generated by rapid startup and shutdown, thereby effectively avoiding false triggering of the overcurrent protection circuit and further ensuring the safety and reliability of the whole liquid crystal display device.
The invention provides an overcurrent protection control circuit for a level shift circuit, which comprises: a first logic unit, a second logic unit, a third logic unit, a fourth logic unit and a fifth logic unit; the first logic unit is used for receiving a first detection current and a first reference current, performing logic operation on the first detection current and the first reference current, generating a first output value and outputting the first output value; the second logic unit is used for receiving the first output value, a first error current and a second error current, performing logic operation on the first output value and the first error current to generate a second output value and output the second output value, and performing logic operation on the first output value and the second error current to generate a third output value; the third logic unit is used for receiving a second detection current and a second reference current, performing logic operation on the second detection current and the second reference current, generating and outputting a fourth output value; the fourth logic unit is configured to receive the second output value, the third output value, and the fourth output value, perform logic judgment on the second output value and the fourth output value to generate and output a first judgment result, and perform logic judgment on the third output value and the fourth output value to generate and output a second judgment result; the fifth logic unit is used for receiving the first judgment result and the second judgment result and generating a final judgment result according to the first judgment result and the second judgment result so as to judge whether to trigger an external overcurrent protection circuit.
In an embodiment of the present invention, the first logic unit includes a first subtractor and a first latch, the second logic unit includes a first adder and a second subtractor, the third logic unit includes a third subtractor, the fourth logic unit includes a first comparator and a second comparator, and the fifth logic unit includes an and gate circuit; a first input end of the first subtractor receives a first detection current, a second input end of the first subtractor receives a first reference current, an output end of the first subtractor is electrically connected to the first latch, and the first subtractor is used for outputting a difference between the first detection current and the first reference current as a first output value to the first latch; the first latch is used for caching the received first output value and respectively outputting the cached first output value to the first adder and the second subtractor; a first input end of the first adder is electrically connected to an output end of the first latch, a second input end of the first adder receives a first error current, an output end of the first adder is electrically connected to the first comparator, and the first adder is used for outputting a sum of the first output value and the first error current to the first comparator as a second output value; a first input end of the second subtractor is electrically connected to an output end of the first latch, a second input end of the second subtractor receives a second error current, an output end of the second subtractor is electrically connected to the second comparator, and the second subtractor is configured to output a difference between the first output value and the second error current as a third output value to the second comparator; a first input end of the third subtractor receives a second detection current, a second input end of the third subtractor receives a second reference current, an output end of the third subtractor is electrically connected to the first comparator and the second comparator respectively, and the third subtractor is used for outputting a difference between the second detection current and the second reference current as a fourth output value to the first comparator and the second comparator respectively; wherein the second detection current is obtained after receiving the first detection current and spaced a preset time period; the first input end of the first comparator receives the second output value, the second input end of the first comparator receives the fourth output value, the output end of the first comparator is electrically connected to the first input end of the and circuit, and the first comparator is used for comparing the second output value with the fourth output value and outputting a comparison result serving as a first comparison value to the and circuit; the first input end of the second comparator receives the fourth output value, the second input end of the second comparator receives the third output value, the output end of the second comparator is electrically connected to the second input end of the and circuit, the second comparator is used for comparing the fourth output value with the third output value, and outputting a comparison result serving as a second comparison value to the and circuit; the first input end of the AND gate circuit receives the first comparison value, the second input end of the AND gate circuit receives the second comparison value, the output end of the AND gate circuit is electrically connected to the overcurrent protection circuit, and the AND gate circuit is used for comparing the first comparison value with the second comparison value and judging whether to trigger the overcurrent protection circuit according to the comparison result.
In an embodiment of the invention, when the second output value is greater than the fourth output value, the output of the first comparator is at a high level; when the third output value is greater than the fourth output value, the output of the second comparator is at a high level; when the first input end and the second input end of the AND gate circuit both receive high levels, the output end of the AND gate circuit outputs the high levels and triggers the over-current protection circuit.
In an embodiment of the invention, when the second detection current is equal to the first detection current, the output of the first comparator is at a high level, and the output of the second comparator is at a high level.
In an embodiment of the invention, when a difference between the first detection current and the second detection current is within a first threshold range, the first comparator output is at a high level, and the second comparator output is at a high level.
In an embodiment of the invention, the second reference current is equal to the first reference current.
In an embodiment of the invention, the second error current is equal to the first error current.
In one embodiment of the present invention, the first error current is equal to the product of the first reference current and a first error coefficient; the second error current is equal to the product of the second reference current and a second error coefficient.
In an embodiment of the invention, when the first detection current is greater than the first reference current, it is determined that the first detection current is a large current; and when the second detection current is larger than the second reference current, judging that the second detection current is a large current.
In addition, the invention also provides a display panel which adopts the GOA architecture, the display panel comprises a level shift circuit, and the level shift circuit comprises the overcurrent protection control circuit for the level shift circuit.
The overcurrent protection control circuit for the level shift circuit has the advantages that the overcurrent protection control circuit for the level shift circuit can judge whether the detected large current is stable large current caused by short circuit of the wiring of the liquid crystal display panel or changed large current generated by switching on and switching off, so that the overcurrent protection circuit is effectively prevented from being triggered by mistake, and the safety and the reliability of the whole liquid crystal display device are further ensured.
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In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a circuit connection diagram of an overcurrent protection control circuit for a level shift circuit according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a display panel including an overcurrent protection control circuit for a level shift circuit according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the objects so described are interchangeable under appropriate circumstances. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions.
In this patent document, the drawings discussed below and the embodiments used to describe the principles of the present disclosure are by way of illustration only and should not be construed in any way to limit the scope of the present disclosure. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged system. Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. Further, a terminal according to an exemplary embodiment will be described in detail with reference to the accompanying drawings. Like reference symbols in the various drawings indicate like elements.
The terms used in the description of the present invention are only used to describe specific embodiments, and are not intended to show the concept of the present invention. Unless the context clearly dictates otherwise, expressions used in the singular form encompass expressions in the plural form. In the present specification, it is to be understood that terms such as "comprising," "having," and "containing" are intended to specify the presence of stated features, integers, steps, acts, or combinations thereof, as taught in the present specification, and are not intended to preclude the presence or addition of one or more other features, integers, steps, acts, or combinations thereof. Like reference symbols in the various drawings indicate like elements.
The embodiment of the invention provides an overcurrent protection control circuit for a level shift circuit and a display panel. The details will be described below separately.
The overcurrent protection control circuit for the level shift circuit comprises: a first logic unit, a second logic unit, a third logic unit, a fourth logic unit and a fifth logic unit (not shown).
The first logic unit, the second logic unit, the third logic unit, the fourth logic unit, and the fifth logic unit may be composed of a circuit including a logic device. The logic devices include, but are not limited to: analog logic devices and digital logic devices. Wherein the analog logic device is used for processing analog electrical signals, including but not limited to: comparators, and gates, or gates, etc.; the digital logic device is used for processing devices which represent digital signals by pulse signals, and includes but is not limited to: flip-flops, gates, latches, selectors, etc.
The first logic unit is used for receiving a first detection current and a first reference current, performing logic operation on the first detection current and the first reference current, generating a first output value and outputting the first output value; the second logic unit is used for receiving the first output value, a first error current and a second error current, performing logic operation on the first output value and the first error current to generate a second output value and output the second output value, and performing logic operation on the first output value and the second error current to generate a third output value; the third logic unit is used for receiving a second detection current and a second reference current, performing logic operation on the second detection current and the second reference current, generating and outputting a fourth output value; the fourth logic unit is configured to receive the second output value, the third output value, and the fourth output value, perform logic judgment on the second output value and the fourth output value to generate and output a first judgment result, and perform logic judgment on the third output value and the fourth output value to generate and output a second judgment result; the fifth logic unit is used for receiving the first judgment result and the second judgment result and generating a final judgment result according to the first judgment result and the second judgment result so as to judge whether to trigger an external overcurrent protection circuit.
Referring to fig. 1, a circuit connection diagram of an overcurrent protection control circuit for a level shift circuit according to an embodiment of the present invention is shown. The over-current protection control circuit 100 for a level shift circuit includes a first logic unit, a second logic unit, a third logic unit, a fourth logic unit, and a fifth logic unit (not shown).
In this embodiment, the first logic unit includes a first subtractor 110 and a first latch 120, the second logic unit includes a first adder 130 and a second subtractor 150, the third logic unit includes a third subtractor 170, the fourth logic unit includes a first comparator 140 and a second comparator 160, and the fifth logic unit includes an and gate 180.
Specifically, a first input terminal of the first subtractor 110 receives a first detection current IDetection 1A second input terminal of the first subtractor 110 receives a first reference current IReference 1An output end of the first subtractor 110 is electrically connected to the first latch 120, and the first subtractor 110 is configured to detect the first detection current IDetection 1And the first reference current IReference 1The difference is output as a first output value TP1 to the first latch 120. In this embodiment, when the first detection current IDetection 1Is greater than the first reference current IReference 1Then, the first detection current I is judgedDetection 1Is a large current. That is, if the first detection current IDetection 1Is less than the first reference current IReference 1The operation of the subsequent electronic devices such as subtractors, adders, comparators, etc. is not triggered. In addition, the first reference current IReference 1Is arranged to indicate when the first detected current I isDetection 1Is greater than the first reference current IReference 1Then the first detection current IDetection 1When the first detection current I is a large current (set to a large current caused by short circuit trigger)Detection 1Is less than the first reference current IReference 1Then the first detection current IDetection 1Normal current or low current.
The first latch 120 is configured to buffer the received first output value TP1 and output the buffered first output value TP1 to the first adder 130 and the second subtractor 150, respectively. For example, if the first output value TP1 is a current of 9 amperes, the first latch 120 outputs a current of 9 amperes. The first latch 120 can maintain a time difference (for example, the time difference is 2 milliseconds) between the first detection current and the second detection current, thereby further ensuring the reliability of the entire detection.
A first input terminal of the first adder is electrically connected to an output terminal of the first latch 120, and a second input terminal of the first adder receives a first error current IError 1An output end of the first adder is electrically connected to the first comparator 140, and the first adder is configured to combine the first output value TP1 and the first error current IError 1The sum is output as a second output value TP2 to the first comparator 140. Wherein the first error current IError 1Is equal to the first reference current IReference 1Multiplied by a first error coefficient. The first error current IError 1A very small error current value. For example, the first reference current IReference 1Is 1 ampere, and the first detection current IDetection 110 amperes, the first error current IError 1Equal to 1 × 0.15 ═ 0.15 ampere, where 0.15 is the first error factor.
A first input terminal of the second subtractor 150 is electrically connected to the output terminal of the first latch 120, and a second input terminal of the second subtractor 150 receives a second error current IError 2An output end of the second subtractor 150 is electrically connected to the second comparator 160, and the second subtractor 150 is configured to combine the first output value TP1 and the second error current IError 2The difference is output as a third output TP3 to the second comparator 160. Wherein the second error current IError 2Equal to the product of the second reference current and a second error coefficient. The second error current IError 2A very small error current value. For example, if the second reference current is 1 ampere, the second error isDifferential current IError 2Equal to 1 × 0.1 ═ 0.1 ampere, where 0.1 is the second error factor. In this embodiment, the second error current IError 2Is equal to the first error current IError 1. In some other embodiments, the second error current IError 2May not be equal to the first error current IError 1. In addition, the second reference current is set equal to the first reference current IReference 1Of course, in other embodiments, the second reference current may not be equal to the first reference current.
A first input terminal of the third subtractor 170 receives a second detection current IDetection 2A second input terminal of the third subtractor 170 receives a second reference current IReference 2An output end of the third subtractor 170 is electrically connected to the first comparator 140 and the second comparator 160, respectively, and the third subtractor 170 is configured to detect the second detection current IDetection 2And the second reference current IReference 2The difference is output as a fourth output value TP4 to the first comparator 140 and the second comparator 160, respectively; wherein the received second detection current IDetection 2Is at the received first detection current IDetection 1And obtained after a preset time period. The preset time period may be, for example, 1 ms, but is not limited thereto. In addition, the second reference current IReference 2Is arranged to indicate when the second detected current I isDetection 2Is greater than the second reference current IReference 2Then the second detection current IDetection 2For a large current, when the second detection current IDetection 2Is less than the second reference current IReference 2Then the second detection current IDetection 2Normal current or low current.
The first input terminal of the first comparator 140 receives the second output value TP2, the second input terminal of the first comparator 140 receives the fourth output value TP4, the output terminal of the first comparator 140 is electrically connected to the first input terminal of the and circuit 180, and the first comparator 140 is configured to compare the second output value TP2 with the fourth output value TP4, and output the comparison result to the and circuit 180 as the first comparison value a.
The first input of the second comparator 160 receives the fourth output value TP4, the second input of the second comparator 160 receives the third output value TP3, the output of the second comparator 160 is electrically connected to the second input of the and circuit 180, and the second comparator 160 is configured to compare the fourth output value TP4 with the third output value TP3, and output the comparison result as a second comparison value B to the and circuit 180.
The first input end of the and circuit 180 receives the first comparison value a, the second input end of the and circuit 180 receives the second comparison value B, the output end of the and circuit 180 is electrically connected to the overcurrent protection circuit, and the and circuit 180 is configured to compare the first comparison value a with the second comparison value B, and determine whether to trigger the overcurrent protection circuit according to a comparison result.
In this embodiment, when the second output value TP2 is greater than the fourth output value TP4, the output of the first comparator 140 is at a high level. When the second output value TP2 is less than the fourth output value TP4, then the first comparator 140 output is low.
When the third output value TP3 is greater than the fourth output value TP4, the second comparator 160 output is high. When the third output value TP3 is greater than the fourth output value TP4, the second comparator 160 output is low.
When the first input end and the second input end of the and-gate circuit 180 both receive a high level, the output end of the and-gate circuit 180 outputs the high level and triggers the over-current protection circuit. That is, when the first comparison value a received by the first input terminal of the and circuit 180 and the second comparison value B received by the second input terminal of the and circuit 180 are both at a high level, the and circuit 180 outputs a high level, and the overcurrent protection circuit is triggered. That is, when either the first comparison value a or the second comparison value B is at a low level, the output of the and circuit 180 is at a low level, and the over-current protection circuit is not triggered.
In this embodiment, when the second detection current IDetection 2Is equal to the first detection current IDetection 1When the first comparator 140 output is high, the second comparator 160 output is also high. Then, the output terminal of the and circuit 180 outputs a high level and triggers the overcurrent protection circuit. That is, the first detection current I detected for the first timeDetection 1For high current, after a preset time period, detecting a second detection current I for the second timeDetection 2Is still a large current and is in contact with the first detection current I detected for the first timeDetection 1The same indicates that the detected large current is a constant large current. The constant large current is caused by short circuit of the wires inside the display panel. Therefore, it is necessary to trigger an overcurrent protection measure.
Or, when the first detection current IDetection 1And the second detection current IDetection 2When the difference between the first reference current and the second reference current is within a first threshold range, the output of the first comparator 140 is at a high level, and the output of the second comparator 160 is at a high levelReference 1(equivalent to the second reference current IReference 2) 15% of the total. Then, the output terminal of the and circuit 180 outputs a high level and triggers the overcurrent protection circuit. That is, the first detection current I detected for the first timeDetection 1For high current, after a preset time period, detecting a second detection current I for the second timeDetection 2Is still a large current and is in contact with the first detection current I detected for the first timeDetection 1Approximately the same or nearly the same, indicating that the detected high current is an approximately constant high current. The nearly constant large current is caused by short circuit of the wires inside the display panel. Therefore, it is necessary to trigger an overcurrent protection measure.
Of course, when the second detection current IDetection 2Is not equal to the first detection current IDetection 1And is provided withThe first detection current IDetection 1And the second detection current IDetection 2The difference between them exceeds the first threshold range (e.g. the first reference current I)Reference 115%) of the first and second comparators 140 and 160, one of the outputs is at a high level and the other is at a low level. Thus, the output terminal of the and circuit 180 outputs a low level, and does not trigger the overcurrent protection circuit. That is, the first detection current I detected for the first timeDetection 1For high current, after a preset time period, detecting a second detection current I for the second timeDetection 2Possibly a small current, or a second detected current I detected a second timeDetection 2Is a large current and is in contact with a first detection current I of a first detectionDetection 1The detected large current is a changed large current which is possibly caused by fast startup and shutdown, so that overcurrent protection does not need to be triggered.
The operation of the over-current protection control circuit 100 for a level shift circuit is described below with an embodiment.
Setting a first detection current IDetection 110 amperes, a first reference current IReference 1Is 1 ampere, the first error current IError 10.1 ampere, second reference current IReference 21 ampere, a second error circuit of 0.1 ampere, and a second detection current IDetection 2At 10 amps.
A first input terminal of the first subtractor 110 receives a first detection current I of 10 amperesDetection 1And the second input terminal receives a reference current of 1 ampere, the output terminal of the first subtractor 110 outputs a current of 9 amperes as the first output value TP1, and the first output value TP1 is transmitted to the first latch 120. The first latch 120 receives the 9 a first output TP1 for latching, and still outputs 9 a current, and transmits the current as a first output TP1 to the first adder 130 and the second subtractor 150, respectively.
The first input terminal of the first adder 130 receives a first output value TP1 of 9A, and the second input terminal receives a second output value TP1 of 0.1AAn error current IError 1Then the output terminal of the first adder 130 outputs a current of 9.1 amperes as the second output TP2, and is sent to the first comparator 140.
A first input terminal of the second subtractor 150 receives a first output TP1 of 9 amperes, and a second input terminal receives a second error current I of 0.1 amperesError 2Then the output terminal of the second subtractor 150 outputs a current of 8.9 amperes as a third output value TP3, and is transmitted to the second comparator 160.
A first input terminal of the third subtractor 170 receives a second detection current I of 10 amperesDetection 2The second detection current IDetection 2Is obtaining a first detection current IDetection 1And 3 seconds thereafter. A second input terminal of the third subtractor 170 receives a second reference current I of 1 ampereReference 2The output terminal of the third subtractor 170 outputs a current of 9 amperes and is transmitted as a fourth output value TP4 to the first comparator 140 and the second comparator 160, respectively.
The first input terminal of the first comparator 140 receives the second output value TP2 of 9.1 amperes, the second input terminal receives the fourth output value TP4 of 9 amperes, and the output terminal of the first comparator 140 outputs a high level.
The first input terminal of the second comparator 160 receives the fourth output value TP4 of 9 amperes, the second input terminal receives the third output value TP3 of 8.9 amperes, and the output terminal of the second comparator 160 outputs a high level.
The first input end and the second input end of the and-gate circuit 180 both receive a high level, and the output end of the and-gate circuit 180 also outputs the high level, thereby triggering the overcurrent protection circuit.
From the above description of the operation of the overcurrent protection control circuit 100 for a level shift circuit, it can be seen that when the first detection current I is detectedDetection 1And a second detection current IDetection 2When equal, i.e. when the detected current is a constant current, and the first detected current IDetection 1Greater than a first reference current IReference 1(for judging whether it is a large powerCurrent), it is judged that the constant large current is caused by the short circuit of the wiring and not generated by the rapid on-off, thereby effectively avoiding the false triggering of the overcurrent protection circuit and further ensuring the safety and reliability of the whole liquid crystal display device.
Referring to fig. 2, the present invention further provides a display panel 200, where the display panel 200 is a display panel adopting a GOA architecture, and the display panel 200 includes a level shift circuit, and the level shift circuit includes the above-mentioned over-current protection control circuit 100 for the level shift circuit, which is not described herein again.
The over-current protection control circuit 100 for the level shift circuit has the advantages that the over-current protection control circuit 100 for the level shift circuit can judge whether the detected large current is stable large current caused by short circuit of the wiring of the liquid crystal display panel or changed large current generated by switching on and switching off, so that the over-current protection circuit is effectively prevented from being triggered by mistake, and the safety and the reliability of the whole liquid crystal display device are further ensured.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. An overcurrent protection control circuit for a level shift circuit, the overcurrent protection control circuit comprising: a first logic unit, a second logic unit, a third logic unit, a fourth logic unit and a fifth logic unit;
the first logic unit is used for receiving a first detection current and a first reference current, performing logic operation on the first detection current and the first reference current, generating a first output value and outputting the first output value;
the second logic unit is used for receiving the first output value, a first error current and a second error current, performing logic operation on the first output value and the first error current to generate a second output value and output the second output value, and performing logic operation on the first output value and the second error current to generate a third output value;
the third logic unit is used for receiving a second detection current and a second reference current, performing logic operation on the second detection current and the second reference current, generating and outputting a fourth output value;
the fourth logic unit is configured to receive the second output value, the third output value, and the fourth output value, perform logic judgment on the second output value and the fourth output value to generate and output a first judgment result, and perform logic judgment on the third output value and the fourth output value to generate and output a second judgment result;
the fifth logic unit is used for receiving the first judgment result and the second judgment result and generating a final judgment result according to the first judgment result and the second judgment result so as to judge whether to trigger an external overcurrent protection circuit.
2. The overcurrent protection control circuit for a level shift circuit as set forth in claim 1, wherein the first logic unit includes a first subtractor and a first latch, the second logic unit includes a first adder and a second subtractor, the third logic unit includes a third subtractor, the fourth logic unit includes a first comparator and a second comparator, and the fifth logic unit includes an and gate;
a first input end of the first subtractor receives a first detection current, a second input end of the first subtractor receives a first reference current, an output end of the first subtractor is electrically connected to the first latch, and the first subtractor is used for outputting a difference between the first detection current and the first reference current as a first output value to the first latch;
the first latch is used for caching the received first output value and respectively outputting the cached first output value to the first adder and the second subtractor;
a first input end of the first adder is electrically connected to an output end of the first latch, a second input end of the first adder receives a first error current, an output end of the first adder is electrically connected to the first comparator, and the first adder is used for outputting a sum of the first output value and the first error current to the first comparator as a second output value;
a first input end of the second subtractor is electrically connected to an output end of the first latch, a second input end of the second subtractor receives a second error current, an output end of the second subtractor is electrically connected to the second comparator, and the second subtractor is configured to output a difference between the first output value and the second error current as a third output value to the second comparator;
a first input end of the third subtractor receives a second detection current, a second input end of the third subtractor receives a second reference current, an output end of the third subtractor is electrically connected to the first comparator and the second comparator respectively, and the third subtractor is used for outputting a difference between the second detection current and the second reference current as a fourth output value to the first comparator and the second comparator respectively; wherein the second detection current is obtained after receiving the first detection current and spaced a preset time period;
the first input end of the first comparator receives the second output value, the second input end of the first comparator receives the fourth output value, the output end of the first comparator is electrically connected to the first input end of the and circuit, and the first comparator is used for comparing the second output value with the fourth output value and outputting a comparison result serving as a first comparison value to the and circuit;
the first input end of the second comparator receives the fourth output value, the second input end of the second comparator receives the third output value, the output end of the second comparator is electrically connected to the second input end of the and circuit, the second comparator is used for comparing the fourth output value with the third output value, and outputting a comparison result serving as a second comparison value to the and circuit;
the first input end of the AND gate circuit receives the first comparison value, the second input end of the AND gate circuit receives the second comparison value, the output end of the AND gate circuit is electrically connected to the overcurrent protection circuit, and the AND gate circuit is used for comparing the first comparison value with the second comparison value and judging whether to trigger the overcurrent protection circuit according to the comparison result.
3. The overcurrent protection control circuit for a level shift circuit as set forth in claim 2, wherein the first comparator output is high when the second output value is greater than the fourth output value; when the third output value is greater than the fourth output value, the output of the second comparator is at a high level; when the first input end and the second input end of the AND gate circuit both receive high levels, the output end of the AND gate circuit outputs the high levels and triggers the over-current protection circuit.
4. The overcurrent protection control circuit for a level shift circuit as set forth in claim 3, wherein the first comparator output is high and the second comparator output is high when the second detection current is equal to the first detection current.
5. The overcurrent protection control circuit for a level shift circuit as set forth in claim 3, wherein the first comparator output is high and the second comparator output is high when the difference between the first detected current and the second detected current is within a first threshold range.
6. The overcurrent protection control circuit for a level shift circuit of claim 2, wherein the second reference current is equal to the first reference current.
7. The overcurrent protection control circuit for a level shift circuit of claim 2, wherein the second error current is equal to the first error current.
8. The over-current protection control circuit for a level shift circuit of claim 2, wherein the first error current is equal to a product of the first reference current and a first error coefficient; the second error current is equal to the product of the second reference current and a second error coefficient.
9. The overcurrent protection control circuit for a level shift circuit as set forth in claim 2, wherein the first detection current is determined to be a large current when the first detection current is larger than the first reference current; and when the second detection current is larger than the second reference current, judging that the second detection current is a large current.
10. A display panel, wherein the display panel is a display panel adopting a GOA architecture, and the display panel comprises a level shift circuit, and the level shift circuit comprises the over-current protection control circuit for the level shift circuit according to any one of claims 1 to 9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811401077.4A CN109346019B (en) | 2018-11-22 | 2018-11-22 | Overcurrent protection control circuit for level shift circuit |
| PCT/CN2019/070203 WO2020103308A1 (en) | 2018-11-22 | 2019-01-03 | Overcurrent protection control circuit for use in level shift circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811401077.4A CN109346019B (en) | 2018-11-22 | 2018-11-22 | Overcurrent protection control circuit for level shift circuit |
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| CN109346019A CN109346019A (en) | 2019-02-15 |
| CN109346019B true CN109346019B (en) | 2020-07-10 |
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| CN110120656A (en) * | 2019-05-16 | 2019-08-13 | 深圳市华星光电技术有限公司 | Overcurrent protection circuit and its driving method |
| CN112290505B (en) * | 2020-10-14 | 2023-02-07 | Tcl华星光电技术有限公司 | GOA overcurrent protection detection circuit, protection detection method thereof and electronic device |
| CN114512079A (en) * | 2020-11-16 | 2022-05-17 | 群创光电股份有限公司 | Electronic device |
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| WO2020103308A1 (en) | 2020-05-28 |
| CN109346019A (en) | 2019-02-15 |
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