CN109314620B - Early acknowledgement feedback apparatus and computer readable storage medium for 5G packet transmission - Google Patents

Abstract

An apparatus of an eNB and related method of encoding a 5G packet Downlink (DL) transmission (GDLT), wherein the GDLT includes a plurality of TDD subframes, including a first subframe and a second subframe used to transmit a single PDSCH. The apparatus encodes a PDCCH as part of a GDLT and a PDSCH as part of the GDLT. The PDSCH includes a plurality of PDSCH portions including a first portion included in the first subframe and a second portion included in the second subframe. The apparatus initiates GDLT transmission to the UE and then decodes GDLT-related feedback from the UE while the GDLT is in progress. When the feedback is ACK, the apparatus continues to transmit the GDLT, and when the feedback is NACK or the feedback is not received, the apparatus terminates the GDLT.

Description

Early acknowledgement feedback apparatus and computer readable storage medium for 5G packet transmission

Priority declaration

This application claims the benefit of U.S. provisional application No. 62/356,196 entitled "MECHANISMS ON EARLY ACKNOWLEDGEMENT FEEDBACK FOR GROUPED TRANSMISSION FOR 5G SYSTEMS" filed on 29.6.2016, which is hereby incorporated by reference.

Technical Field

The present disclosure relates to wireless networks and wireless communications. Some aspects relate to 5G systems and include mechanisms for early acknowledgement feedback for packet transmission (grouped transmission).

Background

Mobile communications have evolved from early speech systems to today's highly sophisticated integrated communication platforms. Next generation wireless communication systems (e.g., fifth generation (5G)) may provide better access to information and data sharing for various users and applications. The fifth generation will help provide a unified network/system with the goal of meeting vastly different and sometimes conflicting performance dimensions and services. Such diverse multidimensional demands are driven by different services and applications. In summary, 5G has evolved based on third generation partnership project (3GPP) Long Term Evolution (LTE) with additional potential new Radio Access Technologies (RATs) to enrich people's lives with better, simple, and seamless wireless connectivity solutions. In addition, 5G may enable fast and rich content and services for various devices connected over wireless links. Improved communication is still a goal of the 5G system.

Drawings

The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

fig. 1 is a schematic diagram of a system including a User Equipment (UE) operating between two Radio Access Networks (RANs), according to some aspects.

Fig. 2 is a block timing diagram illustrating one example of a self-contained Time Division Duplex (TDD) subframe structure including a Downlink (DL) subframe transmitted by an eNB to a UE and an Uplink (UL) subframe transmitted by the UE to the eNB, in accordance with some aspects.

Fig. 3 is a block timing diagram illustrating a self-contained TDD subframe structure with aggregation in the DL according to some aspects.

Fig. 4 is a block timing diagram of an aggregated DL data subframe 400 of N aggregated subframes, which DL data subframe 400 may be used to illustrate a problem when a UE misses a DL grant for a PDSCH, according to some aspects.

Fig. 5 is a flow diagram of a process 500 illustrating a detailed process for early feedback for DL packet transmission, according to some aspects.

Fig. 6 is a block timing diagram of an aggregated DL data subframe for DL packet transmission, illustrating one example of early feedback timing of DL packet transmission for a TDD system (option 1), in accordance with some aspects.

Fig. 7 is a block timing diagram of an aggregated DL data subframe for DL packet transmission, illustrating another example of early feedback timing of DL packet transmission for a TDD system (option 2), in accordance with some aspects.

Fig. 8 is a block timing diagram of an aggregated DL data subframe for DL packet transmission illustrating another example of early feedback timing of DL packet transmission for a TDD system, in accordance with some aspects.

Fig. 9 is a flow diagram illustrating a process for early feedback for UL packet transmissions, in accordance with some aspects.

Fig. 10 is a block timing diagram of an aggregate UL data subframe for UL packet transmission illustrating one example of early feedback timing, in accordance with some aspects.

Fig. 11 is a block diagram of an aggregated UL data subframe for UL packet transmission, illustrating another example of early feedback timing, in accordance with some aspects.

FIG. 12 is a block diagram illustrating, in one aspect, example components of an electronic device.

Fig. 13 is a flow diagram illustrating a process for deciding whether to continue or terminate packet transmission, according to some aspects.

Fig. 14 is a flow diagram illustrating another process for deciding whether to continue or terminate packet transmission in accordance with some aspects.

Fig. 15 is a flow diagram of a process for generating and sending feedback related to decoding, according to some aspects.

Fig. 16 is a flow diagram of a process for utilizing feedback regarding transmissions, according to some aspects.

Fig. 17 is a flow diagram of a process for sending a packet UL transmission, according to some aspects.

Fig. 18 is a block diagram of an example machine on which one or more of the techniques (e.g., methods) discussed herein may be executed.

Detailed Description

The following description and the annexed drawings set forth in detail certain illustrative aspects that enable those skilled in the art to practice them. Other aspects may include structural, logical, electrical, process, and other changes. Portions and features of some aspects may be included in, or substituted for, portions and features of other aspects. Variations set forth in the claims encompass available equivalents of those claims.

Fig. 1 is a schematic diagram of a system including a UE 100 operating between two RANs 130, 131 in accordance with various aspects disclosed herein. The UE 100 may be a cellular telephone or some other mobile communication device such as the device 1800 shown in fig. 18 and discussed subsequently.

The system may also include a cellular network 130 (e.g., an evolved universal terrestrial radio access network (E-UTRAN), RAN) having a plurality of cells 111. Each cell 111 may have a base station (e.g., evolved node b (enb)) 112 for communicating within that particular cell 111. A cellular network operator 113, including switches, controllers, and servers (which may also be configured as the device 1800) may be coupled between landline communication lines (e.g., internet, telephone lines) and enbs of the network 130. This provides the UE 100 with wireless access to landline communications. The cellular network 130 may communicate with the UE 100 through 3 GPP.

A Wireless Local Area Network (WLAN)131 of the system may include an Access Point (AP)108 that provides a coverage area 110 for the WLAN 131. When the UE 100 is within the coverage area, it may access landline communication lines (e.g., internet, telephone lines) through the WLAN operator 109. The WLAN operator 109 may also include servers, controllers and switches.

The WLAN 131 may be deployed by the same cellular network operator or a different operator. The WLAN AP 108 is shown logically or physically collocated with the E-UTRAN eNB 112. However, other embodiments may have separate antennas and only substantially overlapping cells 111 and coverage areas 110.

The UE 100 may be moving through an area served by both the WLAN 131 and the cellular network 130. For example, if the UE 100 is communicating with the eNB 112 and traffic overloads the network 130, the UE may be offloaded to the WLAN 131 so that it communicates with the AP 108. Subsequent embodiments may use System Information Block (SIB) information and RAN assistance information. The SIB information may be defined as data sent from the E-UTRAN to the UE that the UE needs to read and decode. The SIB information may be transmitted through a Broadcast Control Channel (BCCH). RAN assistance information may be defined as data broadcast by the E-UTRAN that the UE may use to configure its network settings to enable the UE to communicate with the network and/or make traffic steering decisions. For example, the information may include UTRAN signal strength thresholds and other data.

To enable low latency transmission of enhanced mobile broadband communications, a self-contained Time Division Duplex (TDD) subframe structure may be introduced in a 5G system.

Fig. 2 is a block timing diagram illustrating one example of a self-contained TDD subframe structure including a Downlink (DL) subframe 200 transmitted by the eNB 112 to the UE 100 and an Uplink (UL) subframe 250 transmitted by the UE 100 to the eNB 112, in accordance with some aspects. In fig. 2, to accommodate the DL-to-UL and UL-to-DL switching times and round trip propagation delays, Guard Periods (GP)230, 270 are inserted between a 5G Physical Downlink Shared Channel (PDSCH)220 and a 5G Physical Uplink Control Channel (PUCCH)240, and a 5G Physical Downlink Control Channel (PDCCH)260 and a 5G Physical Uplink Shared Channel (PUSCH) 280. PDCCH 210 of DL data subframe 200 may include Downlink Control Information (DCI)212 carrying a DL grant. Similarly, PDCCH 260 of UL data subframe 250 may include

Fig. 3 is a block timing diagram illustrating a self-contained TDD subframe structure 300 with aggregation in the DL, according to some aspects. For large cell sizes, the round trip propagation delay may be large, and thus the size of the GP 230, 270 may be large. To reduce GP 230 overhead, two or more subframes 205A, 205B (collectively or representatively referred to as 205) may be aggregated for one PDSCH 220 or PUSCH 280 transmission for one particular UE 100. As shown in fig. 3, the PDSCH 220A, 220B (which may be collectively referred to herein as 220) spans two subframes 205, and the GP 230 is inserted in the second subframe 205B. In this case, the GP overhead can be reduced by half compared to the TDD subframe structure 200 as shown in fig. 2.

When a relatively large number of subframes 205 are aggregated for PDSCH 220 or PUSCH 280 transmissions, if the UE 100 misses the Downlink Control Information (DCI)212 carrying a DL grant, all PDSCHs 220 in the aggregated subframes may be lost, which may result in a significant loss of spectral efficiency.

Fig. 4 is a block timing diagram of an aggregated DL data subframe 400 of N aggregated subframes, which may be used to illustrate a problem when a UE 100 misses a DL grant for a PDSCH 220, in accordance with some aspects. If the UE 100 misses the DL grant in the DCI 212, all transmissions in the N aggregated subframes are lost.

Various aspects described herein provide mechanisms for 5G systems to enable early acknowledgement feedback to inform the eNB 112 of the results of at least DCI 212 decoding operations for these aggregated transmissions in multiple Subframes (SFs), which may enable improved system throughput and spectral efficiency. More specifically, various aspects described herein provide the following mechanisms: a mechanism to enable early acknowledgement feedback for DL packet (grouped) transmissions; and mechanisms to enable early acknowledgement feedback for UL packet transmissions.

Mechanism to enable early feedback for DL packet transmission

Fig. 5 is a flow chart of a process 500 showing a detailed process for early feedback for DL packet transmission. In particular, early feedback for DL packet transmission may include the following operations. In operation S505, the eNB 112 may transmit to the UE 100 a PDCCH 210 carrying one or more subframes 205 and a packetized PDSCH 220, where the PDCCH 210 carries DL Downlink Control Information (DCI)212 indicating transmission of the packetized PDSCH 220 and an indicator to enable early feedback.

In operation S510, the UE 100 may report feedback-header K by transmitting Acknowledgement (ACK) (success) or Negative (NACK) (failure) to the eNB 112 through the PUCCH 240 in the allocated resources₀Whether PDCCH 210 or PDSCH 220 in subframe 205 was successfully decoded. K₀The value of (c) may be predefined in the specification or configured by higher layers (the general term "higher layer" as used herein may be defined as "higher layer") via, for example, 5G Master Information Block (MIB), 5G System Information Block (SIB), or Radio Resource Control (RRC) signaling, or explicitly indicated in the DCI 212, and K is₀<L (where L is the total number of subframes 205).

In operation S515, the eNB 112 receives feedback from the UE 100 and determines whether it is ACK or NACK. The UE 100 may not send feedback to the eNB 112 if the UE 100 fails to decode the PDCCH 210. In this case, the eNB 112 may treat the feedback from the UE 100 as a NACK. If the reported feedback is an ACK (S515: ACK), the eNB 112 proceeds with the transmission of the packet PDSCH carrying the subsequent subframe. If the reported feedback is a NACK (S515: NACK or no response), the eNB 112 terminates the packet PDSCH transmission.

In various aspects, one or more of the operations of the processes depicted in fig. 5 may be rearranged, omitted, or combined with one or more other processes discussed herein.

The indication to enable early feedback for DL or UL packet transmission may be indicated in the DCI 212 format for DL assignment or UL grant. In another option, it may be configured by higher layers in a cell-specific or UE-specific manner via a 5G Master Information Block (MIB), a 5G System Information Block (SIB), or RRC signaling. In some designs, configuration information related to grouped or aggregated transmission of the DL or UL may be signaled in a UE-specific manner, which may include a number of consecutive subframes scheduled by a single DCI format, a set of ACK/NACK timelines received for the PDCCH, and an ACK/NACK timeline for the PDSCH scheduled by the PDCCH. Alternatively or additionally, one index of the configured ACK/NACK timeline for PDCCH and PDSCH may be dynamically signaled as part of the DCI format.

Alternatively, the indication to enable early feedback for DL or UL packet transmission may be implicitly determined based on the number of aggregated subframes used for packet transmission. Early feedback may be implicitly enabled if the number of aggregated subframes used for packet transmission is greater than a predefined threshold, and vice versa.

Various aspects of the early feedback mechanism for DL packet transmission are described below.

In an aspect, the UE 100 may provide a feedback ACK/NACK via the PUCCH 240 in the allocated resources in the determined subframe to indicate whether the associated PDCCH 210 was successfully decoded. Specifically, in the case where the UE 100 decodes the PDCCH 210 in the subframe 205A in which the PDCCH 210 is transmitted, the UE 100 may provide feedback ACK/NACK in the same subframe 205A. If the UE 100 fails to decode the PDCCH 210, the UE 100 may not transmit anything to the eNB 112. In this case, the eNB 112 may consider the feedback (or no feedback) from the UE 100 as a NACK.

As described above, the ACK/NACK may be transmitted via the PUCCH 240. In one option, PUCCH 240 utilizing a first format (format 1) of the switching transmission scheme may be used for ACK/NACK transmission. More specifically, the UE 100 may transmit PUCCH 240 format 1 for ACK in case the UE 100 successfully decodes PDCCH 210, and the UE 100 does not transmit anything in case the UE 100 fails to decode PDCCH 210.

In another aspect, PUCCH 240 format 1a may be used to carry ACK/NACK feedback bits. More specifically, when the UE 100 successfully decodes the PDCCH 210, the UE 100 may transmit "ACK ═ 1" through the PUCCH 240 format 1 a. In case that the UE 100 fails to decode the PDCCH 210, the UE 100 does not transmit anything.

Fig. 6 is a block timing diagram of an aggregated DL data subframe 600 for DL packet transmission, illustrating one example of early feedback timing of DL packet transmission for a TDD system (option 1), in accordance with some aspects. In this example, in subframe # n, eNB 112 transmits PDCCH 210 carrying DL grants for packet transmission in five subframes. In the first subframe 205A, the UE 100 provides feedback of ACK/NACK via the PUCCH 240. When the eNB 112 receives ACK/NACK feedback from the UE 100, the eNB 112 may decide whether to continue or terminate the PDSCH transmission 600 in the remaining subframes.

In some aspects, after the eNB 112 receives the ACK/NACK feedback from the UE 100, the eNB 112 may send another PDCCH 210 to indicate whether the packet PDSCH transmission 600 is terminated.

Fig. 7 is a block timing diagram of an aggregated DL data subframe 700 for DL packet transmission illustrating another example of early feedback timing of DL packet transmission for a TDD system (option 2), according to some aspects. In this example, in subframe # n, eNB 112 transmits PDCCH 210A carrying a DL grant for packet transmission in five subframes. In the first subframe 205A, the UE 100 provides feedback of ACK/NACK via the PUCCH 240. In addition, in subframe # (n +2)205C, eNB 112 transmits PDCCH 210C to indicate whether packet PDSCH 700 is terminated or continued.

In another aspect, the UE 100 may provide feedback of ACK/NACK via PUCCH 240 in the allocated resources to indicate whether PDSCH 220 in the first L subframes was successfully decoded, where the value L may be predefined in the specification or configured by higher layers. In one example, L ═ 1 to allow earliest feedback.

Considering UE 100 processing delay for decoding PDSCH 220, eNB 112 may indicate PUCCH 240 resources for ACK/NACK feedback k subframes after receiving DL DCI 212, and k may be indicated in DL DCI 212.

Fig. 8 is a block timing diagram of an aggregated DL data subframe 800 for DL packet transmission illustrating another example of early feedback timing of DL packet transmission for a TDD system, in accordance with some aspects. In this example, the UE 100 provides feedback in subframe # (n +2)205C for the first PDSCH 220A transmission in subframe # n 205A — a hybrid automatic repeat request (HARQ) ACK/NACK. Subsequently, based on the feedback received in subframe # (n +2)205C, the eNB 112 may continue or terminate PDSCH transmission in the remaining subframes, such as subframe # (n +3) 205D.

Although the various aspects are described as being applicable to a TDD system, the above mechanisms can also be extended directly to support Frequency Division Duplex (FDD) systems.

On the other hand, if carrier aggregation is enabled, ACK/NACK may be reported via another Component Carrier (CC), so that the frame structure of DL packet transmission in fig. 4 may be preserved. The feedback CC index may be indicated by the DCI 212 in the current CC. If an uplink grant of a feedback CC is received, the ACK/NACK may be reported through the PUCCH 240 or the PUSCH 280.

Various aspects may support separate acknowledgement of PDCCH 210 for aggregate transmission scheduling on DL or UL and associated PDSCH 220 or PUSCH 280 scheduled by PDCCH 210, 260. It may include identifying PDCCH 210 for aggregate transmission scheduling in subframe n. Upon detecting PDCCH 210, UE 100 may send two ACK/NACK feedbacks. A first ACK/NACK may be sent in UL subframe n + k, which provides an acknowledgement response at least for the detected PDCCH 210. For a detected PDSCH 220 scheduled by PDCCH 210, a second ACK/NACK feedback may be sent in UL subframe n + m. The values k and m may be different. More specifically, the value m may be greater than the value k. These two values may be configured by higher layer signaling or system information or determined in the specification, or dynamically signaled as part of PDCCH 210.

Mechanism to enable early feedback for UL packet transmission

In the current LTE protocol, there is no acknowledgement sent by the UE 100 to the eNB 112 after receiving the UL grant. For aggregated UL transmissions, a feature in 5G may be provided to inform the eNB 112 of PDCCH 210 reception to avoid significant waste of resources due to PDCCH 210 false detections. In order for the UE 100 to recognize the aggregated UL grant, an ACK/NACK may be transmitted using PUCCH 240 resources associated with the UL grant, or by explicit signaling using a portion of the UL grant. Alternatively, a two-stage DCI 212 format design may be considered to support early feedback from the eNB 112 to the UE 100 to control the transmission of packet transmissions, as described in further detail below.

Fig. 9 is a flow diagram illustrating a process 900 for early feedback for UL packet transmissions, in accordance with some aspects. In particular, early feedback for UL packet transmission may include: in operation S905, the eNB 112 may transmit a PDCCH carrying UL DCI indicating a packet PUSCH transmission and enabling early feedback. In operation S910, the UE 100 may transmit a packet PUSCH in resources indicated by the UL DCI. In operation S912, the eNB may send an indication to the UE 100 via the PDCCH or a 5G physical HARQ indicator channel (xPHICH) to indicate whether the UE 100 continues or terminates the PUSCH transmission. In operation S915, the UE may receive feedback from the eNB 112 and decide whether to terminate the PUSCH transmission. If not (S915: ACK), the UE 100 continues packet PUSCH transmission in the subsequent subframe in operation S920. If so (S915: NACK or no response), the UE 100 terminates the packet PUSCH transmission in operation S925.

In various aspects, one or more of the operations of the processes depicted in fig. 9 may be rearranged, omitted, or combined with one or more other processes discussed herein. The timing of the early feedback from the eNB 112 may be predefined in the specification or configured by higher layers. Alternatively, the timing may be dynamically indicated in the UL DCI 262, which the UL DCI 262 may be used to trigger a packet PUSCH transmission. In one example, a gap between a first PUSCH transmission and a PDCCH carrying early feedback may be indicated in DCI, which may be used to trigger a packet PUSCH transmission. In addition, the early feedback indication may be represented as a single bit of information or in the form of HARQ ACK/NACK.

Fig. 10 is a block timing diagram of an aggregated UL data subframe 1000 for UL packet transmission, illustrating one example of early feedback timing, in accordance with some aspects. In this example, PUSCH 270B transmission begins at subframe # (n +1)205B, subframe # (n +1)205B being scheduled by PDCCH 260A in subframe # n 205A. In addition, PDCCH 260C carrying early feedback is transmitted in subframe # (n +2) 205C. When the UE 100 receives the indication from the eNB 112, the UE 100 may continue or terminate the packet PUSCH transmission in the remaining subframes.

In another aspect, the UE 100 may provide feedback in the form of an ACK/NACK via PUCCH in the allocated resources in the determined subframe to indicate whether the associated PDCCH carrying the UL grant was successfully decoded.

Fig. 11 is a block diagram of an aggregated UL data subframe 1100 for UL packet transmission, illustrating another example of early feedback timing, in accordance with some aspects. In this example, when PDCCH 260A carrying a UL grant is transmitted, UE 100 provides feedback ACK/NACK 265A for PDCCH 260A in the same subframe 205A.

Applications/embodiments

As used herein, the term "circuitry" may refer to, be or include the following: an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide the described functionality. In some aspects, a circuit may be implemented in one or more software or firmware blocks, or functions associated with a circuit may be implemented by one or more software or firmware blocks. In some aspects, a circuit may include logic operable, at least in part, in hardware. Aspects described herein may be implemented as a system using any suitably configured hardware and/or software.

FIG. 12 is a block diagram that illustrates, in one aspect, example components of an electronic device 1200. In various aspects, the electronic device 1200 may be, implement, incorporate, or otherwise be part of: a user equipment such as the UE 100 described above, an evolved NodeB such as the eNB 112 described above, or any other suitable electronic device. In some aspects, the electronic device 1200 may include application circuitry 1202, baseband circuitry 1204, Radio Frequency (RF) circuitry 1206, Front End (FE) circuitry 1208, and one or more antennas 1210 coupled together at least as shown.

The application circuitry 1202 may include one or more application processors. For example, the application circuitry 1202 may include circuitry such as, but not limited to, one or more single-core or multi-core processors 1202A. The one or more processors 1202A may include any combination of general-purpose processors and special-purpose processors (e.g., graphics processors, application processors, etc.). Processor 1202A can be coupled with and/or can include computer-readable medium 1202B (also referred to as "CRM 1202B," "memory 1202B," "storage 1202B," or "memory/storage 1202B") and can be configured to execute instructions stored in CRM 1202B to enable various applications and/or operating systems to run on the system.

The baseband circuitry 1204 may include circuitry such as, but not limited to, one or more single-core or multi-core processors. Baseband circuitry 1204 may include one or more baseband processors and/or control logic to process baseband signals received from the receive signal path of RF circuitry 1206 and to generate baseband signals for the transmit signal path of RF circuitry 1206. Baseband circuitry 1204 may interface with application circuitry 1202 for generating and processing baseband signals and for controlling operation of RF circuitry 1206. For example, in some aspects, the baseband circuitry 1204 may include a second generation (2G) baseband processor 1204A, a third generation (3G) baseband processor 1204B, a fourth generation (4G) baseband processor 1204C, and/or one or more other baseband processors 1204D for other existing generations, generations under development or to be developed in the future (e.g., fifth generation (5G), sixth generation (6G), etc.). The baseband circuitry 1204 (e.g., one or more of the baseband processors 1204A-d) may handle various radio control functions that enable communication with one or more radio networks via the RF circuitry 1206. The radio control functions may include, but are not limited to, signal modulation/demodulation, encoding/decoding, radio frequency shifting, and the like. In some aspects, the modulation/demodulation circuitry of baseband circuitry 1204 may include Fast Fourier Transform (FFT), precoding, and/or constellation mapping/demapping functionality. In some aspects, the encoding/decoding circuitry of baseband circuitry 1204 may include convolution, tail-biting convolution, turbo, viterbi, and/or Low Density Parity Check (LDPC) encoder/decoder functionality. Aspects of the modulation/demodulation and encoder/decoder functions are not limited to these examples, and may include other suitable functions in other aspects.

In some aspects, the baseband circuitry 1204 may include elements of a protocol stack, such as, for example, elements of an evolved universal terrestrial radio access network (E-UTRAN) protocol, including, for example, Physical (PHY), Medium Access Control (MAC), Radio Link Control (RLC), Packet Data Convergence Protocol (PDCP), and/or Radio Resource Control (RRC) elements. A Central Processing Unit (CPU)1204E of the baseband circuitry 1204 may be configured to run elements of a protocol stack for signaling of the PHY, MAC, RLC, PDCP, and/or RRC layers. In some aspects, the baseband circuitry may include one or more audio Digital Signal Processors (DSPs) 1204F. The one or more audio DSPs 1204F may include elements for compression/decompression and echo cancellation, and may otherwise include other suitable processing elements. The baseband circuitry 1204 may also include a computer-readable medium 1204B (also referred to as "CRM 1204B," "memory 1204B," "storage 1204B," or "CRM 1204B"). CRM 1204G may be used to load and store data and/or instructions for operations performed by the processor of baseband circuitry 1204. For one aspect, CRM 1204G can include any combination of suitable volatile memory and/or non-volatile memory. CRM 1204G may include any combination of various levels of memory/storage, including but not limited to Read Only Memory (ROM) with embedded software instructions (e.g., firmware), random access memory (e.g., Dynamic Random Access Memory (DRAM), cache memory, buffers, etc.). CRM 1204G may be shared among various processors or dedicated to a particular processor. In some aspects, the components of the baseband circuitry 1204 may be combined as appropriate in a single chip, a single chipset, or disposed on the same circuit board. In some aspects, some or all of the constituent components of the baseband circuitry 1204 and the application circuitry 1202 may be implemented together, such as, for example, on a system on a chip (SOC).

In some aspects, the baseband circuitry 1204 may provide communications compatible with one or more radio technologies. For example, in some aspects, the baseband circuitry 1204 may support communication with E-UTRAN and/or other Wireless Metropolitan Area Networks (WMANs), Wireless Local Area Networks (WLANs), Wireless Personal Area Networks (WPANs). Aspects of the baseband circuitry 1204 that are configured to support radio communications of more than one wireless protocol may be referred to as multi-mode baseband circuitry.

The RF circuitry 1206 may enable communication with a wireless network using modulated electromagnetic radiation through a non-solid medium. In various aspects, the RF circuitry 1206 may include switches, filters, amplifiers, and the like to facilitate communication with a wireless network. The RF circuitry 1206 may include a receive signal path, which may include circuitry to down-convert RF signals received from the FEM circuitry 1208 and provide baseband signals to the baseband circuitry 1204. RF circuitry 1206 may also include a transmit signal path, which may include circuitry to up-convert baseband signals provided by baseband circuitry 1204 and provide RF output signals to FEM circuitry 1208 for transmission.

In some aspects, the RF circuitry 1206 may include a receive signal path and a transmit signal path. The receive signal path of the RF circuitry 1206 may include a mixer circuit 1206A, an amplifier circuit 1206B, and a filter circuit 1206C. The transmit signal path of the RF circuitry 1206 may include a filter circuit 1206C and a mixer circuit 1206A. The RF circuitry 1206 may also include synthesizer circuitry 1206D to synthesize frequencies used by the mixer circuitry 1206A of the receive signal path and the transmit signal path. In some aspects, the mixer circuit 1206A of the receive signal path may be configured to down-convert the RF signal received from the FEM circuit 1208 based on a synthesized frequency provided by the synthesizer circuit 1206D. The amplifier circuit 1206B may be configured to amplify the downconverted signal, and the filter circuit 1206C may be a Low Pass Filter (LPF) or a Band Pass Filter (BPF) configured to remove unwanted signals from the downconverted signal to generate an output baseband signal. The output baseband signal may be provided to baseband circuitry 1204 for further processing. In some aspects, the output baseband signal may be a zero frequency baseband signal, but this is not required. In some aspects, mixer circuit 1206A of the receive signal path may comprise a passive mixer, although the scope of aspects is not limited in this respect.

In some aspects, the mixer circuitry 1206A of the transmit signal path may be configured to upconvert an input baseband signal based on a synthesis frequency provided by the synthesizer circuitry 1206D to generate an RF output signal for the FEM circuitry 1208. The baseband signal may be provided by baseband circuitry 1204 and may be filtered by filter circuitry 1206C. Filter circuit 1206C may include a Low Pass Filter (LPF), although the scope of these aspects is not limited in this respect.

In some aspects, mixer circuit 1206A of the receive signal path and mixer circuit 1206A of the transmit signal path may include two or more mixers and may be arranged for quadrature downconversion and/or upconversion, respectively. In some aspects, the mixer circuit 1206A of the receive signal path and the mixer circuit 1206A of the transmit signal path may include two or more mixers and may be arranged for image rejection (e.g., Hartley image rejection). In some aspects, mixer circuit 1206A of the receive signal path and mixer circuit 1206A of the transmit signal path may be arranged for direct down-conversion and/or direct up-conversion, respectively. In some aspects, mixer circuit 1206A of the receive signal path and mixer circuit 1206A of the transmit signal path may be configured for superheterodyne operation.

In some aspects, the output baseband signal and the input baseband signal may be analog baseband signals, although the scope of these aspects is not limited in this respect. In some alternative aspects, the output baseband signal and the input baseband signal may be digital baseband signals. In these alternative aspects, the RF circuitry 1206 may include analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuitry, and the baseband circuitry 1204 may include a digital baseband interface to communicate with the RF circuitry 1206.

In some dual-mode aspects, separate radio IC circuits may be provided for processing signals for each spectrum, although the scope of these aspects is not limited in this respect.

In some aspects, synthesizer circuit 1206D may be a fractional-N synthesizer or a fractional N/N +1 synthesizer, although the scope of these aspects is not limited in this respect as other types of frequency synthesizers may be suitable. For example, synthesizer circuit 1206D may be a delta-sigma synthesizer, a frequency multiplier, or a synthesizer including a phase locked loop with a frequency divider. The synthesizer circuit 1206D may be configured to synthesize an output frequency based on the frequency input and the divider control input for use by the mixer circuit 1206A of the RF circuit 1206. In some aspects, the synthesizer circuit 1206D may be a fractional N/N +1 synthesizer.

In some aspects, the frequency input may be provided by a Voltage Controlled Oscillator (VCO), but this is not required. The divider control input may be provided by the baseband circuitry 1204 or the application circuitry 1202, depending on the desired output frequency. In some aspects, the divider control input (e.g., N) may be determined from a look-up table based on the channel indicated by the application circuitry 1202.

Synthesizer circuit 1206D of RF circuit 1206 may include a frequency divider, a Delay Locked Loop (DLL), a multiplexer, and a phase accumulator. In some aspects, the divider may be a dual-mode divider (DMD) and the phase accumulator may be a Digital Phase Accumulator (DPA). In some aspects, the DMD may be configured to divide an input signal by N or N +1 (e.g., based on a carry) to provide a fractional division ratio. In some various aspects, a DLL may include a set of cascaded, tunable delay elements, a phase detector, a charge pump, and a D-type flip-flop. In these aspects, the delay elements may be configured to decompose the VCO period into Nd equal phase groups, where Nd is the number of delay elements in the delay line. Thus, the DLL provides negative feedback to help ensure that the total delay through the delay line is one VCO cycle.

In some aspects, synthesizer circuit 1206D may be configured to generate a carrier frequency as the output frequency, while in other aspects, the output frequency may be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency) and used in conjunction with a quadrature generator and divider circuit to generate a plurality of signals having a plurality of carrier frequencies with different phases relative to each other. In some aspects, the output frequency may be an LO frequency (fLO). In some aspects, the RF circuit 1206 may include an IQ/polarity converter.

The FEM circuitry 1208 may include a receive signal path, which may include circuitry configured to operate on RF signals received from the one or more antennas 1210, amplify the received signals, and provide amplified versions of the received signals to the RF circuitry 1206 for further processing. The FEM circuitry 1208 may also include a transmit signal path, which may include circuitry configured to amplify signals provided by the RF circuitry 1206 for transmission by one or more of the one or more antennas 1210. In some aspects, the FEM circuitry 1208 may include a TX/RX switch to switch between transmit mode and receive mode operation. The FEM circuitry 1208 may include a receive signal path and a transmit signal path. The receive signal path of the FEM circuitry may include a Low Noise Amplifier (LNA) to amplify the received RF signal and provide the amplified receive RF signal as an output (e.g., to the RF circuitry 1206). The transmit signal path of the FEM circuitry 1208 may include a Power Amplifier (PA) to amplify an input RF signal (e.g., provided by the RF circuitry 1206), and one or more filters to generate the RF signal for subsequent transmission (e.g., by one or more of the one or more antennas 1210).

In some aspects, the electronic device 1200 may include additional elements, such as, for example, a display, a camera, one or more sensors, and/or interface circuitry (e.g., an input/output (I/O) interface or bus) (not shown). In aspects in which the electronic device is implemented in or by an eNB, the electronic device 1200 may include network interface circuitry. The network interface circuits may be one or more computer hardware components that connect the electronic device 1200 to one or more network elements, such as one or more servers within a core network or one or more other enbs, via a wired connection. To this end, the network interface circuitry may include one or more special purpose processors and/or Field Programmable Gate Arrays (FPGAs) to communicate using one or more network communication protocols, such as the X2 Application Protocol (AP), S1AP, Stream Control Transmission Protocol (SCTP), ethernet, point-to-point (PPP), Fiber Distributed Data Interface (FDDI), and/or any other suitable network communication protocol.

In various aspects, the electronic device 1200 of fig. 12 may be used to: transmitting a packet Downlink (DL) transmission to a User Equipment (UE), wherein the packet DL transmission comprises a Physical Downlink Control Channel (PDCCH) transmission and a Physical Downlink Shared Channel (PDSCH) transmission in one or more subframes, wherein the PDCCH is to carry Downlink Control Information (DCI), and wherein the DCI comprises an indicator for the packet DL transmission and an early feedback indicator; receiving feedback from the UE based on the packet DL transmission; determining whether the packet DL transmission is decoded correctly based on the feedback, wherein the packet DL transmission is decoded correctly when the PDCCH transmission and/or the PDSCH transmission are decoded correctly in a predetermined number of subframes; and continuing to transmit the packet DL transmission in one or more subsequent subframes when the feedback indicates that the PDCCH transmission and/or the PDSCH transmission is decoded correctly or terminating transmission of the packet DL transmission when the feedback indicates that the PDCCH transmission and/or the PDSCH transmission is not decoded correctly. In such an aspect, the electronic device 1200 may be or may be implemented in an eNB.

In various aspects, the electronic device 1200 of fig. 12 may be used to: receiving a packet Downlink (DL) transmission, wherein the packet DL transmission comprises a Physical Downlink Control Channel (PDCCH) transmission and a Physical Downlink Shared Channel (PDSCH) transmission in one or more subframes, wherein the PDCCH is to carry Downlink Control Information (DCI), and wherein the DCI includes an indicator for the packet DL transmission and an early feedback indicator; sending feedback based on the packet DL transmission; decoding a packet DL transmission; generating feedback based on whether the packet DL transmission is decoded correctly, wherein the packet DL transmission is decoded correctly when the PDCCH transmission and/or the PDSCH transmission is decoded correctly in a predetermined number of subframes; and terminating receiving the packet DL transmission when the feedback indicates that the PDCCH transmission and/or the PDSCH transmission is not decoded correctly, or continuing receiving the packet DL transmission in one or more subsequent subframes when the feedback indicates that the PDCCH transmission and/or the PDSCH transmission is decoded correctly. In such an aspect, the electronic device 1200 may be or may be implemented in a UE. In some aspects, the electronic device of fig. 12 may be configured to perform one or more processes, techniques, and/or methods as described herein, or portions thereof.

Fig. 13 is a flow diagram illustrating a process 1300 for determining whether to continue or terminate packet transmission, according to some aspects. For example, process 1300 may include: in operation S1305, an indicator and early feedback for a packet 5G Physical Downlink Shared Channel (PDSCH) are received by a UE via Downlink Control Information (DCI) carried by a 5G Physical Downlink Control Channel (PDCCH). The process may include: in operation S1310, Acknowledgement (ACK) feedback is reported by the UE via a 5G Physical Uplink Control Channel (PUCCH) in the allocated resources to indicate a header K₀Whether the PDCCH or PDSCH in each subframe is successfully decoded. The process may include determining, by the eNB, whether to continue or terminate the packet PDSCH transmission based on the feedback. In various aspects, one or more of the operations of the processes depicted in fig. 13 may be rearranged, omitted, or combined with one or more other processes discussed herein.

Fig. 14 is a flow diagram illustrating another process 1400 for determining whether to continue or terminate packet transmissions, in accordance with some aspects. For example, the process may include: in operation S1405, a packet Downlink (DL) transmission is transmitted or caused to be transmitted. In various aspects, a packet DL transmission may include a Physical Downlink Control Channel (PDCCH) transmission and a Physical Downlink Shared Channel (PDSCH) transmission in one or more subframes. In various aspects, the PDCCH may carry Downlink Control Information (DCI). In various aspects, the DCI may include an indicator for packet DL transmission and an early feedback indicator. The process may include: in operation S1410, feedback based on packet DL transmission is received or caused to be received. The process may include: in operation S1415, a determination is made or caused to be made whether the packet DL transmission is decoded correctly based on the feedback. In various aspects, a packet DL transmission may have been correctly decoded when a PDCCH transmission and/or a PDSCH transmission are correctly decoded in a predetermined number of subframes. The process may include: in operation S1420, transmission of the packet DL transmission is terminated or continued based on the feedback. In various aspects, the process may include: terminating or causing to terminate transmission of the packet DL transmission when the feedback indicates that the PDCCH transmission and/or the PDSCH transmission is not decoded correctly, or causing to continue or cause to continue the packet DL transmission in one or more subsequent subframes when the feedback indicates that the PDCCH transmission and/or the PDSCH transmission is decoded correctly. In various aspects, the process depicted in fig. 14 may be performed by an eNB. In various aspects, one or more of the operations of the process depicted in fig. 14 may be rearranged, omitted, or combined with one or more other processes discussed herein.

Fig. 15 is a flow diagram of a process 1500 for generating and sending feedback related to decoding, according to some aspects. For example, the procedure 1500 may include, in operation S1505, sending or causing to be sent a PDCCH transmission carrying DCI. In various aspects, other DCIs may include an indicator to indicate that packet Uplink (UL) transmission is allowed and an early feedback indicator. The process may include receiving or causing to be received a packet UL transmission in a resource indicated by the DCI at operation S1510. The process may include decoding or causing to be decoded the received packet UL transmission at operation S1515. The process may include generating or causing to be generated feedback at operation S1520. In various aspects, the feedback may indicate whether the received packet UL transmission was decoded correctly. The process may include sending or causing to be sent feedback to indicate whether the received packet UL transmission was decoded correctly at operation S1525. In various aspects, the process depicted in fig. 15 may be performed by an eNB. In various aspects, one or more of the operations of the processes depicted in fig. 15 may be rearranged, omitted, or combined with one or more other processes discussed herein.

Fig. 16 is a flow diagram of a process 1600 for utilizing feedback regarding transmissions, in accordance with some aspects. For example, process 1600 may include: in operation S1605, a packet Downlink (DL) transmission is received or caused to be received. In various aspects, a packet DL transmission may include a Physical Downlink Control Channel (PDCCH) transmission and a Physical Downlink Shared Channel (PDSCH) transmission in one or more subframes. In various aspects, the PDCCH may carry Downlink Control Information (DCI), which may include an indicator for packet DL transmission and an early feedback indicator. The process may include: in operation S1610, a packet DL transmission is decoded or caused to be decoded. The process may include: in operation S1615, feedback is generated or caused to be generated based on whether the packet DL transmission is decoded correctly. In various aspects, a packet DL transmission may have been correctly decoded when a PDCCH transmission and/or a PDSCH transmission are correctly decoded in a predetermined number of subframes. The process may include: in operation S1620, feedback is transmitted or caused to be transmitted. The process may include: in operation S1625, reception of the packet DL transmission is terminated or continued. In various aspects, the process may include: terminating or causing to terminate reception of the packet DL transmission when the feedback indicates that the PDCCH transmission and/or the PDSCH transmission is not decoded correctly, or continuing or causing to continue the packet DL transmission in one or more subsequent subframes when the feedback indicates that the PDCCH transmission and/or the PDSCH transmission is decoded correctly. In various aspects, the process depicted in fig. 16 may be performed by a UE. In various aspects, one or more of the operations of the process depicted in fig. 16 may be rearranged, omitted, or combined with one or more other processes discussed herein.

Fig. 17 is a flow diagram of a process 1700 for sending a packet UL transmission, according to some aspects. For example, process 1700 may include: in operation S1705, a PDCCH transmission carrying DCI is received or caused to be received. In various aspects, the DCI may include an indicator to indicate that packet Uplink (UL) transmission is allowed and an early feedback indicator. The process may include: in operation S1710, a packet UL transmission is transmitted or caused to be transmitted in the resource indicated by the DCI. The process may include: in operation S1715, another feedback indicating whether the received packet UL transmission was decoded correctly is received or caused to be received. In various aspects, the process depicted in fig. 17 may be performed by a UE. In various aspects, one or more of the operations of the processes depicted in fig. 17 may be rearranged, omitted, or combined with one or more other processes discussed herein.

Fig. 18 is a block diagram of an example machine 1800 on which one or more of the techniques (e.g., methods) discussed herein may be executed. In alternative aspects, the machine 1800 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the machine 1800 may operate in the capacity of a server machine, a client machine, or both, in server-client network environments. In one example, the machine 1800 may operate as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 1800 may be a master station, an HE station, a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a portable communication device, a mobile telephone, a smart phone, a network appliance, a network router, switch or bridge, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that machine. Additionally, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein, such as cloud computing, software as a service (SaaS), other computer cluster configurations.

The machine (e.g., computer system) 1800 may include a hardware processor 1802 (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a hardware processor core, or any combination thereof), a main memory 1804, and a static memory 1806, some or all of which may communicate with each other via an interconnection link (e.g., bus) 1808.

Specific examples of main memory 1804 include Random Access Memory (RAM) and semiconductor memory devices, which in some various aspects may include memory cells in a semiconductor such as registers. Specific examples of static memory 1806 include: non-volatile memories such as semiconductor memory devices (e.g., electrically programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; a RAM; and CD-ROM and DVD-ROM disks.

The machine 1800 may also include a display device 1810, an input device 1812 (e.g., a keyboard), and a User Interface (UI) navigation device 1814 (e.g., a mouse). In one example, the display device 1810, the input device 1812, and the UI navigation device 1814 may be a touch screen display. The machine 1800 may additionally include a mass storage device (e.g., drive unit) 1816, a signal generation device 1818 (e.g., a speaker), a network interface device 1820, and one or more sensors 1821, such as a Global Positioning System (GPS) sensor, compass, accelerometer, or other sensor. The machine 1800 may include an output controller 1828, such as a serial (e.g., Universal Serial Bus (USB)), parallel, or other wired or wireless (e.g., Infrared (IR), Near Field Communication (NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.). In some various aspects, the processor 1802 and/or the instructions 1824 may include processing circuitry and/or transceiver circuitry.

The storage device 1816 may include a machine-readable medium 1822 having stored thereon one or more sets of data structures or instructions 1824 (e.g., software) embodying or used by any one or more of the techniques or functions described herein. The instructions 1824 may also reside, completely or at least partially, within the main memory 1804, within static memory 1806, or within the hardware processor 1802 during execution thereof by the machine 1800. In one example, one or any combination of the hardware processor 1802, the main memory 1804, the static memory 1806, or the storage device 1816 may constitute machine-readable media.

Specific examples of the machine-readable medium may include: non-volatile memories such as semiconductor memory devices (e.g., EPROM or EEPROM) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; a RAM; and CD-ROM and DVD-ROM disks.

While the machine-readable medium 1822 is shown to be a single medium, the term "machine-readable medium" can include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated cache memories and servers) configured to store the one or more instructions 1824.

The devices of machine 1800 may be one or more of the following: a hardware processor 1802 (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a hardware processor core, or any combination thereof), a main memory 1804 and a static memory 1806, sensors 1821, a network interface device 1820, an antenna 1860, a display device 1810, an input device 1812, a UI navigation device 1814, a mass storage 1816, instructions 1824, a signal generation device 1818, and an output controller 1828. The apparatus may be configured to perform one or more of the methods and/or operations disclosed herein. The apparatus may be intended as a component of the machine 1800 to perform and/or be a part of one or more of the methods and/or operations disclosed herein. In some various aspects, the device may include a pin or other device for receiving power. In some various aspects, the apparatus may include power conditioning hardware.

The term "machine-readable medium" may include any medium that is capable of storing, encoding or carrying instructions for execution by the machine 1800 and that cause the machine 1800 to perform any one or more of the techniques of this disclosure, or that is capable of storing, encoding or carrying data structures used by or associated with such instructions. Non-limiting examples of machine-readable media may include solid-state memory, and optical and magnetic media. Specific examples of the machine-readable medium may include: non-volatile memories such as semiconductor memory devices (e.g., electrically programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; random Access Memory (RAM); and CD-ROM and DVD-ROM disks. In some examples, the machine-readable medium may include a non-transitory machine-readable medium. In some examples, a machine-readable medium may include a machine-readable medium that is not a transitory propagating signal.

The instructions 1824 may also be transmitted or received over a communication network 1826 using a transmission medium via the network interface device 1820 using any one of a number of transmission protocols (e.g., frame relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks may include a Local Area Network (LAN), a Wide Area Network (WAN), a packet data network (e.g., the Internet), a mobile telephone network (e.g., a cellular network), a Plain Old Telephone (POTS) network, and a wireless data network (e.g., referred to as a "WLAN")

Of the Institute of Electrical and Electronics Engineers (IEEE)802.11 family of standards, referred to as

IEEE 802.16 family of standards), IEEE 802.15.4 family of standards, Long Term Evolution (LTE) family of standards, Universal Mobile Telecommunications System (UMTS) family of standards, peer-to-peer (P2P) networks, and the like.

In one example, the network interface device 1820 may include one or more physical jacks (e.g., ethernet, coaxial, or telephone jacks) or one or more antennas to connect to the communication network 1826. In one example, the network interface device 1820 may include one or more antennas 1860 to wirelessly communicate using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) techniques. In some examples, the network interface device 1820 may communicate wirelessly using multi-user MIMO techniques. The term "transmission medium" shall be taken to include any intangible medium that is capable of storing, encoding or carrying instructions for execution by the machine 1800, and includes digital or analog communications signals or other intangible medium to facilitate communication of such software.

As described herein, an example may include, or may operate on, logic or multiple components, modules, or mechanisms. A module is a tangible entity (e.g., hardware) capable of performing specified operations and may be configured or arranged in a certain manner. In one example, a circuit arrangement (e.g., internal or with respect to an external entity such as other circuits) may be treated as a module in a specified manner. In one example, all or a portion of one or more computer systems (e.g., stand-alone, client or server computer systems) or one or more hardware processors may be configured by firmware or software (e.g., instructions, application portions, or applications) as a module that operates to perform specified operations. In one example, the software may reside on a machine-readable medium. In one example, software, when executed by the underlying hardware of the module, causes the hardware to perform specified operations.

Thus, the term "module" is understood to encompass a tangible entity, be it an entity of physical construction, specially configured (e.g., hardwired), or temporarily (e.g., temporarily) configured (e.g., programmed) to operate in a specified manner or to perform some or all of any of the operations described herein. Considering the example where modules are temporarily configured, each module need not be instantiated at any one time. For example, where the modules include a general purpose hardware processor configured using software, the general purpose hardware processor may be configured as respective different modules at different times. The software may configure the hardware processor accordingly, e.g., to constitute a particular module at one time and another module at another time.

Some of the various aspects may be implemented in whole or in part in software and/or firmware. The software and/or firmware may take the form of instructions contained in or on a non-transitory computer-readable storage medium. Those instructions may then be read and executed by one or more processors to enable performance of the operations described herein. The instructions may be in any suitable form, such as but not limited to source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. Such computer-readable media may include any tangible, non-transitory media for storing information in a form readable by one or more computers, such as, but not limited to, Read Only Memory (ROM); random Access Memory (RAM); a magnetic disk storage medium; an optical storage medium; flash memory, etc.

For the purposes of promoting an understanding of the principles of the disclosure, reference has been made to various configurations illustrated in the drawings, and specific language has been used to describe the same. However, the scope of the inventive subject matter is not intended to be limited to the particular language, and the inventive subject matter should be construed to include all aspects and configurations that would normally occur to one of ordinary skill in the art. Configurations herein may be described in terms of functional block components and various processing steps. Such functional blocks may be implemented by any number of components that perform the specified functions. The particular embodiments shown and described herein are illustrative examples and are not intended to limit the scope of the inventive subject matter in any way. In some cases, the lines or connections shown in the various figures presented may be intended to represent example functional relationships and/or physical or logical couplings between the various elements. However, many alternative or additional functional relationships, physical connections, or logical connections may be present in a practical device. In addition, no item or component is required unless the element is specifically described as "required" or "critical". Many modifications and adaptations will be apparent to those skilled in the art.

Examples of the invention

Example 1 is an apparatus of an enhanced node b (enb), the apparatus comprising: a memory; and a processor configured to: encoding a 5G packet Downlink (DL) transmission (GDLT) to the memory, wherein the GDLT comprises a plurality of Time Division Duplex (TDD) subframes including first and second subframes used to transmit a single Physical Downlink Shared Channel (PDSCH); encoding a Physical Downlink Control Channel (PDCCH) as part of a GDLT; encoding a PDSCH as part of a GDLT, wherein the PDSCH includes a plurality of PDSCH portions including a first portion included in a first subframe and a second portion included in a second subframe; initiate a GDLT transmission to a User Equipment (UE); and decoding GDLT related feedback from the UE while the GDLT is in progress, wherein when the feedback is an Acknowledgement (ACK), the processor is configured to cause the GDLT to continue, and when the feedback is Negative (NACK) or no feedback is received, the processor is configured to cause the GDLT to terminate.

In example 2, the subject matter of example 1 optionally includes: wherein the processor is further configured to: when the feedback indicates that the PDCCH or PDSCH transmission is decoded correctly, the GDLT is continued by transmitting one or more subsequent subframes containing the additional PDSCH portion.

In example 3, the subject matter of any one or more of examples 1-2 optionally includes: wherein the indication of the GDLT or the early feedback indicator is included in a Master Information Block (MIB), a System Information Block (SIB), or a Radio Resource Control (RRC) message.

In example 4, the subject matter of example 3 optionally includes: wherein the indication of the GDLT or the early feedback indicator is implicitly determined based on a predetermined number of aggregated subframes of the GDLT such that the GDLT or the early feedback is enabled when the number of aggregated subframes of the GDLT is greater than a predefined threshold.

In example 5, the subject matter of example 4 optionally includes: wherein the predetermined number of subframes is predefined or indicated by Downlink Control Information (DCI).

In example 6, the subject matter of any one or more of examples 1-5 optionally includes: wherein the processor is further configured to decode feedback from a Physical Uplink Control Channel (PUCCH) in the allocated resources.

In example 7, the subject matter of example 6 can optionally include utilizing ACK/NACK feedback bits.

In example 8, the subject matter of any one or more of examples 1-7 optionally includes: wherein the processor is further configured to encode another PDCCH transmission to indicate whether the GDLT is terminated.

In example 9, the subject matter of any one or more of examples 1-8 optionally includes, wherein: when carrier aggregation is enabled, the processor is further configured to decode feedback via a Component Carrier (CC); and the feedback CC index is indicated by Downlink Control Information (DCI) in the current CC.

In example 10, the subject matter of example 9 optionally includes: wherein the processor is further configured to decode feedback from a PUCCH or a Physical Uplink Shared Channel (PUSCH).

In example 11, the subject matter of example 10 optionally includes: wherein the feedback comprises: first feedback for PDCCH transmission; and second feedback for PDSCH transmissions scheduled by the PDCCH.

In example 12, the subject matter of example 11 can optionally include: wherein the processor is further configured to: decoding the first feedback in subframe n + k; and decoding the second feedback in subframe n + m, wherein a PDCCH carrying a DL grant for packet transmission is encoded for subframe n.

In example 13, the subject matter of example 12 optionally includes: wherein the value of m is greater than the value of k.

In example 14, the subject matter of example 13 optionally includes: where the value of k and the value of m are predefined or indicated using higher layer signaling, system information, or dynamically signaled as part of the PDCCH.

In example 15, the subject matter of example 14 can optionally include: wherein the processor is further configured to: encoding a PDCCH carrying another DCI, wherein the another DCI includes an indicator indicating to the UE that 5G packet Uplink (UL) transmission (GULT) is allowed and another early feedback indicator; decoding a GULT in a resource indicated by another DCI; encoding another feedback indicating whether the GULT is decoded correctly; and initiating transmission to the UE including the further feedback.

In example 16, the subject matter of example 15 optionally includes: wherein the other feedback is encoded in PDCCH or physical hybrid automatic repeat request indicator channel (xPHICH).

In example 17, the subject matter of any one or more of examples 15-16 optionally includes: wherein the processor is further configured to: when another feedback indicates that the GULT is decoded correctly, continue decoding the GULT; and terminating decoding of the GULT when another feedback indicates that the GULT is not decoded correctly.

In example 18, the subject matter of any one or more of examples 15-17 optionally includes: wherein, the GULT contains PUSCH.

Example 19 is an apparatus of a User Equipment (UE), the apparatus comprising: a memory; and a processor configured to: decoding a 5G packet Downlink (DL) transmission (GDLT) received from an eNB to the memory, wherein the GDLT comprises a plurality of Time Division Duplex (TDD) subframes including first and second subframes used to transmit a single Physical Downlink Shared Channel (PDSCH); decoding a Physical Downlink Control Channel (PDCCH) that is part of the GDLT; decoding a PDSCH that is part of a GDLT, wherein the PDSCH includes a plurality of PDSCH portions including a first portion included in a first subframe and a second portion included in a second subframe; and encoding GDLT related feedback for the eNB while the GDLT is ongoing, wherein the feedback is an Acknowledgement (ACK) when the PDCCH or PDSCH portion is successfully decoded and a Negative (NACK) when the PDCCH or PDSCH portion is not successfully decoded.

In example 20, the subject matter of example 19 optionally includes: wherein the processor is further configured to: decoding of the GDLT continues by decoding one or more subsequent subframes containing the additional PDSCH portion, and providing feedback to the eNB indicating that the PDCCH transmission or PDSCH transmission was decoded correctly.

In example 21, the subject matter of any one or more of examples 19-20 optionally includes: wherein the indication of the GDLT or the early feedback indicator is included in a Master Information Block (MIB), a System Information Block (SIB), or a Radio Resource Control (RRC) message.

In example 22, the subject matter of any one or more of examples 19-21 optionally includes: wherein the processor is further configured to encode the feedback in a Physical Uplink Control Channel (PUCCH) in the allocated resources.

In example 23, the subject matter of example 22 can optionally include utilizing ACK/NACK feedback bits.

Example 24 is a computer-readable storage medium storing instructions for execution by processing circuitry of a wireless communication device as an eNB to configure the device to: encoding a 5G packet Downlink (DL) transmission (GDLT), wherein the GDLT comprises a plurality of Time Division Duplex (TDD) subframes including first and second subframes used to transmit a single Physical Downlink Shared Channel (PDSCH); encoding a Physical Downlink Control Channel (PDCCH) as part of a GDLT; encoding a PDSCH as part of a GDLT, wherein the PDSCH includes a plurality of PDSCH portions including a first portion included in a first subframe and a second portion included in a second subframe; initiate a GDLT transmission to a User Equipment (UE); and decoding GDLT related feedback from the UE while the GDLT is in progress, wherein when the feedback is an Acknowledgement (ACK), the processor is configured to cause the GDLT to continue, and when the feedback is Negative (NACK) or no feedback is received, the processor is configured to cause the GDLT to terminate.

In example 25, the subject matter of example 24 can optionally include: wherein the instructions further configure the device to: when the feedback indicates that the PDCCH or PDSCH transmission is decoded correctly, the GDLT is continued by transmitting one or more subsequent subframes containing the additional PDSCH portion.

Example 26 is a non-transitory computer-readable storage medium storing instructions for execution by processing circuitry of a wireless communication device as an eNB to configure the device to: encoding a 5G packet Downlink (DL) transmission (GDLT), wherein the GDLT comprises a plurality of Time Division Duplex (TDD) subframes including first and second subframes used to transmit a single Physical Downlink Shared Channel (PDSCH); encoding a Physical Downlink Control Channel (PDCCH) as part of a GDLT; encoding a PDSCH as part of a GDLT, wherein the PDSCH includes a plurality of PDSCH portions including a first portion included in a first subframe and a second portion included in a second subframe; initiating a GDLT transmission to a User Equipment (UE); and decoding GDLT-related feedback from the UE while the GDLT is in progress, wherein when the feedback is an Acknowledgement (ACK), the processor is configured to cause the GDLT to continue, and when the feedback is Negative (NACK) or the feedback is not received, the processor is configured to cause the GDLT to terminate.

Example 27 is an apparatus comprising means for performing one or more of the elements described in examples 1-25.

Example 28 is one or more non-transitory computer-readable media comprising instructions to cause an electronic device to perform one or more elements described in examples 1-25 when the instructions are executed by one or more processors of the electronic device.

Example 29 is an apparatus comprising logic or circuitry to perform one or more elements described in examples 1-25.

Example 30 is a method, technique, or process as described in examples 1-25.

Example 31 is an apparatus, comprising: one or more processors and one or more computer-readable media comprising instructions that, when executed by the one or more processors, cause the one or more processors to perform a method, technique, or process as described in examples 1-25.

Example 32 is a system to perform operations as described in examples 1-25.

Example 33 is a method of operating an enhanced node b (enb) comprising a processor and a memory, the method comprising: encoding a 5G packet Downlink (DL) transmission (GDLT) to the memory, wherein the GDLT includes a plurality of Time Division Duplex (TDD) subframes including first and second subframes used to transmit a single Physical Downlink Shared Channel (PDSCH); encoding a Physical Downlink Control Channel (PDCCH) as part of a GDLT; encoding a PDSCH as part of a GDLT, wherein the PDSCH includes a plurality of PDSCH portions including a first portion included in a first subframe and a second portion included in a second subframe; initiate a GDLT transmission to a User Equipment (UE); and decoding GDLT related feedback from the UE while the GDLT is in progress, wherein when the feedback is an Acknowledgement (ACK), the processor is configured to cause the GDLT to continue, and when the feedback is Negative (NACK) or no feedback is received, the processor is configured to cause the GDLT to terminate.

In example 34, the subject matter of example 33 optionally includes: when the feedback indicates that the PDCCH or PDSCH transmission is decoded correctly, the GDLT is continued by transmitting one or more subsequent subframes containing the additional PDSCH portion.

In example 35, the subject matter of any one or more of examples 33-34 optionally includes: wherein the indication of the GDLT or the early feedback indicator is included in a Master Information Block (MIB), a System Information Block (SIB), or a Radio Resource Control (RRC) message.

In example 36, the subject matter of example 35 can optionally include determining the indication of GDLT or the early feedback indicator implicitly based on a predetermined number of aggregated subframes of GDLT such that GDLT or early feedback is enabled when the number of aggregated subframes of GDLT is greater than a predefined threshold.

In example 37, the subject matter of example 36 can optionally include: wherein the predetermined number of subframes is predefined or indicated by Downlink Control Information (DCI).

In example 38, the subject matter of any one or more of examples 33-37 optionally includes decoding feedback from a Physical Uplink Control Channel (PUCCH) in the allocated resources.

In example 39, the subject matter of example 38 can optionally include utilizing ACK/NACK feedback bits.

In example 40, the subject matter of any one or more of examples 33-39 may optionally include encoding another PDCCH transmission to indicate whether the GDLT is terminated.

In example 41, the subject matter of any one or more of examples 33-40 optionally includes, wherein: decoding feedback via a Component Carrier (CC) when carrier aggregation is enabled; and the feedback CC index is indicated by Downlink Control Information (DCI) in the current CC.

In example 42, the subject matter of example 41 optionally includes decoding feedback from a PUCCH or a Physical Uplink Shared Channel (PUSCH).

In example 43, the subject matter of example 42 can optionally include: wherein the feedback comprises: first feedback for PDCCH transmission; and second feedback for PDSCH transmissions scheduled by the PDCCH.

In example 44, the subject matter of example 43 can optionally include: decoding the first feedback in subframe n + k; and decoding the second feedback in subframe n + m, wherein a PDCCH carrying a DL grant for packet transmission is encoded for subframe n.

In example 45, the subject matter of example 44 can optionally include: wherein the value of m is greater than the value of k.

In example 46, the subject matter of example 45 optionally includes: where the value of k and the value of m are predefined or indicated using higher layer signaling, system information, or dynamically signaled as part of the PDCCH.

In example 47, the subject matter of example 46 can optionally include: encoding a PDCCH carrying another DCI, wherein the another DCI includes an indicator indicating to the UE that 5G packet Uplink (UL) transmission (GULT) is allowed and another early feedback indicator; decoding a GULT in a resource indicated by another DCI; encoding another feedback indicating whether the GULT is decoded correctly; and initiating transmission to the UE including the further feedback.

In example 48, the subject matter of example 47 optionally includes: wherein the other feedback is encoded in PDCCH or physical hybrid automatic repeat request indicator channel (xPHICH).

In example 49, the subject matter of any one or more of examples 47-48 optionally includes: when another feedback indicates that the GULT is decoded correctly, continue decoding the GULT; and terminating decoding of the GULT when another feedback indicates that the GULT is not decoded correctly.

In example 50, the subject matter of any one or more of examples 47-49 optionally includes: wherein, the GULT contains PUSCH.

Example 51 is a method of a User Equipment (UE), comprising: decoding a 5G packet Downlink (DL) transmission (GDLT) received from an eNB to a memory, wherein the GDLT includes a plurality of Time Division Duplex (TDD) subframes including first and second subframes used to transmit a single Physical Downlink Shared Channel (PDSCH); decoding a Physical Downlink Control Channel (PDCCH) that is part of the GDLT; decoding a PDSCH that is part of a GDLT, wherein the PDSCH includes a plurality of PDSCH portions including a first portion included in a first subframe and a second portion included in a second subframe; and encoding GDLT related feedback for the eNB while the GDLT is ongoing, wherein the feedback is an Acknowledgement (ACK) when the PDCCH or PDSCH portion is successfully decoded and a Negative (NACK) when the PDCCH or PDSCH portion is not successfully decoded.

In example 52, the subject matter of example 51 can optionally include: decoding of the GDLT continues by decoding one or more subsequent subframes containing the additional PDSCH portion, and providing feedback to the eNB indicating that the PDCCH transmission or PDSCH transmission was decoded correctly.

In example 53, the subject matter of any one or more of examples 51-52 optionally includes: wherein the indication of the GDLT or the early feedback indicator is included in a Master Information Block (MIB), a System Information Block (SIB), or a Radio Resource Control (RRC) message.

In example 54, the subject matter of any one or more of examples 51-53 may optionally include encoding the feedback in a Physical Uplink Control Channel (PUCCH) in the allocated resources.

In example 55, the subject matter of example 54 can optionally include utilizing ACK/NACK feedback bits.

Example 56 is an enhanced node b (enb), comprising: means for encoding a 5G packet Downlink (DL) transmission (GDLT), wherein the GDLT comprises a plurality of Time Division Duplex (TDD) subframes including first and second subframes used to transmit a single Physical Downlink Shared Channel (PDSCH); means for encoding a Physical Downlink Control Channel (PDCCH) as part of a GDLT; means for encoding a PDSCH as part of a GDLT, wherein the PDSCH includes a plurality of PDSCH portions including a first portion included in a first subframe and a second portion included in a second subframe; means for initiating a GDLT transmission to a User Equipment (UE); and means for decoding GDLT-related feedback from the UE while the GDLT is in progress, wherein when the feedback is an Acknowledgement (ACK), the processor is configured to cause the GDLT to continue, and when the feedback is Negative (NACK) or no feedback is received, the processor is configured to cause the GDLT to terminate.

Example 57 is an operating User Equipment (UE), comprising: means for decoding a 5G packet Downlink (DL) transmission (GDLT) received from an eNB to a memory, wherein the GDLT includes a plurality of Time Division Duplex (TDD) subframes including first and second subframes used to transmit a single Physical Downlink Shared Channel (PDSCH); means for decoding a Physical Downlink Control Channel (PDCCH) that is part of the GDLT; means for decoding a PDSCH that is part of a GDLT, wherein the PDSCH includes a plurality of PDSCH portions including a first portion included in a first subframe and a second portion included in a second subframe; and means for encoding GDLT related feedback for the eNB while the GDLT is ongoing, wherein the feedback is an Acknowledgement (ACK) when the PDCCH or PDSCH portion is successfully decoded and a Negative Acknowledgement (NACK) when the PDCCH or PDSCH portion is not successfully decoded.

Example 58 is an apparatus comprising means for performing one or more of the elements described in examples 1-57.

Example 59 is one or more non-transitory computer-readable media comprising instructions to cause an electronic device to perform one or more elements described in examples 1-57 when the instructions are executed by one or more processors of the electronic device.

Example 60 is an apparatus comprising logic or circuitry to perform one or more elements described in examples 1-57.

Example 61 is a method, technique, or process as described in examples 1-57.

Example 62 is an apparatus, comprising: one or more processors and one or more computer-readable media comprising instructions that, when executed by the one or more processors, cause the one or more processors to perform a method, technique, or process as described in examples 1-57.

Example 63 is a system to perform operations as described in examples 1-57.

The foregoing description of one or more embodiments provides illustration and description, but is not intended to be exhaustive or to limit the scope of aspects to the precise form disclosed. Modifications and variations are possible in light of the above teachings or may be acquired from practice of various aspects.

Claims (25)

1. An apparatus of a base station, the apparatus comprising: a memory; and a processor configured to:

encoding a 5G packet downlink transmission (GDLT) to the memory, wherein the GDLT comprises a plurality of Time Division Duplex (TDD) subframes including a first subframe and a second subframe used to transmit a single Physical Downlink Shared Channel (PDSCH);

encoding a physical downlink control channel, PDCCH, as part of a GDLT;

encoding a PDSCH as part of a GDLT, wherein the PDSCH comprises a plurality of PDSCH portions including a first portion included in a first subframe and a second portion included in a second subframe;

initiating transmission of a GDLT to a User Equipment (UE); and

decoding GDLT-related feedback from the UE while the GDLT is in progress, wherein when the feedback is an Acknowledgement (ACK), the processor is configured to cause the GDLT to continue, and when the feedback is a negative NACK or no feedback is received, the processor is configured to cause the GDLT to terminate.

2. The apparatus of claim 1, wherein the processor is further configured to: when the feedback indicates that the PDCCH or PDSCH transmission is decoded correctly, the GDLT is continued by transmitting one or more subsequent subframes containing the additional PDSCH portion.

3. The apparatus of claim 1, wherein the indication of the GDLT or the early feedback indicator is included in a master information block, MIB, a system information block, SIB, or a radio resource control, RRC, message.

4. The apparatus of claim 3, wherein the indication of the GDLT or the early feedback indicator is implicitly determined based on a predetermined number of aggregated subframes of the GDLT such that the GDLT or the early feedback is enabled when the number of aggregated subframes of the GDLT is greater than a predefined threshold.

5. The apparatus of claim 4, wherein the predetermined number of subframes is predefined or indicated by downlink control information, DCI.

6. The apparatus of claim 1, in which the processor is further configured to decode feedback from a physical uplink control channel, PUCCH, in the allocated resources.

7. The apparatus of claim 6, in which the feedback is carried via PUCCH format 1 with a switched transmission scheme or PUCCH format 1a with ACK/NACK feedback bits.

8. The apparatus of claim 1, wherein the processor is further configured to encode another PDCCH transmission to indicate whether a GDLT is terminated.

9. The apparatus of claim 1, wherein:

when carrier aggregation is enabled, the processor is further configured to decode feedback via Component Carriers (CCs); and is

The feedback CC index is indicated by downlink control information DCI in the current CC.

10. The apparatus of claim 9, in which the processor is further configured to decode feedback from a PUCCH or a physical uplink shared channel, PUSCH.

11. The apparatus of claim 10, wherein the feedback comprises:

first feedback for PDCCH transmissions; and

second feedback for PDSCH transmissions scheduled by PDCCH.

12. The apparatus of claim 11, wherein the processor is further configured to:

decoding the first feedback in subframe n + k; and

decoding the second feedback in subframe n + m, wherein the PDCCH carrying the downlink DL grant for the packet transmission is encoded for subframe n.

13. The apparatus of claim 12, wherein the value of m is greater than the value of k.

14. The apparatus of claim 13, in which a value of k and a value of m are predefined or indicated using higher layer signaling, system information, or dynamically signaled as part of a PDCCH.

15. The apparatus of claim 14, wherein the processor is further configured to:

encoding a PDCCH carrying another DCI, wherein the another DCI comprises an indicator indicating to the UE that 5G packet uplink transmission GULT is allowed and another early feedback indicator;

decoding a GULT in a resource indicated by the other DCI;

encoding another feedback indicating whether the GULT is decoded correctly; and

initiate transmission to the UE including the other feedback.

16. The apparatus of claim 15, wherein the other feedback is encoded in PDCCH or physical hybrid automatic repeat request indicator channel PHICH.

17. The apparatus of claim 15, wherein the processor is further configured to:

when the further feedback indicates that the GULT is decoded correctly, continuing to decode the GULT; and

terminating the decoding of the GULT when the further feedback indicates that the GULT was not decoded correctly.

18. The apparatus of claim 15, wherein a GULT comprises a PUSCH.

19. An apparatus of a User Equipment (UE), the apparatus comprising: a memory; and a processor configured to:

decoding a 5G packet downlink transmission (GDLT) received from a base station to the memory, wherein the GDLT comprises a plurality of Time Division Duplex (TDD) subframes including a first subframe and a second subframe used to transmit a single Physical Downlink Shared Channel (PDSCH);

decoding a physical downlink control channel, PDCCH, as part of the GDLT;

decoding a PDSCH that is part of a GDLT, wherein the PDSCH includes a plurality of PDSCH portions including a first portion included in the first subframe and a second portion included in the second subframe; and

encoding GDLT-related feedback for the base station while GDLT is ongoing, wherein the feedback is an Acknowledgement (ACK) when a PDCCH or PDSCH portion is successfully decoded and a negative NACK when the PDCCH or PDSCH portion is unsuccessfully decoded.

20. The apparatus of claim 19, wherein the processor is further configured to: continuing decoding of the GDLT by decoding one or more subsequent subframes containing the additional PDSCH portion, and providing feedback to the base station indicating that the PDCCH transmission or PDSCH transmission is decoded correctly.

21. The apparatus of claim 19, wherein the indication of GDLT or the early feedback indicator is included in a master information block, MIB, a system information block, SIB, or a radio resource control, RRC, message.

22. The apparatus of claim 19, in which the processor is further configured to encode the feedback in a physical uplink control channel, PUCCH, in the allocated resources.

23. The apparatus of claim 22, in which the feedback is carried via PUCCH format 1 with a switching transmission scheme or PUCCH format 1a with ACK/NACK feedback bits.

24. A computer-readable storage medium storing instructions for execution by processing circuitry of a wireless communication device as a base station to configure the device to:

encoding a 5G packet downlink transmission (GDLT), wherein the GDLT comprises a plurality of Time Division Duplex (TDD) subframes including a first subframe and a second subframe used to transmit a single Physical Downlink Shared Channel (PDSCH);

encoding a physical downlink control channel, PDCCH, as part of a GDLT;

encoding a PDSCH as part of a GDLT, wherein the PDSCH comprises a plurality of PDSCH portions including a first portion included in the first subframe and a second portion included in the second subframe;

initiating transmission of a GDLT to a User Equipment (UE); and

decoding GDLT-related feedback from the UE while GDLT is in progress, wherein when the feedback is an Acknowledgement (ACK), the processor is configured to cause GDLT to continue, and when the feedback is a negative NACK or no feedback is received, the processor is configured to cause GDLT to terminate.

25. The medium of claim 24, wherein the instructions further configure the device to: when the feedback indicates that the PDCCH or PDSCH transmission is decoded correctly, the GDLT is continued by transmitting one or more subsequent subframes containing the additional PDSCH portion.

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