CN109308374B - Layout parameter extraction method for polygonal spiral inductance device - Google Patents
Layout parameter extraction method for polygonal spiral inductance device Download PDFInfo
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- CN109308374B CN109308374B CN201810927476.8A CN201810927476A CN109308374B CN 109308374 B CN109308374 B CN 109308374B CN 201810927476 A CN201810927476 A CN 201810927476A CN 109308374 B CN109308374 B CN 109308374B
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
The invention relates to a layout parameter extraction method of a polygonal spiral inductance device, which relates to a semiconductor integrated circuit manufacturing technology, wherein the polygonal spiral inductance device comprises a first outgoing line, a second outgoing line and an outer ring protection ring, and the method comprises the following steps: drawing an auxiliary layer, wherein the auxiliary layer is rectangular, two opposite sides of the auxiliary layer are respectively overlapped with the inner walls of the first outgoing line and the second outgoing line, and the other two opposite sides of the auxiliary layer are respectively overlapped with the inner walls of the outer ring protection rings; generating a derivative inner diameter rectangle inside the spiral inductance coil of the inductance device by using the position relation between the auxiliary layer and the inner walls of the first outgoing line, the second outgoing line and the outer ring protection ring through an electronic design automation tool EDA; generating a technical file for calculating the inner diameter R and the number of turns N of the induction coil through an electronic design automation tool EDA; and operating the technical file to extract the parameters of the inductance device so as to accurately extract the parameters of the inductance device, improve the layout drawing efficiency of the inductance device and reduce the error risk.
Description
Technical Field
The invention relates to a semiconductor integrated circuit manufacturing technology, in particular to a layout parameter extraction method of a polygonal spiral inductance device.
Background
In the semiconductor integrated circuit technology, with the development of integrated technology, the process node of integrated circuit fabrication is continuously reduced, and a System On Chip (SOC) becomes a design hotspot, and in the field of Radio Frequency Integrated Circuit (RFIC) design, a designer adopts a radio frequency system on chip (RF SOC) design. In radio frequency system on chip (RF SOC) design, designers choose to replace conventional spiral tube structures with on-chip planar inductor structures to achieve the design requirements of small area, high inductance quality factor (Q), and low power consumption.
At present, more planar inductor structures are used, namely, a top metal is made into a structure of a spiral polygon (such as a quadrangle, a hexagon or an octagon) by utilizing a subsequent metal interconnection process, and a lower layer through hole and a metal connecting wire are used for making the spiral polygon planar inductor device.
In the process of drawing an integrated circuit layout, parameter extraction and verification of a layout ratio schematic LVS (Layout Versus Schematics) of an inductance device are required to be carried out by utilizing an Electronic Design Automation (EDA) tool so as to ensure the validity and the correctness of the layout design of the inductance device. The current layout parameter extraction method of the inductance device is that various special auxiliary layers are drawn, and then various parameters are extracted according to the various special auxiliary layers, so that the method cannot be compatible with various customers, increases design difficulty, increases complexity of corresponding Design Rule Checking (DRC), and reduces layout drawing efficiency.
Therefore, in the semiconductor integrated circuit technology, a layout parameter extraction method of a spiral polygonal inductor is needed to accurately extract the parameters of the inductor, improve the layout drawing efficiency of the inductor and reduce the error risk.
Disclosure of Invention
The invention aims to provide a layout parameter extraction method of a polygonal spiral inductance device, so as to accurately extract the parameters of the inductance device, improve the layout drawing efficiency of the inductance device and reduce the error risk.
The invention provides a layout parameter extraction method of a polygonal spiral inductance device, which comprises a first outgoing line, a second outgoing line and an outer ring protection ring, and is characterized by comprising the following steps: s1: drawing an auxiliary layer INDID, wherein the auxiliary layer INDID is rectangular, two opposite sides of the auxiliary layer INDID are respectively overlapped with the inner walls of the first outgoing line and the second outgoing line, and the other two opposite sides of the auxiliary layer INDID are respectively overlapped with the inner wall of the outer ring protection ring; s2: generating a derivative inner diameter rectangle ind_inner_r inside the spiral inductance coil of the inductance device by using the position relation between the auxiliary layer INDID and the first outgoing line, the second outgoing line and the inner wall of the outer ring protection ring through an electronic design automation tool EDA; s3: generating a technical file for calculating the inner diameter R and the number of turns N of the induction coil through an electronic design automation tool EDA; s4: and operating the technical file, and extracting parameters of the inductance device.
Further, in step S3, a technical file for calculating the inner diameter R of the inductor coil is generated by using the relationship between the derived inner diameter rectangle ind_inner_r and the auxiliary layer INDID.
Further, in step S3, a technical document for calculating the number of turns N of the inductor coil is generated by determining the number of included obtuse angles of the spiral inductor coil.
Further, comparing the edges of the derived inner diameter rectangle ind_inner_r and the auxiliary layer INDID, selecting a shorter edge, wherein the value R of the inner diameter R is 1/2 of the value of the shorter edge.
Further, the winding angle of the spiral inductance coil is judged to be the obtuse angle number which is larger than 180 degrees and smaller than 270 degrees, and the number of turns N is 1/4 of the obtuse angle number.
Still further, S5: and outputting an operation result, checking the LVS report file, and comparing and verifying.
Further, the number of sides of the polygonal spiral inductor is greater than or equal to 4.
Further, the number of sides of the polygonal spiral inductor is 8.
Still further, the inductor spiral inductor includes an integer number of turns, half turns, or 1/4 turns of the coil.
In one embodiment of the invention, an auxiliary layer is adopted to replace a special auxiliary layer designed according to different inductance devices in the prior art, and the auxiliary layer is utilized to realize the extraction of layout parameters of the polygonal spiral inductance devices through EDA tools.
Drawings
Fig. 1 is a schematic layout diagram of a three-port asymmetric octagonal spiral inductor according to an embodiment of the present invention.
Fig. 2 is a flow chart of a layout parameter extraction method of the three-port asymmetric octagonal spiral inductor device shown in fig. 1 according to an embodiment of the present invention.
Fig. 3 is an auxiliary layer INDID schematic diagram of the three-port asymmetric octagonal spiral inductor shown in fig. 1.
The main element reference numerals in the drawings are explained as follows:
110. a first lead-out wire; 120. a second lead-out wire; 130. an outer ring protection ring; 140. an auxiliary layer INDID; 150. the inner diameter rectangle ind_inner_r.
Detailed Description
The following description of the embodiments of the present invention will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In one embodiment of the present invention, the layout of a three-port asymmetric octagonal spiral inductor device is taken as an example to describe the present invention. Referring specifically to fig. 1, fig. 1 is a schematic layout diagram of a three-port asymmetric octagonal spiral inductor according to an embodiment of the present invention. As shown in fig. 1, the three-port asymmetric octagonal spiral inductor device includes a first lead-out wire 110 as a first port, a second lead-out wire 120 as a second port, and an outer ring guard ring 130 as a third port. Referring to fig. 2, fig. 2 is a flow chart illustrating a layout parameter extraction method of the three-port asymmetric octagonal spiral inductor device shown in fig. 1 according to an embodiment of the present invention. As shown in fig. 2, the layout parameter extraction method of the three-port asymmetric octagonal spiral inductor provided by the invention comprises the following steps:
s1: drawing an auxiliary layer INDID, wherein the auxiliary layer INDID is rectangular, two opposite sides of the auxiliary layer INDID are respectively overlapped with the inner walls of the first outgoing line and the second outgoing line, and the other two opposite sides of the auxiliary layer INDID are respectively overlapped with the inner walls of the outer ring protection rings.
Specifically, referring to fig. 3, fig. 3 is an auxiliary layer INDID schematic diagram of the three-port asymmetric octagonal spiral inductor shown in fig. 1. As shown in fig. 3, the auxiliary layer information 140 is rectangular, two long sides of the auxiliary layer information 140 are respectively overlapped with inner walls of the first outgoing line 110 and the second outgoing line 120, and as shown in fig. 3, the inner walls of the first outgoing line 110 and the second outgoing line 120 are respectively opposite side walls of the first outgoing line 110 and the second outgoing line 120; two short sides of the auxiliary layer INDID140 are respectively overlapped with the inner wall of the outer ring protection ring 130 of the inductance device.
S2: and generating a derivative inner diameter rectangle ind_inner_r inside the spiral inductance coil of the inductance device by using the position relation between the auxiliary layer INDID and the first outgoing line, the second outgoing line and the inner wall of the outer ring protection ring through an electronic design automation tool EDA.
Specifically, the specific steps and codes for generating the derivative inner diameter rectangle ind_inner_r150 inside the spiral inductance coil of the inductance device by using the position relation between the auxiliary layer ind and the first outgoing line, the second outgoing line and the inner wall of the outer ring protection ring of the inductance device through the electronic design automation tool EDA are as follows:
X＝INDID NOT TOUCH EDGE ptap
Y＝EXPAND EDGE X OUTSIDE BY 0.005
Z＝(Y NOT ind_mt)NOT INTERACT ptap
ind_inner_r＝Z NOT INSIDE ind_sp
wherein ptap is an outer ring guard ring 130 surrounding the outside of the inductor, i.e., the third port; ind_mt is a metal inductance coil inside the outer ring protection ring; ind_sp is a derivative rectangle with the maximum value of the internal distance of the inductance coil not exceeding the coil interval; ind_inner_r is the derived inner diameter rectangle inside the inductor coil created by the EDA tool.
X represents the auxiliary layer INDID rectangle with short sides removed, i.e. the sides coinciding with the inner walls of the outer ring protection ring, and only the remaining long sides, i.e. the sides coinciding with the inner walls of the first outgoing line and the second outgoing line. Y represents two derived rectangles generated by expanding each of the two long sides of the auxiliary layer INDID represented by X to the outside by 5nm, namely one lattice point. Z represents a pattern in which two derivative rectangles represented by Y are subtracted from the overlap of the inductor coil and are not in contact with the outer ring guard ring ptap. I.e. the Z-characterized pattern is a collection of internally derived inner diameter rectangles and a series of rectangles (ind sp) of width not exceeding the coil pitch that are sandwiched inside the inductor coil. ind_inner_r represents a series of rectangles (ind_sp) of width not exceeding the coil spacing that sandwich the Z-characterized set of rectangles inside the inductor, i.e., derived inside diameter rectangles inside the inductor.
S3: the technical document for calculating the inner diameter R and the number of turns N of the inductor winding is generated by means of an electronic design automation tool EDA.
In an embodiment of the present invention, a technical file for calculating the inner diameter R of the inductor coil is generated by using the relation between the derivative inner diameter rectangle ind_inner_r and the auxiliary layer INDID; and generating a technical file for calculating the number of turns N of the induction coil by judging the number of the included obtuse angles of the spiral induction coil.
Specifically, the LVS file is edited by using calibre svrf language, and the key codes are as follows:
1)ind_seed＝INDID INTERACT ind_mt
2)ind_corner＝ind_mt NOT INDID
3)ind_angle＝EXT(convex edge ind_corner angle1>180<270angle2>180<270)<0.5ABUT REGION
4)coin_seed_inner＝coin edge ind_seed ind_inner_r
5)coin_seed_inner_p＝dfm property coin_seed_inner[len＝length(coin_seed_inner)]
6)ind_seed_p＝DFM PROPERTY INDID coin_seed_inner_p OVERLAP ABUT ALSO MULTI[r＝min(property(coin_seed_inner_p,len))/2]
7)DEVICE single_end_ind ind_seed t4m2(top)t4m2(bottom)ptap(gnode)<ind_angle><ind_seed_p>[
PROPERTY R,N
R＝DFM_NUM_VAL(ind_seed_p,“r”)*1e-6
N＝COUNT(ind_angle)/4
]
8)TRACE PROPERTY single_end_ind R R
9)TRACE PROPERTY single_end_ind N N
wherein 1) a planar octagonal spiral inductor (single_end_ind) auxiliary layer INDID is defined.
2) -3) defining an obtuse angle (ind_angle) contained in the spiral inductor corner.
4) Two sides (paint_feed_inner) of the derived inner diameter rectangle ind_inner_r, which are generated by means of the EDA tool, are defined to coincide with the auxiliary layer INDID.
5) -6) defining a pair of said two overlapping edges (in_feed_inner), selecting the edge with the smaller edge length, and outputting the edge (ind_feed_p) with the edge length value satisfying r.
7) Defining an inductance device (single_end_ind) by using calibre svrf language, defining an input port (t 4m 2), an output port (t 4m 2) and a grounding port (ptap), and obtaining an extraction and calculation formula of a turn number N and an inner diameter R of the inductance device, wherein the extraction formula of the inner diameter R is that R=DFM_NUM_VAL (ind_seed_p, R') is 1/2 of a shorter side length value in two sides of the derivative inner diameter rectangle ind_inner_r overlapped with the auxiliary layer INDID, the ind_seed_p is a specific value of the inner diameter R, the side meeting R value, and DFM_NUM_VAL (_, "NUM") is a function of extracting and reading a graph conforming to the NUM value by using svrf language; the extraction and calculation formula of the number of turns N: n=count (ind_angle)/4, ind_angle is the obtuse angle contained in the corner of the spiral inductor, and COUNT (_l) is the function of the svrf language to extract and take the value of the graph.
Specifically, the calculation formula of r is r=min (property_seed_inner_p, len))/2, wherein the property_seed_inner_p is two sides of the derivative inner diameter rectangle ind_inner_r overlapped with the auxiliary layer INDID, property (property, len) is a value taking side length, and min (property) is a minimum function taking svrf language.
8) 9) using calibre svrf language to define Layout netlist information (Layout) and circuit netlist information (Schem-atic) to compare device parameters. Specifically, in an embodiment of the present invention, edges of the derived inner diameter rectangle ind_inner_r and the auxiliary layer INDID are compared, a shorter edge is selected, and the value R of the inner diameter R is 1/2 of the value of the shorter edge; judging the number of obtuse angles of the spiral inductance coil, wherein the winding angle of the spiral inductance coil is larger than 180 degrees and smaller than 270 degrees, and the number of turns N is 1/4 of the number of obtuse angles.
S4: and operating the technical file, and extracting parameters of the inductance device.
Further, S5: and outputting an operation result, checking the LVS report file, and comparing and verifying. According to the above steps of the present invention, the extraction netlist results are as follows:
.SUBCKT inductor
X0 1 2 3single_end_ind r＝60n＝1$X＝1536145$Y＝-694560$D＝148
X1 4 5 6single_end_ind r＝50n＝1.5$X＝1517080$Y＝-305865$D＝148
.ENDS
the netlist result shows that the actual inductance layout size is identical to that of the actual inductance layout, and the method can accurately extract the inductance device parameters.
In the above, the layout of the three-port asymmetric octagonal spiral inductor device is taken as an example to explain the layout parameter extraction method of the inductor device, but the invention is not limited to the octagonal spiral inductor device, and the octagonal spiral inductor device is only required to be a quadrilateral spiral inductor device which is more than or equal to the octagonal spiral inductor device, such as a quadrilateral spiral inductor or a hexagonal spiral inductor. In addition, the inductance device of the invention can be a symmetrical inductance device or an asymmetrical inductance device. Meanwhile, the number of ports of the spiral inductor is not limited.
The layout parameter extraction method of the polygonal spiral inductance device provided by the invention supports the extraction of the number of turns of the inductance device comprising integer-circle, half-circle or 1/4-circle coils.
Thus, in an embodiment of the invention, the layout parameter extraction method of the polygonal spiral inductor provided by the invention adopts an auxiliary layer to replace a special auxiliary layer designed according to different inductors in the prior art, and realizes the extraction of the layout parameters of the polygonal spiral inductor by using the auxiliary layer through EDA tool.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (7)
1. The layout parameter extraction method of the polygonal spiral inductance device comprises a first outgoing line, a second outgoing line and an outer ring protection ring, and is characterized by comprising the following steps:
s1: drawing an auxiliary layer INDID, wherein the auxiliary layer INDID is rectangular, two opposite sides of the auxiliary layer INDID are respectively overlapped with the inner walls of the first outgoing line and the second outgoing line, and the other two opposite sides of the auxiliary layer INDID are respectively overlapped with the inner wall of the outer ring protection ring;
s2: generating a derivative inner diameter rectangle ind_inner_r inside the spiral inductance coil of the inductance device by using the position relation between the auxiliary layer INDID and the first outgoing line, the second outgoing line and the inner wall of the outer ring protection ring through an electronic design automation tool EDA;
s3: generating a technical file for calculating the inner diameter R of the induction coil by using the relation between the derivative inner diameter rectangle ind_inner_r and the auxiliary layer INDID through an electronic design automation tool EDA, and generating a technical file for calculating the number of turns N of the induction coil by judging the number of obtuse angles contained in the corners of the spiral induction coil; and
s4: and operating the technical file, and extracting parameters of the inductance device.
2. The method for extracting layout parameters of a polygonal spiral inductor according to claim 1, wherein the side lengths of the derived inner diameter rectangle ind_inner_r and the auxiliary layer INDID are compared, the shorter side length is selected, and the value R of the inner diameter R is 1/2 of the shorter side length.
3. The layout parameter extraction method of a polygonal spiral inductor according to claim 1, wherein the number of obtuse angles contained in corners of the spiral inductor is judged, and the number of turns N is 1/4 of the number of obtuse angles.
4. The layout parameter extraction method of a polygonal spiral inductor according to claim 1, further comprising S5: and outputting an operation result, checking the LVS report file, and comparing and verifying.
5. The layout parameter extraction method of the polygonal spiral inductor according to claim 1, wherein the number of sides of the polygonal spiral inductor is greater than or equal to 4.
6. The layout parameter extraction method of a polygonal spiral inductor according to claim 5, wherein the number of sides of the polygonal spiral inductor is 8.
7. The method for extracting layout parameters of polygonal spiral inductor according to claim 1, wherein said inductor spiral inductor comprises an integer number of turns, half turns or 1/4 turn of turns.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102368276A (en) * | 2011-09-14 | 2012-03-07 | 天津蓝海微科技有限公司 | Flow method for automatically verifying correctness of electric rule file |
| CN102521469A (en) * | 2011-12-30 | 2012-06-27 | 上海集成电路研发中心有限公司 | Method for generating planar octagonal helical structure |
| CN108133101A (en) * | 2017-12-21 | 2018-06-08 | 上海华力微电子有限公司 | A kind of method that the auxiliary layer and device parameters of inductance domain extract |
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| US7243321B2 (en) * | 2004-04-07 | 2007-07-10 | Cadence Design Systems, Inc. | IC layout physical verification method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102368276A (en) * | 2011-09-14 | 2012-03-07 | 天津蓝海微科技有限公司 | Flow method for automatically verifying correctness of electric rule file |
| CN102521469A (en) * | 2011-12-30 | 2012-06-27 | 上海集成电路研发中心有限公司 | Method for generating planar octagonal helical structure |
| CN108133101A (en) * | 2017-12-21 | 2018-06-08 | 上海华力微电子有限公司 | A kind of method that the auxiliary layer and device parameters of inductance domain extract |
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