CN109300989A - A kind of indium selenide transistor and its manufacturing method - Google Patents
A kind of indium selenide transistor and its manufacturing method Download PDFInfo
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- CN109300989A CN109300989A CN201811087125.7A CN201811087125A CN109300989A CN 109300989 A CN109300989 A CN 109300989A CN 201811087125 A CN201811087125 A CN 201811087125A CN 109300989 A CN109300989 A CN 109300989A
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- AKUCEXGLFUSJCD-UHFFFAOYSA-N indium(3+);selenium(2-) Chemical compound [Se-2].[Se-2].[Se-2].[In+3].[In+3] AKUCEXGLFUSJCD-UHFFFAOYSA-N 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910000449 hafnium oxide Inorganic materials 0.000 claims abstract description 21
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims description 53
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 41
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 41
- 239000000758 substrate Substances 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 19
- 239000010408 film Substances 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 16
- 150000001875 compounds Chemical class 0.000 claims description 13
- 239000010936 titanium Substances 0.000 claims description 13
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 12
- 239000002390 adhesive tape Substances 0.000 claims description 12
- 229910052719 titanium Inorganic materials 0.000 claims description 12
- 239000010931 gold Substances 0.000 claims description 8
- 238000004528 spin coating Methods 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 238000000231 atomic layer deposition Methods 0.000 claims description 5
- 239000010409 thin film Substances 0.000 claims description 5
- 238000005566 electron beam evaporation Methods 0.000 claims description 4
- 238000009987 spinning Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000004070 electrodeposition Methods 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims description 2
- 229920000642 polymer Polymers 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 110
- 230000005669 field effect Effects 0.000 description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 238000012546 transfer Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 239000008186 active pharmaceutical agent Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 5
- 229910052738 indium Inorganic materials 0.000 description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000005527 interface trap Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000001000 micrograph Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000001179 sorption measurement Methods 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005264 electron capture Effects 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 238000012407 engineering method Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000399 optical microscopy Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- NMHFBDQVKIZULJ-UHFFFAOYSA-N selanylideneindium Chemical compound [In]=[Se] NMHFBDQVKIZULJ-UHFFFAOYSA-N 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 239000011669 selenium Substances 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
The invention discloses a kind of indium selenide transistor and its manufacturing methods, the hafnium oxide of high k and indium selenide are clipped in double-deck polymer P MMA in the transistor, so that the interface conditions of channel are greatly improved, so that high-field effect electron mobility and minimum lag may be implemented in indium selenide transistor, device performance is greatly improved.
Description
The present invention obtains special " the micro nano biochemical sensitive material of state key research and development plan " the advanced electronic material of strategy " emphasis
With device " support of project (2017YFB0405400).
Technical field
The present invention relates to a kind of transistor more particularly to two-dimensional material transistors.
Background technique
Indium selenide is typical two-dimensional layer semiconductor material, bandgap range 1.24-1.54eV, specific bandgap range
Depending on the number of plies.Indium selenide film has excellent electronics and photoelectric characteristic.Quality Research physical for indium selenide has been paid
Sizable effort is gone out.It has been reported it has been proved that the two-dimensional material device under being exposed to environmental condition is since interface causes
Additional scattering and significantly reduce carrier mobility.
High-k dielectric can effectively shield the coulomb impurity scattering (CI) of two-dimentional field effect transistor.Multilayer indium selenide
Transistor shows high field-effect mobility, Al2O3Dielectric can reduce Coulomb scattering.
The electrical stability of indium selenide field effect transistor plays a crucial role in practical applications, and electricity is steady
It is qualitative to be embodied in the hysteresis of transmission characteristic.The field-effect electron mobility for how improving indium selenide transistor, reduces it
Lag, improves the device performance of indium selenide transistor, is that industry personnel is badly in need of to push the application range of indium selenide transistor
It solves the problems, such as.
Summary of the invention
The invention discloses a kind of indium selenide transistor and its manufacturing method, by the hafnium oxide and selenium of high k in the transistor
Change indium to be clipped in double-deck polymer P MMA, so that the interface conditions of channel are greatly improved, so that indium selenide transistor
High-field effect electron mobility and minimum lag may be implemented, greatly improve device performance.
The manufacturing method of indium selenide transistor of the invention, includes the following steps:
Prepare semiconductor substrate；
Grid is formed on a semiconductor substrate；
Compound medium layer is deposited on grid；
Two-dimensional semiconductor layer is formed on compound medium layer；
Source/drain electrode is formed on the semiconductor layer；
Third dielectric layer is formed on semiconductor layer and source/drain electrode, forms indium selenide transistor；
Wherein, which includes first medium layer and second dielectric layer；
The first medium layer is hafnium oxide, which is PMMA；
The two-dimensional semiconductor layer is InSe；
The third dielectric layer is PMMA.
Wherein, the preferred silicon wafer of substrate；
Grid can be metal, preferably titanium/gold thin film；
Grid is preferably the gate portion directly formed on a semiconductor substrate by heavy doping；
The first medium layer with a thickness of 20-40nm；The second dielectric layer with a thickness of 200-300nm；The third medium
Layer with a thickness of 200-300nm；
Preferably, the first medium layer with a thickness of 25-35nm；The second dielectric layer with a thickness of 230-270nm；This
Three dielectric layers with a thickness of 230-270nm；
Preferably, the first medium layer with a thickness of 30nm, the second dielectric layer with a thickness of 250nm；The third medium
Layer with a thickness of 250nm.
The method for forming first medium layer is atomic layer deposition；
The method for forming second dielectric layer is spin coating, and is toasted after spinning；
The method for forming third dielectric layer is spin coating, and is toasted after spinning.
Preferably, the method for preparing InSe film is that block InSe material is placed on adhesive tape, sticks tear tape repeatedly,
Then adhesive tape is glutinous on a semiconductor substrate, it tears adhesive tape off, obtains being formed InSe film on a semiconductor substrate.
Preferably, it deposits to form source/drain electrode by electron beam evaporation；
Preferably, the material of source/drain electrode is titanium/billon.
Preferably, source/drain electrode position is defined with shadowmask on InSe film, then places it in electronics
In beam evaporation depositing system, vapor deposition titanium/gold material forms source/drain electrode.
Preferably, the spin coating PMMA on two-dimensional semiconductor layer, baking, is packaged, obtains InSe field effect transistor.
Indium selenide of the invention includes:
Semiconductor substrate；
It is provided with grid on a semiconductor substrate；
Compound medium layer is provided on grid；
There is two-dimensional semiconductor layer on compound medium layer；
On the semiconductor layer and its side has source/drain electrode；
There is third dielectric layer on semiconductor layer and source/drain electrode；
Wherein, which includes first medium layer and second dielectric layer；
The first medium layer is hafnium oxide, which is PMMA；
The two-dimensional semiconductor layer is InSe；
The third dielectric layer is PMMA.
Wherein, the preferred silicon wafer of substrate；
Grid can be metal, preferably titanium/gold thin film；
Grid is preferably the gate portion directly formed on a semiconductor substrate by heavy doping；
The first medium layer with a thickness of 20-40nm；The second dielectric layer with a thickness of 200-300nm；The third medium
Layer with a thickness of 200-300nm；
Preferably, the first medium layer with a thickness of 25-35nm；The second dielectric layer with a thickness of 230-270nm；This
Three dielectric layers with a thickness of 230-270nm；
Preferably, the first medium layer with a thickness of 30nm, the second dielectric layer with a thickness of 250nm；The third medium
Layer with a thickness of 250nm.
Preferably, the material of source/drain electrode is titanium/billon.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of indium selenide transistor of the invention.
Fig. 2 is the scanning electron microscope image of indium selenide transistor of the invention.
Fig. 3 is the structural schematic diagram of transistor in each step in the manufacturing method of indium selenide transistor of the invention.
Fig. 4 a is the indium selenide field effect transistor for using PMMA to encapsulate simultaneously based on hafnium oxide/PMMA bilayer dielectric layer
In VDSTransfer characteristic curve when=0.1V.Fig. 4 b is its corresponding output characteristic curve.Fig. 4 c is the indium selenide transistor
Mutual conductance and field-effect mobility.Fig. 4 d is the test thickness (afm image) of indium selenide film in the transistor.
Fig. 5 includes: that Fig. 5 a is SiO2- InSe-FET structure, Fig. 5 b are PMMA-InSe-PMMA SiO2FET structure, Fig. 5 c
For HfO2- InSe-FET structure and Fig. 5 d are PMMA-InSe-PMMA HfO2The lag of FET structure at room temperature.
Fig. 6 includes: that Fig. 6 a and Fig. 6 b are respectively to apply VGS=10V, VGSThe grid bias of=- 10V 5 minutes, 10 minutes and
PMMA-InSe-PMMA HfO after twenty minutes2Transfer characteristic curve of the transistor of structure in room temperature condition.Fig. 6 c is selenizing
The electron capture-of indium Adsorption on Surface molecule removes Trapping Mechanism schematic diagram.Fig. 6 d is indium selenide under minus gate voltage and positive grid voltage
Band curvature schematic diagram.
Specific embodiment
In order to make those skilled in the art are clearer to understand indium selenide field effect transistor and its manufacturer of the invention
Method and the principle of the technology of the present invention design, and the mechanism of beneficial effect is generated, it specifically describes with reference to the accompanying drawing.
As shown in Figure 1, indium selenide of the invention includes:
Semiconductor substrate 1；
It is provided with grid (not shown) on semiconductor substrate 1；
Compound medium layer is provided on grid；
There is two-dimensional semiconductor layer 4 on compound medium layer；
On semiconductor layer 4 and its side has source/drain electrode 5；
There is third dielectric layer 6 on semiconductor layer 4 and source/drain electrode 5；
Wherein, which includes first medium layer 2 and second dielectric layer 3；
The first medium layer 2 is hafnium oxide, which is PMMA；
The two-dimensional semiconductor layer 4 is InSe；
The third dielectric layer 6 is PMMA.
Wherein, the preferred silicon wafer of substrate；
Grid can be metal, preferably titanium/gold thin film；
Grid is preferably the gate portion directly formed on a semiconductor substrate by heavy doping；
The first medium layer with a thickness of 20-40nm；The second dielectric layer with a thickness of 200-300nm；The third medium
Layer with a thickness of 200-300nm；
Preferably, the first medium layer with a thickness of 25-35nm；The second dielectric layer with a thickness of 230-270nm；This
Three dielectric layers with a thickness of 230-270nm；
Preferably, the first medium layer with a thickness of 30nm, the second dielectric layer with a thickness of 250nm；The third medium
Layer with a thickness of 250nm.
Preferably, the material of source/drain electrode is titanium/billon.
Fig. 2 shows the scanning electron microscope images of indium selenide transistor of the invention.
As shown in figure 3, the manufacturing method of indium selenide transistor of the invention, includes the following steps:
Prepare semiconductor substrate 1；
Grid is formed on semiconductor substrate 1；
First medium layer 2 is deposited on grid；
Second dielectric layer 3 is formed on first medium layer 2；
Two-dimensional semiconductor layer 4 is formed in second dielectric layer 3；
Source/drain electrode 5 is formed on two-dimensional semiconductor layer 4；
Third dielectric layer 6 is formed in two-dimensional semiconductor layer 4 and source/drain electrode 5；
Wherein, which is hafnium oxide, which is PMMA；
The two-dimensional semiconductor layer is InSe；
The third dielectric layer is PMMA.
Specifically, the manufacturing method of InSe transistor of the invention includes the following steps:
Prepare semiconductor substrate 1, the preferred silicon wafer of substrate；
Grid is formed on silicon wafer；Grid can be metal, preferably titanium/gold thin film；Grid is preferably directly in semiconductor
The gate portion formed on substrate by heavy doping；
Compound medium layer is formed on grid, which includes first medium layer 2 and second dielectric layer 3；Specifically
, which is aluminum oxide or hafnium oxide, which is PMMA；Specifically, the first medium
Layer 2 with a thickness of 20-40nm；The second dielectric layer 3 with a thickness of 200-300nm；Preferably, the thickness of the first medium layer 2
For 25-35nm；The second dielectric layer 3 with a thickness of 230-270nm；
In a specific embodiment, the aluminum oxide or hafnium oxide first medium layer 2 with a thickness of 30nm, should
PMMA second dielectric layer 3 with a thickness of 250nm.
Specifically, the method for forming aluminum oxide or hafnium oxide is atomic layer deposition (ALD)；The method for forming PMMA
For spin coating, and toast after spinning.
In a specific embodiment, using the naked silicon wafer of BOE process p-type heavy doping, atomic layer deposition is used after processing
Product deposits 30nm aluminum oxide or hafnium oxide at 150 DEG C, after growth, using spin coating instrument under 4000 revs/min
It obtains 250nmPMMA within spin coating two minutes, is toasted 1 hour under 150 degrees Celsius.
After grid and compound medium layer is formed on the substrate, semiconductor layer 4 is prepared again on dielectric layer, semiconductor layer 4 is
InSe film.
Specifically, the method for preparing InSe film is, block InSe material is placed on adhesive tape, sticks tear tape repeatedly,
Then adhesive tape is sticked on substrate, tears adhesive tape off, obtain including substrate and its InSe film above.
In one embodiment, using the selenizing phosphide material of high-purity, a fritter block InSe is taken, is placed it in
On Scotch adhesive tape, then repeatedly stick tear tape, repeatedly after adhesive tape is sticked on substrate base, tear off adhesive tape formed
Multilayer InSe film on substrate.
After forming InSe semiconductor layer 4 on dielectric layer, source/drain electrode 5 is formed on semiconductor layer 4.
Specifically, can deposit to form source/drain electrode 5 by electron beam evaporation；The material of source/drain electrode 5 can be titanium/
Billon.
In a specific embodiment, multi-layer nano InSe film is positioned using optical microscopy, it is fixed with shadowmask
Adopted electrode position is placed in electron beam evaporation depositing system, and titanium (Ti)/gold (Au) electrode of 5/70nm is deposited.
It forms source/drain electrode 5 and then forms third dielectric layer in source/drain electrode 5, obtain InSe transistor.
Specifically, the method for forming third dielectric layer are as follows: the device rotary coating 250nmPMMA that will be made toasts 1 at 110 DEG C
Hour, it is packaged, obtains InSe field effect transistor.
As described in above content, the invention discloses one kind to improve selenizing by high-k dielectric and polymer interface engineering
The field-effect mobility of indium transistor and the new method of lag.After interface improves, the field-effect electron transfer of indium selenide transistor
Rate increases to 1100cm2/ Vs, lag are suppressed to 0.4V.
In order to compare the influence whether there is or not PMMA dielectric layer and dielectric material to transistor performance, we, which have manufactured, has heat
The indium selenide field effect transistor of the silicon dioxide dielectric layers of oxidation is as a comparison.For silica and hafnium oxide dielectric
Layer, and two kinds of transistor arrangements have been manufactured respectively: (1) without PMMA layer two sides in indium selenide, and (2) indium selenide two sides have
PMMA layers.
At room temperature using the I of Agilent B2901A parameter analyzer measurement InSe FETDS-VDSOutput characteristics
And IDS-VGSTransfer characteristic.For output characteristics, VDSIt is scanned from 0 to 10V, while VGSFrom -5 to 5V stepping, increment 2V.For
Transfer characteristic, VGSIn VDSTo be scanned when 0.1V from -10 to 12V.
Fig. 4 a is the indium selenide field effect transistor for using PMMA to encapsulate simultaneously based on hafnium oxide/PMMA bilayer dielectric layer
In VDSTransfer characteristic curve when=0.1V.Fig. 4 b is its corresponding output characteristic curve.Fig. 4 c is the indium selenide transistor
Mutual conductance and field-effect mobility.Fig. 4 d is the test thickness (afm image) of indium selenide film in the transistor.
As shown in figure 4, hafnium oxide/PMMA bilayer dielectric the layer and PMMA using high k encapsulate (PMMA-PMMA/
HfO2FET as shown in fig. 4 a, corresponding output characteristics is as schemed for the transfer characteristic curve of multilayer indium selenide field effect transistor)
Shown in 4b.The switching current ratio of transistor is 106, subthreshold swing S is 260mV/decade, off-state current 10pA.From figure
In the least square fitting of 4c, we are in VGSIt is about 1100cm that linear electron mobility is extracted in 5-10V range2/Vs.Threshold
Threshold voltage VTFor -3.8V.Fig. 4 d shows the test thickness (afm image) of indium selenide film.
Fig. 5 is (a) SiO2- InSe-FET structure, (b) PMMA-InSe-PMMA SiO2FET structure, (c) HfO2-InSe-
FET structure and (d) PMMA-InSe-PMMA HfO2The lag of FET structure at room temperature.The lag behavior of transfer characteristic has
There is identical scanning speed, arrow indicates the direction of grid bias scanning.
As shown in figure 5, the lag of the indium selenide transistor arrangement of above-mentioned four kinds of different structures at room temperature.Measure VGS
Scanning 16s from -10V to 10V, then returned and scanned with 16s.Bilayer dielectric layer and encapsulation indium selenide transistor show 0.4V
Minimum lag, as fig 5d.
Fig. 5 c shows the lag that indium selenide transistor of no PMMA interlayer based on hafnium oxide dielectric layer is about 0.6V,
When scanning needs 16s from -0.1V to 0.1V and returns to scanning with 16s, since the breakdown voltage of hafnium oxide dielectric layer is lower,
Therefore apply lesser grid voltage VGS.If replacing the hafnium oxide of high k with the silicon dioxide dielectric layers of thermal oxide, work as VGSFrom-
When 10V to 10V sweep time is 16s and returns to scanning with 16s, whether there is or not the indium selenide transistors of PMMA sandwich to show respectively
The lag of 1.4V and 4.4V, as shown in figure 5a and 5b.
Above-mentioned experimental data shows use hafnium oxide/PMMA bilayer dielectric layer and PMMA encapsulation (PMMA- of the invention
PMMA/HfO2FET the lag of multilayer indium selenide field effect transistor) is significantly better than other three kinds of structures.
In the field-effect mobility point that the transistor of the silicon dioxide dielectric layers whether there is or not PMMA interlayer based on thermal oxide extracts
It Wei not 89cm2/ Vs and 267cm2/Vs.We summarize the field-effect mobility of indium selenide transistor in table 1 with four kinds of structures,
Subthreshold swing, lag and threshold voltage.
Table 1
For n-type semiconductor, transistor generally has positive threshold voltage.PMMA-PMMA/HfO of the invention2Indium selenide
Transistor illustrates negative threshold voltage.As shown in table 1, PMMA-InSe-PMMA HfO2The transistor of structure illustrates -1.8V's
Threshold voltage, this demonstrate in the transistor indium selenide-dielectric layer interface have a certain amount of positive charge.In order to assess just
Charge, we test the indium selenide transistor in the case where applying grid voltage and being ± 10V 300s, 1000s and 2000s respectively
Transfer characteristic curve.
As shown in figure 6 a and 6b, even if grid voltage applies 2000s, transfer characteristic also be can be ignored, this shows boundary
At face is that positive charge is fixed charge mostly.The lag of indium selenide field effect transistor has electron capture and goes to capture various
Possible source.Including the absorption of the gas molecule on indium selenide surface, the charge at interface between indium selenide and dielectric layer
The defects of capture and indium selenide film.
Fig. 6 c, which is shown, removes Trapping Mechanism schematic diagram by the electron capture-of indium selenide Adsorption on Surface molecule.Biggish
Under negative-gate voltage (OFF state), indium selenide channel runs out of electronics, this helps to discharge the water and oxygen muon capture being adsorbed
Electronics.Which reduce carriers in channel to exhaust (i.e. so that channel more N-shaped), leads to threshold voltage VTNegative sense move
It is dynamic.On the contrary, under big positive grid voltage, the water and oxygen muon capture that electronics is adsorbed from indium selenide channel, this increase
The exhausting of carrier (even if its more p-type), causes the forward direction of threshold voltage mobile.These interface traps are originated from indium selenide-
Defect at dielectric interface.
As fig. 6 c, the electronics of trapping state is discharged into indium selenide channel (even if its more n by negative-gate voltage
Type), and positive grid voltage exhausts electronics (even if its more p-type) from indium selenide channel.Which results in the V observedT's
Variation.It is worth noting that, compared with OFF state (wherein channel capacitance almost can be ignored), in device operational process
Indium selenide channel wants weak more (due to its biggish channel capacitance) with movement under ON state.As shown in fig 6d, inclined with postivie grid
Pressure is compared, the threshold voltage V under negative gate biasTOffset amplitude is expected to bigger.
Another reason for lag is the defect of indium selenide film, channel upper surface using PMMA encapsulation can reduce water and
The absorption of oxygen molecule, and the hafnium oxide of high k and the following PMMA of indium selenide film together reduce interface trap, especially
Low energy defect, and reduce a coulomb impurity scattering.
As described above, the present invention provides a kind of new interface engineering method, it is high for being realized in practical electronic application
The field effect transistor of the two-dimensional material of performance, this method can improve the field-effect mobility of two-dimensional material field effect transistor
And lag.
Claims (10)
1. a kind of manufacturing method of indium selenide transistor, includes the following steps:
Prepare semiconductor substrate；
Grid is formed on a semiconductor substrate；
Compound medium layer is deposited on grid；
Two-dimensional semiconductor layer is formed on compound medium layer；
Source/drain electrode is formed on the semiconductor layer；
Third dielectric layer is formed on semiconductor layer and source/drain electrode, forms indium selenide transistor；
Wherein, which includes first medium layer and second dielectric layer；
The first medium layer is hafnium oxide, which is PMMA；
The two-dimensional semiconductor layer is InSe；
The third dielectric layer is PMMA.
2. manufacturing method as described in claim 1, which is characterized in that grid is titanium/gold thin film, or for directly in semiconductor
The gate portion formed on substrate by heavy doping.
3. manufacturing method as described in claim 1, which is characterized in that the first medium layer with a thickness of 20-40nm；This second
Dielectric layer with a thickness of 200-300nm；The third dielectric layer with a thickness of 200-300nm.
4. manufacturing method as described in claim 1, which is characterized in that the method for forming first medium layer is atomic layer deposition；
The method for forming second dielectric layer is spin coating, and is toasted after spinning；The method for forming third dielectric layer is spin coating, and is being revolved
It is toasted after applying.
5. manufacturing method as described in claim 1, which is characterized in that the method for forming InSe film includes, by block InSe
Material is placed on adhesive tape, sticks tear tape repeatedly, then that adhesive tape is glutinous on a semiconductor substrate, is torn adhesive tape off, is formed in
InSe film in semiconductor substrate.
6. manufacturing method as described in claim 1, which is characterized in that the method for forming source/drain electrode includes, in InSe film
On with shadowmask define source/drain electrode position, then place it in electron beam evaporation depositing system, vapor deposition titanium/
Golden material forms source/drain electrode.
7. a kind of indium selenide transistor characterized by comprising
Semiconductor substrate；
It is provided with grid on a semiconductor substrate；
Compound medium layer is provided on grid；
There is two-dimensional semiconductor layer on compound medium layer；
On the semiconductor layer and its side has source/drain electrode；
There is third dielectric layer on semiconductor layer and source/drain electrode；
The compound medium layer includes first medium layer and second dielectric layer；
The first medium layer is hafnium oxide, which is PMMA；
The two-dimensional semiconductor layer is InSe；
The third dielectric layer is PMMA.
8. transistor as claimed in claim 7, which is characterized in that the first medium layer with a thickness of 20-40nm.
9. transistor as claimed in claim 7, which is characterized in that the second dielectric layer with a thickness of 200-300nm.
10. transistor as claimed in claim 7, which is characterized in that the third dielectric layer with a thickness of 200-300nm.
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| CN110246891A (en) * | 2019-06-28 | 2019-09-17 | 北京大学 | A kind of synapse transistor, device and its manufacturing method, operation array |
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| CN103258850A (en) * | 2012-02-15 | 2013-08-21 | 西安电子科技大学 | Grapheme nano-ribbon field effect transistor and preparation method thereof |
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| CN110246891A (en) * | 2019-06-28 | 2019-09-17 | 北京大学 | A kind of synapse transistor, device and its manufacturing method, operation array |
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