CN109300974A - A kind of nonpolarity InAlN/GaN high electron mobility transistor and preparation method - Google Patents
A kind of nonpolarity InAlN/GaN high electron mobility transistor and preparation method Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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Abstract
The present invention relates to a kind of nonpolarity InAlN/GaN high electron mobility transistor and preparation method, preparation method includes: to grow into core layer material on substrate, forms nucleating layer；GaN is grown with first condition on nucleating layer, forms nonpolar buffer layer；GaN is grown with second condition on nonpolar buffer layer, forms nonpolar channel layer；InAlN is grown on nonpolar channel layer, forms nonpolar barrier layer；Source electrode and drain electrode is made in nonpolar channel layer and nonpolar barrier layer, grid is made on nonpolar barrier layer, obtains nonpolar InAlN/GaN high electron mobility transistor.The preparation method of the nonpolar InAlN/GaN high electron mobility transistor of the embodiment of the present invention forms nonpolar channel layer and nonpolar barrier layer, to form non-polar hetero structures, non-polar hetero structures can be modulated spontaneous polarization and piezoelectric polarization, to inhibit the generation of high density polarization charge in channel, enhanced effect is realized.
Description
Technical field
The invention belongs to microelectronics technologies, and in particular to a kind of nonpolarity InAlN/GaN high electron mobility crystal
Pipe and preparation method.
Background technique
Since the channel memory cell of GaN base heterojunction structure is in high mobility two-dimensional electron gas, GaN becomes preparation high-performance
The optimal material of electronic device.After K.Han et al. proposes the concept of GaN base heterojunction structure for the first time, with AlGaN/
GaN, InAlN/GaN, AlN/GaN etc. achieve in terms of preparing high electron mobility transistor plentiful and substantial for the heterojunction structure of representative
Research achievement.So far, the high electron mobility transistor (High based on conventional AlGaN/GaN heterojunction structure
Electron Mobility Transistor, abbreviation HEMT) cutoff frequency broken through 200GHz, maximum oscillation frequency
300GHz is broken through.
Transistor device based on the face conventional polar c group III-nitride heterojunction structure is depletion device, i.e., device is zero
Open state is presented when biasing, needs applying bias voltage to reach off state.This property can not only make device exist
Loss power under off working state, while making device there are security risks in terms of applied power electronics.In addition, in digital circuit
In system, the realization that depletion device is unable to complete a variety of logic functions is only relied on.Therefore, it prepares high performance enhanced (normal
Pass type) device becomes the focus and emphasis of current GaN base electronic device research.
Currently, realizing that the technology of enhancement device mainly includes p-GaN cap layer structure technology of preparing, recessed grid structure preparation skill
Art and fluorine ion injection technique etc..
For p-GaN cap layers technology of preparing: the working principle of p-GaN cap layers technology is similar with pn-junction, p-type GaN can and n
Type AlGaN potential barrier generates pn-junction electric field, generates depletion action to the two-dimensional electron gas at AlGaN/GaN heterojunction boundary.But
It is in p-GaN cap layer structure, the deposit of cap layers not only will increase the parasitic capacitance of device, while can weaken the grid-control energy of device
Power；Also, requirement of the growth of p-type GaN for doping techniques is very high, is at present still the GaN epitaxy critical technological point not yet captured,
Technical process is difficult to control accurately.
For recessed grid structure technology of preparing: recessed grid structure technology of preparing is performed etching to AlGaN potential barrier, when its thickness
When less than critical value, AlGaN/GaN heterojunction boundary will not generate two-dimensional electron gas, at this moment, the not no product of electronics below grid
Poly-, device is in normal status.But for recessed grid structure, it is shallower that excessively thin barrier layer will lead to channel potential well depth, causes
The confinement of carrier reduces；Moreover, dry etch process can cause to damage to material structure, and technology stability and repeatability
It is poor, it is unfavorable for being mass produced；In addition, the threshold voltage of recessed grid structure device is only capable of reaching the level slightly larger than 0V, it can not
Obtain higher threshold voltage.
For fluorine ion injection technique: the principle of fluorine ion injection technique is by plasma apparatus to gate region
AlGaN potential barrier carries out fluoro plasma processing, so that part fluorine ion is entered formation negative electricity center in AlGaN potential barrier, at it
The potential field that surrounding is formed generates depletion action to channel electrons to form enhancement device.However, since fluorine ion injects work
Skill will cause the increase of trap states and defect damage in barrier layer, influence device performance, especially will affect device in hot conditions
Under stability；
In addition, Conventional processing methods are although can achieve the purpose that exhaust channel carriers, heterostructure interface
The polarization charge at place still has；The prior art indicate that polarization charge will cause when carrying out the device technologies such as gate dielectric deposition
The negative sense of device threshold voltage drifts about, and there are hidden danger for reliability.
In conclusion existing technology there are the process repeatabilities poor, technical process for realizing enhancement device is to material and device
Part causes the problem of damage, process effects device stability, to influence the Performance And Reliability of enhancement device.
Summary of the invention
In order to solve the above-mentioned problems in the prior art, the present invention provides a kind of nonpolarity InAlN/GaN high electricity
Transport factor transistor and preparation method.The technical problem to be solved in the present invention is achieved through the following technical solutions:
The embodiment of the invention provides a kind of preparation method of nonpolarity InAlN/GaN high electron mobility transistor, packets
Include step:
S1, core layer material is grown on substrate, form nucleating layer；
S2, GaN grown with first condition on the nucleating layer, forms nonpolar buffer layer；
S3, GaN grown with second condition on the nonpolar buffer layer, forms nonpolar channel layer；
S4, InAlN is grown on the nonpolar channel layer, forms nonpolar barrier layer；
S5, source electrode and drain electrode is made in the nonpolar channel layer and the nonpolar barrier layer, in the nonpolarity
Grid is made on barrier layer, obtains nonpolar InAlN/GaN high electron mobility transistor.
In one embodiment of the invention, before step S1 further include:
Nitrogen treatment is carried out to the substrate, the temperature of the nitrogen treatment is 828~1012 DEG C.
In one embodiment of the invention, the first condition are as follows: base-plate temp range is 900~1100 DEG C, reaction
Chamber pressure range is 9~11Torr, and the source N first flow and the source Ga first flow ratio range are 9:1~11:1.
In one embodiment of the invention, the second condition are as follows: base-plate temp range is 900~1100 DEG C, reaction
Chamber pressure range is 9~11Torr, and the source N second flow and the source Ga second flow ratio range are 9:1~11:1, and the source Ga
The ratio of second flow and the source Ga first flow is 1:9~1:11, the source N second flow and the source Ga first flow
Ratio be 1:9~1:11.In one embodiment of the invention, step S4 includes:
S41, the growing AIN on the nonpolar channel layer, form insert layer；
S42, InAlN is grown in the insert layer, form the nonpolar barrier layer.
In one embodiment of the invention, the growth conditions of the nonpolar barrier layer are as follows: base-plate temp range is 650
~800 DEG C, reaction chamber pressure range is 180~220Torr, and the flow ratio range in the source N third flow and the source Al is 75~92,
The flow ratio range in the source the N third flow and the source In is 11~14.
In one embodiment of the invention, the material of the nonpolar barrier layer is In1-xAlxN, wherein x range be
80%~85%.
In one embodiment of the invention, step S5 includes:
S51, the first metal, annealing described first are deposited on the nonpolar barrier layer using evaporation of metal method
Metal makes first metal sink down into the nonpolar channel layer, forms source electrode and drain electrode；
S52, the etching nonpolar barrier layer, the nonpolar channel layer and the nonpolar buffer layer, form isolation
Groove；
S53, the second metal is deposited on the nonpolar barrier layer using evaporation of metal method, forms grid.
In one embodiment of the invention, it is gone back after production source electrode, drain and gate on the nonpolar barrier layer
Include:
S6, using plasma enhanced chemical vapor deposition method the nonpolar barrier layer, source electrode (106), drain electrode and
SiN is deposited on grid, forms protective layer；
S7, photoetching interconnects aperture area on the protective layer, makes metal interconnection layer in the interconnection aperture area.
The embodiment of the invention also provides a kind of nonpolarity InAlN/GaN high electron mobility transistor, by such as above-mentioned system
Preparation Method is made.
Compared with prior art, beneficial effects of the present invention:
1, the preparation method of nonpolar InAlN/GaN high electron mobility transistor of the invention is in certain process conditions
Under, nonpolar buffer layer, channel layer and barrier layer are formd, it is different that nonpolar channel layer and nonpolar barrier layer form nonpolarity
Matter structure, non-polar hetero structures can be modulated spontaneous polarization and piezoelectric polarization, to inhibit high density pole in channel
The generation for changing charge, realizes enhanced effect.
2, preparation method of the invention relies only on the growth control of in-situ materials, avoids the techniques such as etching, ion implanting
Damage to material devices, significantly improves process repeatability and stability, ensure that the performance of enhancement device and reliable
Property, it can be achieved that enhancement device prepare with scale.
Detailed description of the invention
Fig. 1 is a kind of nonpolarity InAlN/GaN high electron mobility transistor preparation method provided in an embodiment of the present invention
Flow chart；
Fig. 2 is that a kind of structure of nonpolarity InAlN/GaN high electron mobility transistor provided in an embodiment of the present invention is shown
It is intended to；
Fig. 3 is a kind of c-axis direction of nonpolarity InAlN/GaN high electron mobility transistor provided in an embodiment of the present invention
With grid direction schematic diagram；
Fig. 4 is that another nonpolarity InAlN/GaN high electron mobility transistor structure provided in an embodiment of the present invention shows
It is intended to；
Fig. 5 is that another nonpolarity InAlN/GaN high electron mobility transistor structure provided in an embodiment of the present invention shows
It is intended to.
Specific embodiment
Further detailed description is done to the present invention combined with specific embodiments below, but embodiments of the present invention are not limited to
This.
Embodiment one
Referring to Figure 1, Fig. 1 is a kind of nonpolarity InAlN/GaN high electron mobility crystal provided in an embodiment of the present invention
Tube preparation method flow chart, the preparation method include the following steps:
S1, core layer material is grown on substrate, form nucleating layer；
S2, GaN grown with first condition on the nucleating layer, forms nonpolar buffer layer；
S3, GaN grown with second condition on the nonpolar buffer layer, forms nonpolar channel layer；
S4, InAlN is grown on the nonpolar channel layer, forms nonpolar barrier layer；
S5, source electrode and drain electrode is made in the nonpolar channel layer and the nonpolar barrier layer, in the nonpolarity
Grid is made on barrier layer, obtains nonpolar InAlN/GaN high electron mobility transistor.
Specifically, before step S1 further include:
Nitrogen treatment is carried out to the substrate, the temperature of nitrogen treatment is 828~1012 DEG C；Preferably, treatment temperature is
920℃。
Specifically, the first condition are as follows: base-plate temp range be 900~1100 DEG C, reaction chamber pressure range be 9~
The ratio range of the source 11Tor, N first flow and the source Ga first flow is 9:1~11:1；Preferably, base-plate temp is 1000 DEG C,
Reaction chamber pressure range is 10Tor, and the source N first flow and the source Ga first flow ratio are 10；Further, the preferred source N first
Flow is 1000sccm, and the source Ga first flow is 100sccm.
Specifically, the second condition are as follows: base-plate temp range be 900~1100 DEG C, reaction chamber pressure range be 9~
The source 11Torr, N second flow and the source Ga second flow ratio range are 9:1~11:1, and the source Ga second flow and the source Ga first
The ratio of flow is 1:9~1:11, and the ratio of the source N second flow and the source N first flow is 1:9~1:11；Preferably, pedestal temperature
Degree is 1000 DEG C, and reaction chamber pressure range is 10Tor, and the source N second flow and the source Ga second flow ratio are 10, and the source Ga second
The ratio of flow and the source Ga first flow is the source 10, N second flow and the ratio of the source N first flow is 10；Further, preferably
The source N second flow is 100sccm, and preferably the source Ga second flow is 10sccm.
Specifically, step S4 includes:
S41, the growing AIN on the nonpolar channel layer, form insert layer；
S42, InAlN is grown in the insert layer, form nonpolar barrier layer.
Specifically, the growth conditions of the nonpolarity barrier layer are as follows: base-plate temp range is 648~792 DEG C, reacts chamber pressure
Strong range is 180~220Torr, and the flow ratio range in the source N third flow and the source Al is the source 75~92, N third flow and In
The flow ratio range in source is 11~14；
Preferably, pedestal growth temperature is 720 DEG C, and reaction chamber pressure is 200Torr, third flow and the source Al in the source N
Flow ratio is that the flow ratio in the source 83, N third flow and the source In is 12.5；
Preferably, the flow in the source Al is 12sccm, and the source N third flow is 1000sccm, and the flow in the source In is 80sccm.
Specifically, the material of the nonpolarity barrier layer is In1-xAlxN, wherein x range is 80%~85%；Preferably,
X is 82%.
Specifically, step S5 includes:
S51, the first metal, annealing described first are deposited on the nonpolar barrier layer using evaporation of metal method
Metal makes first metal sink down into the nonpolar channel layer, forms source electrode and drain electrode；
S52, the etching nonpolar barrier layer, the nonpolar channel layer and the nonpolar buffer layer, form isolation
Groove；
S53, the second metal is deposited on the nonpolar barrier layer using evaporation of metal method, forms grid.
Specifically, after making source electrode, drain and gate on the nonpolar barrier layer further include:
S6, using plasma enhanced chemical vapor deposition method on the nonpolar barrier layer, source electrode, drain and gate
SiN is deposited, protective layer is formed；
S7, photoetching interconnects aperture area on the protective layer, makes metal interconnection layer in the interconnection aperture area.
The preparation method of the nonpolar InAlN/GaN high electron mobility transistor of the embodiment of the present invention is capable of forming non-pole
Property buffer layer, channel layer and barrier layer, nonpolar channel layer and nonpolar barrier layer form non-polar hetero structures, nonpolarity
Heterojunction structure can be modulated spontaneous polarization and piezoelectric polarization, thus inhibit the generation of high density polarization charge in channel,
Realize the effect of enhancement device.
The preparation method of the embodiment of the present invention relies only on the growth control of in-situ materials, avoids etching, ion implanting etc.
Damage of the technique to material devices, significantly improves process repeatability and stability, ensure that enhancement device performance and
Reliability, it can be achieved that enhancement device prepare with scale.
Embodiment two
Refer to Fig. 2, a kind of Fig. 2 nonpolarity InAlN/GaN high electron mobility transistor provided in an embodiment of the present invention
Structural schematic diagram, on the basis of the embodiment of the present invention one, with the m surface sapphire that insulate makees substrate 101, grid is oriented parallel to
It is described in detail for the nearly Lattice Matching InAlN/GaN high mobility transistor of c-axis direction production nonpolarity, specific steps are such as
Under:
S1, high-temperature ammonolysis processing is carried out to insulating sapphire substrate 101.
Pure insulating sapphire is placed on above graphite base, guarantees that substrate normally floats, then puts graphite base
Enter in reaction chamber, guarantees that pedestal being capable of normal rotation and revolution；It opens reaction chamber vacuum pump and vacuumize process is carried out to reaction chamber,
So that reaction chamber vacuum degree is lower than 1 × 10-2Torr；High-purity ammonia and hydrogen gas mixture are passed through in reaction chamber, simultaneous reactions
Room vacuum pump works on, and guarantees that react indoor high-purity ammon air pressure is 40Torr by force；Graphite base is carried out by radio frequency source
Heating, makes graphite base temperature be increased to 920 DEG C in 7min, keeps temperature 5min.
It is unfavorable that sapphire substrate surface attachment dangling bonds etc. can not only be eliminated to the high-temperature ammonolysis process of Sapphire Substrate
Factor, while the Al atom of sapphire substrate surface can be carried out to nitridation and form AlN pre-reaction layer, it is provided for subsequent reactions good
Good substrate.
S2, grow into core layer material on substrate 101, form nucleating layer 102, wherein nucleating layer 102 include low temperature AI N at
Stratum nucleare 1021 and high-temperature AlN nucleating layer 1022.Comprising steps of
S21, the growing AIN on substrate 101 form low temperature AI N nucleating layer 1021；
Control graphite base temperature (temperature of graphite base, that is, every layer material growth temperature), make its gradually reduce to
, the source Al trimethyl aluminium is brought by carrier gas of hydrogen, while being passed through ammonia as the source N, and be maintained at reaction intraventricular pressure by force by 620 DEG C
The dynamic equilibrium of 40Torr；Wherein, hydrogen flowing quantity 800sccm, ammonia flow 1500sccm, trimethyl aluminium flow are
6sccm；It grows 5 minutes with this condition, the low temperature AI N nucleating layer 1021 being correspondingly formed is with a thickness of 30nm.
The stress between Sapphire Substrate and epitaxial material can be effectively relieved in low temperature AI N nucleating layer 1021.
S22, the growing AIN on low temperature AI N nucleating layer 1021 form high-temperature AlN nucleating layer 1022；
Graphite base temperature is controlled, it is gradually risen to 1070 DEG C, brings the source Al trimethyl aluminium by carrier gas of hydrogen, together
When be passed through ammonia as the source N, and make to react intraventricular pressure and be maintained at the dynamic equilibrium of 40Torr by force；Wherein, hydrogen flowing quantity is
800sccm, ammonia flow 3000sccm, trimethyl aluminium flow are 12sccm；With this condition, ammonia and trimethyl aluminium is anti-
Answering growth time is 20 minutes, and the high-temperature AlN growth thickness being correspondingly formed is 200nm.
High-temperature AlN nucleating layer is able to ascend the cross growth rate of AlN, is ready for subsequent two-dimensional growth.
Nucleating layer 102, the total thickness of nucleating layer 102 is collectively formed in low temperature AI N nucleating layer 1021 and high-temperature AlN nucleating layer 1022
Degree is 230nm.
S3, GaN is grown on nucleating layer 102, form nonpolar buffer layer 103；
Graphite base temperature is controlled, it is made to be gradually decrease to 1000 DEG C, is passed through the source reaction source Ga and N simultaneously toward reaction chamber
Source, makes the flow ratio 10 in the source N Yu the source Ga, and makes to react the dynamic equilibrium that intraventricular pressure is maintained at by force 10Torr；Wherein, the source Ga
For trimethyl gallium, flow 100sccm；The source Ga is that carrier gas is carried along into reaction chamber by hydrogen, and carrier gas hydrogen flowing quantity is
800sccm；The source N is ammonia, flow 1000sccm；With this condition, it is 60 that trimethyl gallium, which reacts growth time with ammonia,
Minute, the nonpolar buffer layer 103 being correspondingly formed is with a thickness of 1500nm.
Further, form the necessary condition of non-polar conformations are as follows: higher growth temperature, lower reaction chamber pressure with
And the flow-rate ratio of lower V race reaction source and III group reaction source；The growth temperature of nonpolar buffer layer 103 in this embodiment
It is 1000 DEG C, reaction chamber pressure is 10Torr, and the source N and Ga source flux ratio are 10, and three meets the growth item of non-polar conformations
Part, the buffer layer formed with this condition are nonpolar.
S4, GaN is grown on nonpolar buffer layer, form nonpolar channel layer 104；
Maintaining graphite base temperature is 1000 DEG C, reaction chamber pressure is 10Torr, and carrier gas hydrogen flowing quantity is reduced to
80sccm, N source, that is, ammonia flow are reduced to 100sccm, and the source Ga, that is, TMGa flow rate is reduced to 10sccm；With this condition,
It is 40 minutes that trimethyl gallium, which reacts growth time with ammonia, and the nonpolar channel layer 104 being correspondingly formed is with a thickness of 200nm.
Further, the N source flux of growing nonpolar channel layer 104, Ga source flux are growing nonpolar buffer layer 103
N source flux, Ga source flux 1/10th, therefore, the growth rate of nonpolar channel layer 104 is also nonpolar buffer layer
/ 10th of 103 growth rates, it can be ensured that the material crystalline quality of nonpolar channel layer is higher, so that it is guaranteed that nonpolar ditch
The drift speed of electronics in channel layer.
Further, the growth temperature of growing nonpolar channel layer 104 is 1000 DEG C, and reaction chamber pressure is 10Torr, the source N
It is 10 with Ga source flux ratio, meets the growth conditions of non-polar conformations, the channel layer formed with this condition is nonpolar.
S5, InAlN is grown on nonpolar channel layer 104, form nonpolar barrier layer 105.Comprising steps of
S51, the growing AIN on nonpolar channel layer 104 form insert layer 1041；
Maintaining graphite base temperature is 1000 DEG C, reaction chamber pressure is 10Torr, is passed through the source N and the source Al toward reaction chamber；Its
In, the source Al is trimethyl aluminium, flow 5sccm；The source Al is that carrier gas is carried along into reaction chamber by hydrogen, carrier gas hydrogen flowing quantity
For 200sccm；The source N is ammonia, flow 100sccm；With this condition, trimethyl aluminium reacts growth time with ammonia and is
0.5 minute, the insert layer 1041 being correspondingly formed was with a thickness of 2nm.
S52, InAlN is grown in insert layer 1041, form nonpolar barrier layer 105；
Graphite base temperature is gradually decrease to 720 DEG C, the source reaction source Al, the source In and the source N is passed through simultaneously toward reaction chamber, makes
The flow ratio in the source N and the source Al is the source 10, N and the flow ratio in the source In is 12.5, and is maintained at reaction intraventricular pressure by force
The dynamic equilibrium of 200Torr；Wherein, the source Al is trimethyl aluminium, flow 12sccm；The source Al is carried along by hydrogen for carrier gas
In reaction chamber, carrier gas hydrogen flowing quantity is 800sccm；The source N is ammonia, flow 1000sccm；The source In is trimethyl indium, stream
Amount is 80sccm；The source In is that carrier gas is brought into reaction chamber by nitrogen；With this condition, growth time is 5 minutes, is correspondingly formed
Nonpolar barrier layer 105 is with a thickness of 12nm, and Al component is 82% in nonpolar barrier layer 103.
Further, growth temperature is 720 DEG C in the present embodiment, and reaction chamber pressure is 200Torr, the source N and Al source flux
Than being 12.5 for the source 83, N and In source flux ratio, meet the growth conditions of non-polar conformations, the barrier layer formed with this condition
It is nonpolar.
Further, the flow in the source In is higher than the flow in the source Al, this is because the combination energy between phosphide atom and nitrogen-atoms
It is lower, therefore should be kept when growing nonpolar InAlN in reaction chamber as rich indium environment.
Further, Al component is the 82% smectic lattice that barrier layer and channel layer may be implemented in nonpolar barrier layer 103
Matching, under the conditions of the component, heterojunction structure maintains on the basis of guaranteeing that intrinsic two-dimensional electron gas is lower in channel
Biggish band offsets between barrier layer and channel layer ensure that and still form deep potential well at channel, improve current-carrying in channel
The confinement of son.
Further, one layer of ultra-thin insert layer is grown between nonpolar channel layer 102 and nonpolar barrier layer 103
1021, it is to inhibit two dimension because insert layer can form effective barrier between nonpolar barrier layer and nonpolar channel layer
The wave function of electron gas diffuses into nonpolar barrier layer, so that the alloy disorder in ternary barrier material be inhibited to scatter to two dimension
The adverse effect that electron gas transports；Moreover, barrier layer is different from the growth conditions of channel layer, condition conversion process will cause reaction
The influences such as indoor air flow is uneven, temperature is unstable, insert layer can play the transitional function of growth conditions conversion, effectively eliminate life
Elongate member is mutated the adverse effect to heterojunction characteristics；In addition, insert layer can largely play smooth interface pattern, suppression
The effect of interface roughness scattering processed, improves the performance of device.
Further, insert layer selects AlN, is to utilize big excellent of AlN forbidden bandwidth since the forbidden bandwidth of AlN is larger
Potential energy is enough to realize modulating action to heterostructure band structure, and the band rank height being obviously improved between barrier layer and channel layer increases
Big potential well depth, to improve the confinement of two-dimensional electron gas in channel.
S6, source electrode 106 and drain electrode 107 are made in the nonpolar channel layer 104 and the nonpolar barrier layer 105,
Grid 108 is made on the nonpolar barrier layer 105, the specific steps are as follows:
S61, the first metal is deposited on the nonpolar barrier layer 105 using evaporation of metal method, described in annealing
First metal makes the first metal sink down into the nonpolar channel layer 104, forms source electrode 106 and drain electrode 107；
Firstly, photoetching source electrode region and drain regions on nonpolar barrier layer 105；Then, in source electrode region
Is deposited on overseas photoresist on the nonpolar barrier layer 105 in drain regions and source electrode region and drain regions
One metal, wherein first metal is ohmic metal, and the metal stack structure being made of four layers of metal, four layers of metal are under
It is followed successively by Ti, Al, Ni and Au upwards, thickness is respectivelyThen, source electrode region and leakage are removed
The ohmic metal on photoresist outside electrode zone；Finally, the sample for completing ohmic metal evaporation and removing is put into fast speed heat
It is made annealing treatment in annealing furnace, so that the ohmic metal in source electrode region and drain regions on nonpolar barrier layer 105
Nonpolar channel layer 104 is sunk down into, to form the Ohmic contact between ohmic metal and hetero-junctions channel, forms source electrode 106
With drain electrode 107.Wherein, the process conditions made annealing treatment in rapid thermal anneler are as follows: annealing atmosphere N2, annealing temperature is
850 DEG C, annealing time 30s.
Further, the c-axis side on source electrode 106 and the central point connecting line and nonpolar barrier layer 105 on 107 surfaces that drain
To parallel, c-axis direction is the horizontal direction along nonpolar barrier layer 105, refers to Fig. 3, and Fig. 3 is provided in an embodiment of the present invention
A kind of c-axis direction of nonpolarity InAlN/GaN high electron mobility transistor and grid direction schematic diagram, wherein source electrode 106
The line of central point A and the central point B of drain electrode 107 are parallel with c-axis direction, and grid 108 is located on the line of A and B, therefore grid
108 is parallel with c-axis.
S62, the etching nonpolar barrier layer 105, the nonpolar channel layer 104 and the nonpolar buffer layer 103,
Form isolated groove 1071；
Using gluing, drying glue, exposure, development, stripping technology on nonpolar barrier layer 105 photoetching electrically isolated area, it
Ultrapure water is carried out to sample afterwards and is dried with nitrogen, and sample is placed on 110 DEG C of hot plate and toasts 2min；Then, it utilizes
Inductively coupled plasma (inductively coupled plasma, abbreviation ICP) technique is sequentially etched electrically isolated area
Nonpolar barrier layer 105, insert layer 1041 and nonpolar channel layer 104, to realize the mesa-isolated of active area, total etching
Depth is 500nm；Finally, sample is sequentially placed into acetone soln, is cleaned in ethanol solution, it is overseas to remove electricity isolated region
Photoresist, then with ultrapure water sample and with being dried with nitrogen, form isolated groove 1071.
It should be noted that having insert layer 1041 when growing between nonpolar barrier layer 105 and nonpolar channel layer 104
When, nonpolar barrier layer 105, insert layer 1041 and nonpolar channel layer 104 are etched, to form isolated groove 1071；When non-
When between polarity barrier layer 105 and nonpolar channel layer 104 without insert layer 1041, nonpolar barrier layer 105 and nonpolarity are etched
Channel layer 104, to form isolated groove 1071.
S63, the second metal is deposited on the nonpolar barrier layer 105 using evaporation of metal method, forms grid 108；
Photoetching gate electrode area domain, control on nonpolar barrier layer 105 using gluing, drying glue, exposure, development, stripping technology
Grizzly bar direction (gate electrode region is generally rectangle, and the direction where long side in rectangle is grizzly bar direction) processed and extension
Piece surface c-axis direction is parallel, and carries out ultrapure water to sample and be dried with nitrogen；Then, the non-pole in gate electrode region
The second metal is evaporated as grid on property barrier layer 105 and on photoresist that gate electrode area is overseas, wherein second metal is
Schottky metal, the metal stack structure being made of double layer of metal, metal stack structure are followed successively by Ni and Au, Ni from bottom to top
It is respectively with Au thicknessIt is ultrasonically treated finally, the sample for completing gate metal evaporation is put into acetone,
Ultrasonic time is set as 10min, and to remove the schottky metal and photoresist outside gate electrode, sample is put into nmp solution later
Middle ultrasound removal removing glue, then with isopropanol, ultrapure water sample and with being dried with nitrogen, form grid 108.
Further, grid direction is determined by the relative bearing of source electrode and drain electrode, therefore, when making source electrode and drain electrode,
It drains parallel with c-axis direction with source electrode line, drains between source electrode since grid is located at, then the direction Yu c-axis side of grid
To parallel, Fig. 3 is referred to.
S7, plasma enhanced chemical vapor deposition method (plasma enhanced chemical vapor is utilized
Deposition, abbreviation PECVD) on the nonpolar barrier layer 105, source electrode 106, drain electrode 107 and grid 108 SiN is deposited,
Form protective layer 109；Specific step is as follows:
To complete grid 106 make sample carry out surface clean, and using pecvd process nonpolar barrier layer 105,
The SiN that growth thickness is 200nm on source electrode 106, drain electrode 107 and grid 108 forms protective layer 109, the process conditions of growth
Are as follows: use NH3And SiH4As reaction gas, underlayer temperature is 300 DEG C, and reaction chamber pressure 600mTorr, RF power is
30W。
S8, photoetching interconnects aperture area on the protective layer 109, makes metal interconnection layer 110 in the interconnection aperture area；
Specific step is as follows:
Source electrode 106,107 and of drain electrode are made on protective layer 109 of techniques such as gluing, drying glue, exposure, development, removings
The metal interconnection aperture area of grid 108, and ultrapure water is carried out to sample and is dried with nitrogen；Then, in metal interconnection aperture
Area's etch-protecting layer 109 forms metal interconnection open-celled structure；Then, in metal interconnection open-celled structure and metal interconnection aperture
Using electron beam evaporation process deposit interconnection metal on protective layer 109 outside structure, which is made of double layer of metal
Metal stack structure, be followed successively by Ti and Au from bottom to top；Finally, by complete interconnection evaporation of metal sample be put into acetone into
Row ultrasonic treatment, ultrasonic time is set as 10min, to remove interconnection metal and the photoresist outside interconnection region, later by sample
It is put into N-Methyl pyrrolidone (N-methyl-2-pyrrolidone is commonly called as NMP) solution ultrasound removal removing glue, then with different
Propyl alcohol, ultrapure water sample and with being dried with nitrogen, form metal interconnection layer 110, and metal interconnection layer 110 is by source electrode 106, drain electrode
107 and grid 108 draw；Finally obtain the grid direction nonpolar InAlN/GaN high electron mobility crystal parallel with c-axis
Pipe, refers to Fig. 2, and substrate is that sapphire nonpolarity InAlN/GaN high electron mobility transistor includes: Sapphire Substrate
101；Low temperature AI N nucleating layer 1021 is located on substrate 101；High-temperature AlN nucleating layer 1022 is located at low temperature AI N nucleating layer 1021
On；Nonpolar buffer layer 103 is located on high-temperature AlN nucleating layer 1022；Nonpolar channel layer 104 is located at nonpolar buffer layer
On 103；Insert layer 1041 is located on nonpolar channel layer 104；Nonpolar barrier layer 105 is located in insert layer 1041；Source electrode
106, it is located on nonpolar channel layer 104；Drain electrode 107 is located on nonpolar channel layer 104；Grid 108 is located at nonpolar gesture
In barrier layer 105, and grid 108 is oriented parallel to c-axis；Protective layer 109 is covered on nonpolar barrier layer 105, source electrode 106, leakage
On pole 107 and grid 108；Metal interconnection layer 110 is located on source electrode 106, drain electrode 107 and grid 108.
The preparation method of the embodiment of the present invention relies only on the growth control of in-situ materials, avoids etching, ion implanting etc.
Damage of the technique to material devices, significantly improves process repeatability and stability, ensure that enhancement device performance and
Reliability, it can be achieved that enhancement device prepare with scale.
In the nonpolar InAlN/GaN high electron mobility transistor of the embodiment of the present invention, carrier is transported along c-axis direction
Rate is higher than the characteristic of all directions in the face c, and therefore, the relative bearing of control source electrode and drain electrode makes to control the direction of grid
Carrier effectively transports and is oriented parallel to c-axis, to improve device performance.
Embodiment three
On the basis of embodiment one and embodiment two, the present embodiment makes nonpolar smectic on semi-insulation SiC substrate
Lattice match InAlN/GaN high mobility transistor, refer to Fig. 4, and Fig. 4 is another nonpolarity provided in an embodiment of the present invention
InAlN/GaN high electron mobility transistor structure schematic diagram.
Specific step is as follows:
S1, double of insulating SiC substrate 201 carry out high-temperature ammonolysis processing.
Pure semi-insulation SiC substrate 201 is placed on above graphite base, guarantees that substrate normally floats, then by graphite
Pedestal is put into reaction chamber, guarantees that pedestal being capable of normal rotation and revolution；It opens reaction chamber vacuum pump and reaction chamber take out very
Vacancy reason, so that reaction chamber vacuum degree is lower than 1 × 10-2Torr；High-purity ammonia and hydrogen gas mixture are passed through in reaction chamber, together
When reaction chamber vacuum pump work on, guarantee that react indoor high-purity ammon air pressure is 40Torr by force；By radio frequency source to graphite-based
Seat is heated, and so that graphite base temperature is increased to 920 DEG C in 7min, is kept temperature 5min.
The influence of the unfavorable factors such as SiC substrate surface attachment dangling bonds can be eliminated to the high-temperature ammonolysis process of SiC substrate,
Good substrate is provided for subsequent reactions.
S2, the growing AIN on substrate 201 form nucleating layer 202；Comprising steps of
Graphite base temperature is controlled, it is gradually risen to 1070 DEG C, brings the source Al trimethyl aluminium by carrier gas of hydrogen, together
When be passed through ammonia as the source N, and make to react intraventricular pressure and be maintained at the dynamic equilibrium of 40Torr by force；Wherein, hydrogen flowing quantity is
800sccm, ammonia flow 3000sccm, trimethyl aluminium flow are 12sccm；With this condition, ammonia and trimethyl aluminium is anti-
Answering growth time is 20 minutes, and the high-temperature AlN growth thickness being correspondingly formed is 200nm.
It should be noted that since SiC substrate and epitaxial structure lattice mismatch are smaller, to SiC substrate high temperature nitrogen
Epitaxial material cross can be improved in directly growth high-temperature AlN nucleating layer 202, the high-temperature AlN nucleating layer 202 of formation after the completion of changing processing
To growth rate, it is ready for subsequent two-dimensional growth.
Step S3~S8 refers to embodiment two, finally obtains the nonpolar InAlN/GaN high electron mobility that substrate is SiC
Rate transistor, refers to Fig. 4.
Substrate is that the nonpolar InAlN/GaN high electron mobility transistor of SiC includes: SiC substrate 201；High-temperature AlN at
Stratum nucleare 202 is located in SiC substrate 301；Nonpolar buffer layer 203 is located on high-temperature AlN nucleating layer 202；Nonpolar channel layer
204, it is located on nonpolar buffer layer 203；Insert layer 2041 is located on nonpolar channel layer 204；Nonpolar barrier layer 205, position
In in insert layer 2041；Source electrode 206 is located on nonpolar channel layer 204；Drain electrode 207 is located on nonpolar channel layer 204；Grid
Pole 208 is located on nonpolar barrier layer 205, and grid 208 is oriented parallel to c-axis；Protective layer 209 is covered on nonpolar gesture
On barrier layer 205, source electrode 206, drain electrode 207 and grid 208；Metal interconnection layer 210 is located at source electrode 206, drain electrode 207 and grid 208
On.
Example IV
On the basis of embodiment one and embodiment two, the present embodiment makes nonpolar smectic lattice on semi-insulating Si substrate
InAlN/GaN high mobility transistor is matched, Fig. 5 is referred to, Fig. 5 is another nonpolarity provided in an embodiment of the present invention
InAlN/GaN high electron mobility transistor structure schematic diagram.
Specific step is as follows:
S1, high-temperature ammonolysis processing is carried out to semi-insulating Si substrate 301.
Since Si substrate can react generation SiN with ammonia under hot conditions, subsequent epitaxial is had adverse effect on, therefore
Before high-temperature ammonolysis processing, needs to be passed through trimethyl silicon source in reaction chamber first, so that aluminium atom is deposited on substrate surface, play
Protect the effect of substrate.Then, high-purity ammonia and hydrogen gas mixture are passed through in reaction chamber, simultaneous reactions room vacuum pump continues
Work guarantees that high-purity ammonia atmosphere of 40Torr in reaction chamber encloses；Finally, heating by radio frequency source to graphite base, make stone
Black base-plate temp is increased to 920 DEG C in 7 minutes, and keeps the temperature 5 minutes.
It can not only play the role of protecting substrate to the high-temperature ammonolysis process of semi-insulating Si substrate, but also Si can be eliminated
Substrate surface adheres to the unfavorable factors such as dangling bonds, provides good substrate for subsequent reactions.
S2, grow into core layer material on substrate 301, form nucleating layer 302, wherein nucleating layer 302 include low temperature AI N at
Stratum nucleare 3021, high-temperature AlN nucleating layer 3022 and gradual change AlGaN nucleating layer 3023.Comprising steps of
S21, the growing AIN on substrate 301 form low temperature AI N nucleating layer 3021.
The temperature for controlling graphite base, gradually reduces it to 620 DEG C, brings the source Al trimethyl aluminium by carrier gas of hydrogen,
Ammonia is passed through as the source N simultaneously, and makes to react the dynamic equilibrium that intraventricular pressure is maintained at by force 40Torr；Wherein, hydrogen flowing quantity is
800sccm, ammonia flow 1500sccm, trimethyl aluminium flow are 6sccm；It grows 5 minutes, is correspondingly formed with this condition
Low temperature AI N nucleating layer 3021 is with a thickness of 30nm.
The stress between Sapphire Substrate and epitaxial material can be effectively relieved in low temperature AI N nucleating layer 3021.
S22, the growing AIN on low temperature AI N nucleating layer 3021 form high-temperature AlN nucleating layer 3022.
Graphite base temperature is controlled, it is gradually risen to 1070 DEG C, brings the source Al trimethyl aluminium by carrier gas of hydrogen, together
When be passed through ammonia as the source N, and make to react intraventricular pressure and be maintained at the dynamic equilibrium of 40Torr by force；Wherein, hydrogen flowing quantity is
800sccm, ammonia flow 3000sccm, trimethyl aluminium flow are 12sccm；With this condition, ammonia and trimethyl aluminium is anti-
Answering growth time is 20 minutes, and the high-temperature AlN growth thickness being correspondingly formed is 200nm.
High-temperature AlN nucleating layer is able to ascend the cross growth rate of AlN, is ready for subsequent two-dimensional growth.
S23, AlGaN is grown on high-temperature AlN nucleating layer 3022, form high temperature AlGaN nucleating layer 3023.
Graphite base temperature is controlled, so that it is gradually decrease to 1000 DEG C, brings the source Ga and the source Al by carrier gas of hydrogen, simultaneously
It is passed through the source N, and makes to react the dynamic equilibrium that intraventricular pressure is maintained at by force 40Torr；Wherein, the source Ga be trimethyl gallium, flow from
0sccm is stepped up to 100sccm；The source Al is trimethyl aluminium, and flow is gradually reduced from 12sccm to 0sccm；The source N is ammonia
Gas, flow 3000sccm；The flow of carrier gas hydrogen is 800sccm；Growth time is 40min with this condition, corresponding shape
At high temperature AlGaN nucleating layer 3023 with a thickness of 600nm, wherein Al group is divided into gradual change from high to low.
Nucleating layer is collectively formed in low temperature AI N nucleating layer 3021, high-temperature AlN nucleating layer 3022 and gradual change AlGaN nucleating layer
302, the overall thickness of nucleating layer 302 is 830nm.
Successively growing low temperature AlN nucleating layer, high-temperature AlN nucleating layer and gradual change AlGaN nucleating layer on a si substrate, be due to
Lattice mismatch between Si substrate and epitaxial material is very big, and the AlGaN nucleating layer for growing the gradual change from high to low of Al component can be into
One step discharges the stress in epitaxial material, while can be avoided the generation of parasitic channel.
Step S3~S8 refers to S3~S8 of embodiment two, finally obtains the nonpolar InAlN/GaN high that substrate is Si
Electron mobility transistor refers to Fig. 5.
Substrate is that the nonpolar InAlN/GaN high electron mobility transistor of Si includes: Si substrate 301；Low temperature AI N nucleation
Layer 3021 is located on Si substrate 301；High-temperature AlN nucleating layer 3022 is located on low temperature AI N nucleating layer 3021；Gradual change AlGaN at
Stratum nucleare 3023；On high-temperature AlN nucleating layer 3022；Nonpolar buffer layer 303 is located on gradual change AlGaN nucleating layer 3023；It is non-
Polarity channel layer 304 is located on nonpolar buffer layer 303；Insert layer 3041 is located on nonpolar channel layer 304；Nonpolar gesture
Barrier layer 305 is located in insert layer 3041；Source electrode 306 is located on nonpolar channel layer 304；Drain electrode 307 is located at nonpolar channel
On layer 304；Grid 308 is located on nonpolar barrier layer 305, and grid 308 is oriented parallel to c-axis；Protective layer 309, covering
On nonpolar barrier layer 305, source electrode 306, drain electrode 307 and grid 308；Metal interconnection layer 310 is located at source electrode 306, drain electrode
307 and grid 308 on.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be said that
Specific implementation of the invention is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs, exist
Under the premise of not departing from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to of the invention
Protection scope.
Claims (10)
1. a kind of preparation method of nonpolarity InAlN/GaN high electron mobility transistor, which is characterized in that comprising steps of
S1, core layer material is grown on substrate (101), formed nucleating layer (102)；
S2, GaN grown with first condition on the nucleating layer (102), forms nonpolar buffer layer (103)；
S3, GaN grown with second condition on the nonpolar buffer layer (103), forms nonpolar channel layer (104)；
S4, InAlN is grown on the nonpolar channel layer (104), forms nonpolar barrier layer (105)；
S5, production source electrode (106) and drain electrode in the nonpolar channel layer (104) and the nonpolar barrier layer (105)
(107), grid (108) are made on the nonpolar barrier layer (105), obtains nonpolar InAlN/GaN high electron mobility
Transistor.
2. the preparation method of nonpolarity InAlN/GaN high electron mobility transistor as described in claim 1, feature exist
In before step S1 further include:
Nitrogen treatment is carried out to the substrate (101), the temperature of the nitrogen treatment is 828~1012 DEG C.
3. the preparation method of nonpolarity InAlN/GaN high electron mobility transistor as described in claim 1, feature exist
In the first condition are as follows: base-plate temp range is 900~1100 DEG C, and reaction chamber pressure range is 9~11Torr, the source N first
Flow and the source Ga first flow ratio range are 9:1~11:1.
4. the preparation method of nonpolarity InAlN/GaN high electron mobility transistor as claimed in claim 3, feature exist
In the second condition are as follows: base-plate temp range is 900~1100 DEG C, and reaction chamber pressure range is 9~11Torr, the source N second
Flow and the source Ga second flow ratio range are 9:1~11:1, and the source Ga second flow and the source Ga first flow
Ratio is 1:9~1:11, and the ratio of the source N second flow and the source Ga first flow is 1:9~1:11.
5. the preparation method of nonpolarity InAlN/GaN high electron mobility transistor as described in claim 1, feature exist
In step S4 includes:
S41, the growing AIN on the nonpolar channel layer (104), form insert layer (1041)；
S42, InAlN is grown on the insert layer (1041), form the nonpolar barrier layer (105).
6. the preparation method of nonpolarity InAlN/GaN high electron mobility transistor as claimed in claim 1 or 5, feature
It is, the growth conditions of the nonpolarity barrier layer (105) are as follows: base-plate temp range is 650~800 DEG C, reacts chamber pressure model
It encloses for 180~220Torr, the flow ratio range in the source N third flow and the source Al is 75~92, the source the N third flow and In
The flow ratio range in source is 11~14.
7. the preparation method of nonpolarity InAlN/GaN high electron mobility transistor as claimed in claim 6, feature exist
In the material of the nonpolarity barrier layer (105) is In1-xAlxN, wherein x range is 80%~85%.
8. the preparation method of nonpolarity InAlN/GaN high electron mobility transistor as described in claim 1, feature exist
In step S5 includes:
S51, the first metal is deposited on the nonpolar barrier layer (105) using evaporation of metal method, makes annealing treatment described the
One metal makes first metal sink down into the nonpolar channel layer (104), forms source electrode (106) and drain electrode (107)；
S52, the etching nonpolar barrier layer (105), the nonpolar channel layer (104) and the nonpolar buffer layer
(103), isolated groove (1071) are formed；
S53, the second metal is deposited on the nonpolar barrier layer (105) using evaporation of metal method, is formed grid (108).
9. the preparation method of nonpolarity InAlN/GaN high electron mobility transistor as described in claim 1, feature exist
In on the nonpolar barrier layer (105) after production source electrode (106), drain electrode (107) and grid (108) further include:
S6, using plasma enhanced chemical vapor deposition method in the nonpolar barrier layer (105), source electrode (106), drain electrode
(107) and on grid (108) SiN is deposited, is formed protective layer (109)；
S7, photoetching interconnects aperture area on the protective layer (109), makes metal interconnection layer (110) in the interconnection aperture area.
10. a kind of nonpolarity InAlN/GaN high electron mobility transistor, which is characterized in that by any in such as claim 1-9
Method described in is made.
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| CN110444599A (en) * | 2019-08-05 | 2019-11-12 | 中国电子科技集团公司第十三研究所 | GaN base heterojunction field effect transistor and its manufacturing method |
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