CN109300924B

CN109300924B - Image pickup apparatus

Info

Publication number: CN109300924B
Application number: CN201810584008.5A
Authority: CN
Inventors: 佐藤好弘; 平濑顺司; 高见义则
Original assignee: Panasonic Intellectual Property Management Co Ltd
Current assignee: Panasonic Intellectual Property Management Co Ltd
Priority date: 2017-07-24
Filing date: 2018-06-08
Publication date: 2023-11-03
Anticipated expiration: 2038-06-08
Also published as: TW201909383A; CN109300924A; TWI750351B; JP2019024075A

Abstract

An image pickup device capable of suppressing dark current is provided. The imaging device is provided with: a semiconductor substrate including a 1 st diffusion region containing an impurity of a 1 st conductivity type and a 2 nd diffusion region containing an impurity of a 1 st conductivity type; and a plurality of pixels; the plurality of pixels each include: a photoelectric conversion unit that converts light into electric charges; and a 1 st transistor including a source electrode, a drain electrode, and a gate electrode, wherein the 1 st diffusion region for accumulating at least a part of the electric charge is one of the source electrode and the drain electrode, and the 2 nd diffusion region is the other of the source electrode and the drain electrode; the concentration of the 1 st conductive type impurity in the 1 st diffusion region is smaller than the concentration of the 1 st conductive type impurity in the 2 nd diffusion region; the 1 st diffusion region has a smaller area than the 2 nd diffusion region when viewed from a direction perpendicular to the semiconductor substrate.

Description

Image pickup apparatus

Technical Field

The present disclosure relates to an image pickup apparatus.

Background

A CCD (Charge Coupled Device: charge coupled device) image sensor and a CMOS (Complementary Metal Oxide Semiconductor: complementary metal oxide semiconductor) image sensor are widely used in digital cameras and the like. As is well known, these image sensors have photodiodes formed on a semiconductor substrate.

On the other hand, a structure in which a photoelectric conversion portion having a photoelectric conversion layer is disposed above a semiconductor substrate has been proposed (for example, patent documents 1 and 2). An imaging apparatus having such a configuration is sometimes referred to as a stacked imaging apparatus. In a stacked image pickup apparatus, charges generated by photoelectric conversion are stored in a charge storage region (referred to as "FD: floating diffusion"). The signal corresponding to the amount of charge stored in the charge storage region is read out via a CCD circuit or CMOS circuit formed on the semiconductor substrate.

Patent document 1: international publication No. 2014/002330

Patent document 2: international publication No. 2012/147302

Disclosure of Invention

In a stacked image pickup apparatus, there is a case where deterioration occurs in a resulting image due to leakage current (hereinafter, referred to as "dark current") from or to a charge accumulation region. It would be beneficial if such leakage currents could be reduced.

An imaging device according to an aspect of the present disclosure includes: a semiconductor substrate including a 1 st diffusion region containing an impurity of a 1 st conductivity type and a 2 nd diffusion region containing an impurity of a 1 st conductivity type; and a plurality of pixels; the plurality of pixels each include: a photoelectric conversion unit that converts light into electric charges; and a 1 st transistor including a source electrode, a drain electrode, and a gate electrode, wherein the 1 st diffusion region for accumulating at least a part of the electric charge is one of the source electrode and the drain electrode, and the 2 nd diffusion region is the other of the source electrode and the drain electrode; the concentration of the 1 st conductive type impurity in the 1 st diffusion region is lower than the concentration of the 1 st conductive type impurity in the 2 nd diffusion region; the 1 st diffusion region has a smaller area than the 2 nd diffusion region when viewed from a direction perpendicular to the semiconductor substrate.

The inclusion or particular technique may be implemented by an element, device, module, system, or method. Furthermore, the inclusion or particular technique may be implemented by any combination of elements, devices, modules, systems, and methods.

Additional effects and advantages of the disclosed embodiments will become apparent from the description and drawings. The effects and/or advantages are provided by the various embodiments or features disclosed in the specification and drawings, respectively, and not all are required to obtain 1 or more of them.

According to the present disclosure, an image pickup apparatus capable of suppressing dark current can be provided.

Drawings

Fig. 1 is a block diagram of an image pickup apparatus according to the embodiment.

Fig. 2 is a diagram showing a circuit configuration of the imaging device according to the embodiment.

Fig. 3 is a plan view showing a layout in a pixel according to the embodiment.

Fig. 4 is a schematic cross-sectional view of a device structure of a pixel of an embodiment.

Fig. 5 is a diagram showing a circuit configuration of an imaging device according to modification 1 of the embodiment.

Fig. 6 is a plan view showing a layout in a pixel according to modification 1 of the embodiment.

Fig. 7 is a schematic cross-sectional view of a device structure of a pixel according to modification 1 of the embodiment.

Fig. 8 is a plan view showing a layout in a pixel according to modification 2 of the embodiment.

Fig. 9 is a diagram showing a circuit configuration of a pixel according to modification 3 of the embodiment.

Fig. 10 is a plan view showing a layout in a pixel according to modification 3 of the embodiment.

Detailed Description

An outline of an aspect of the present disclosure is as follows.

[ item 1]

An imaging device is provided with: a semiconductor substrate including a 1 st diffusion region containing an impurity of a 1 st conductivity type and a 2 nd diffusion region containing an impurity of a 1 st conductivity type; and a plurality of pixels; the plurality of pixels each include: a photoelectric conversion unit that converts light into electric charges; and a 1 st transistor including a source electrode, a drain electrode, and a gate electrode, wherein the 1 st diffusion region for accumulating at least a part of the electric charge is one of the source electrode and the drain electrode, and the 2 nd diffusion region is the other of the source electrode and the drain electrode; the concentration of the 1 st conductive type impurity in the 1 st diffusion region is lower than the concentration of the 1 st conductive type impurity in the 2 nd diffusion region; the 1 st diffusion region has a smaller area than the 2 nd diffusion region when viewed from a direction perpendicular to the semiconductor substrate.

Thus, the impurity concentration of the 1 st conductivity type contained in the 1 st diffusion region is lower than the impurity concentration of the other diffusion regions containing the 1 st conductivity type impurities in the pixel. Thus, the bonding concentration at the bonding portion of the 1 st diffusion region and the semiconductor substrate becomes small, so that the leakage current in the 1 st diffusion region is reduced.

Further, the area of the depletion layer formed at the junction of the 1 st diffusion region and the semiconductor substrate, in particular, the depletion layer on the surface of the semiconductor substrate can be reduced. Since the crystal defect becomes large in the vicinity of the surface of the semiconductor substrate, if a depletion layer is formed here, the leakage current becomes large. Thus, by reducing the area of the depletion layer on the surface of the semiconductor substrate, the leakage current can be reduced.

[ item 2]

The image pickup device according to item 1, wherein the semiconductor substrate further includes a 3 rd diffusion region containing an impurity of a 1 st conductivity type; each of the plurality of pixels includes a 2 nd transistor including the 3 rd diffusion region as one of a source and a drain; the concentration of the 1 st conductive type impurity in the 1 st diffusion region is lower than the concentration of the 1 st conductive type impurity in the 3 rd diffusion region.

[ item 3]

The image pickup device according to item 1 or 2, wherein each of the plurality of pixels includes a 3 rd transistor including the 1 st diffusion region as one of a source and a drain.

[ item 4]

The imaging device according to item 1, wherein the area of the 1 st diffusion region is an area of a portion of the 1 st diffusion region that does not overlap with the gate electrode when viewed from a direction perpendicular to the semiconductor substrate; the area of the 2 nd diffusion region is an area of a portion of the 2 nd diffusion region that does not overlap with the gate electrode when viewed from a direction perpendicular to the semiconductor substrate.

[ item 5]

The image pickup device according to any one of items 1 to 4, wherein each of the plurality of pixels includes: a 1 st plug connected to a 1 st portion of the 1 st diffusion region; and a 2 nd plug connected to a 2 nd portion of the 2 nd diffusion region; the distance between the 1 st portion and the gate electrode is smaller than the distance between the 2 nd portion and the gate electrode when viewed from a direction perpendicular to the semiconductor substrate.

Thus, the distance from the 1 st plug of the 1 st diffusion region to the gate electrode of the 1 st transistor becomes short, so that the rise in the resistance value of the 1 st diffusion region can be reduced.

[ item 6]

The image pickup device according to any one of items 1 to 5, wherein the semiconductor substrate includes a 4 th diffusion region including an impurity of a 2 nd conductivity type different from the 1 st conductivity type; the plurality of pixels each include a transistor other than the 1 st transistor, and include the 4 th diffusion region as a separation region for separating the 1 st transistor from the other transistors; the 4 th diffusion region is not in contact with the 1 st diffusion region in the surface of the semiconductor substrate.

In this way, the 1 st diffusion region containing the 1 st conductive type impurity and the separation region containing the 2 nd conductive type impurity different from the 1 st conductive type impurity are not in contact with each other in the surface of the semiconductor substrate where the leakage current is most likely to occur, so that the leakage current at the junction portion of the surface of the semiconductor substrate can be reduced.

[ item 7]

The image pickup device according to any one of items 1 to 6, wherein the semiconductor substrate contains an impurity of a 2 nd conductivity type different from the 1 st conductivity type; the concentration of the impurity of the 1 st conductivity type contained in the 1 st diffusion region is 1×10 ¹⁶ atoms/cm ³ Above and 5×10 ¹⁶ atoms/cm ³ The following are set forth; the concentration of the impurity of the 2 nd conductivity type contained in the portion adjacent to the 1 st diffusion region in the semiconductor substrate is 1×10 ¹⁶ atoms/cm ³ Above and 5×10 ¹⁶ atoms/cm ³ The following is given.

By reducing the concentrations of the impurities of the 1 st conductivity type and the 2 nd conductivity type in this manner, an increase in the electric field strength at the junction between the 1 st diffusion region and the semiconductor substrate can be suppressed, and leakage current can be reduced.

[ item 8]

The image pickup device according to any one of items 1 to 7, wherein the 1 st diffusion region is circular when viewed from a direction perpendicular to the semiconductor substrate.

Thus, the area of the 1 st diffusion region on the surface of the semiconductor substrate is reduced, so that the area of the depletion layer formed at the junction of the surface of the semiconductor substrate can be reduced. Thus, leakage current can be reduced.

[ item 9]

An imaging device is provided with: a semiconductor substrate including a 1 st diffusion region containing an impurity of a 1 st conductivity type and a 2 nd diffusion region containing an impurity of a 1 st conductivity type; and a plurality of pixels; the plurality of pixels each include: a photoelectric conversion unit that converts light into electric charges; a 1 st transistor including a source electrode, a drain electrode, and a gate electrode, wherein the 1 st diffusion region for accumulating at least a part of the electric charge is one of the source electrode and the drain electrode, and the 2 nd diffusion region is the other of the source electrode and the drain electrode; a 1 st plug connected to a 1 st portion of the 1 st diffusion region; and a 2 nd plug connected to a 2 nd portion of the 2 nd diffusion region; the concentration of the 1 st conductive type impurity in the 1 st diffusion region is lower than the concentration of the 1 st conductive type impurity in the 2 nd diffusion region; the distance between the 1 st portion and the gate electrode is smaller than the distance between the 2 nd portion and the gate electrode when viewed from a direction perpendicular to the semiconductor substrate.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments described below are all inclusive and specific examples. The numerical values, shapes, materials, components, arrangement and connection forms of the components, steps, order of steps, and the like shown in the following embodiments are examples, and are not intended to limit the present disclosure. The various aspects described in the present specification can be combined with each other as long as no contradiction occurs. Among the constituent elements of the following embodiments, constituent elements not described in the independent claims showing the uppermost concepts are described as arbitrary constituent elements. In the drawings, constituent elements having substantially the same function are denoted by common reference numerals, and a repetitive description thereof may be omitted or abbreviated.

The various elements shown in the drawings are schematically shown for the understanding of the present disclosure, and the dimensional ratio, appearance, and the like may be different from those of the actual objects.

In the present specification, the light receiving side of the imaging device is referred to as "upper", and the side opposite to the light receiving side is referred to as "lower". The "upper surface" and the "lower surface" of each member are also referred to as "upper surfaces" and "lower surfaces" respectively, with respect to the surface facing the light receiving side of the imaging device. The terms "upper", "lower", "upper surface", and "lower surface" are used merely to designate the mutual arrangement of the components, and are not intended to limit the posture of the imaging device in use.

(embodiment)

Fig. 1 is a block diagram of an image pickup apparatus according to the present embodiment. As shown in fig. 1, an image pickup device 100A according to the present embodiment includes a plurality of pixels 10A and peripheral circuits 40 formed on a semiconductor substrate 60. Each pixel 10A includes a photoelectric conversion portion 12 disposed above a semiconductor substrate 60. That is, as an example of the imaging apparatus of the present disclosure, the stacked imaging apparatus 100A will be described.

In the example shown in fig. 1, the pixels 10A are arranged in a matrix of m rows and n columns. Here, m and n are integers of 2 or more. The pixels 10A form an image pickup region R1 by being arranged two-dimensionally on the semiconductor substrate 60, for example. As described above, each pixel 10A includes the photoelectric conversion portion 12 disposed above the semiconductor substrate 60. Therefore, the imaging region R1 is defined as a region of the semiconductor substrate 60 covered with the photoelectric conversion portion 12. In fig. 1, the photoelectric conversion units 12 of the pixels 10A are shown spatially separated from each other from the viewpoint of facilitating the description, but the photoelectric conversion units 12 of the pixels 10A may be arranged on the semiconductor substrate 60 without being spaced apart from each other.

The number and arrangement of the pixels 10A are not limited to the illustrated example. For example, the number of pixels 10A included in the image pickup device 100A may be 1. In this example, the center of each pixel 10A is located on a lattice point of a square lattice, but the arrangement of the pixels 10A may not be the same. For example, the plurality of pixels 10A may be arranged such that each center is located at a lattice point of a triangular lattice, a hexagonal lattice, or the like. If the pixels 10A are arranged one-dimensionally, the image pickup device 100A may be used as a line sensor.

In the structure illustrated in fig. 1, the peripheral circuit 40 includes a vertical scanning circuit (also referred to as a "row scanning circuit") 46 and a horizontal signal readout circuit (also referred to as a "column scanning circuit") 48. The vertical scanning circuit 46 has a connection to the address signal line 34 provided corresponding to each row of the plurality of pixels 10A. The horizontal signal readout circuit 48 has a connection with the vertical signal line 35 provided corresponding to each column of the plurality of pixels 10A. As schematically shown in fig. 1, these circuits are arranged in a peripheral region R2 outside the image pickup region R1. The peripheral circuit 40 may further include a signal processing circuit, an output circuit, a control circuit, a power supply for supplying a predetermined voltage to each pixel 10A, and the like. A part of the peripheral circuit 40 may be arranged on a different substrate from the semiconductor substrate 60 on which the pixels 10A are formed.

Fig. 2 is a diagram showing a circuit configuration of the imaging device 100A according to the embodiment. Fig. 2 shows 4 pixels 10A arranged in 2 rows and 2 columns among the plurality of pixels 10A shown in fig. 1, in order to avoid complicating the illustration.

The photoelectric conversion portion 12 of each pixel 10A receives light incidence and generates positive and negative charges (typically, hole-electron pairs). The photoelectric conversion unit 12 of each pixel 10A has a connection to the accumulation control line 39, and applies a predetermined voltage to the accumulation control line 39 during operation of the imaging device 100A. By applying a predetermined voltage to the accumulation control line 39, one of positive and negative charges generated by photoelectric conversion can be selectively accumulated in the charge accumulation region. Hereinafter, a case of using positive charges among positive and negative charges generated by photoelectric conversion as signal charges will be described.

Each pixel 10A includes a signal detection circuit 14 electrically connected to the photoelectric conversion portion 12. In the structure illustrated in fig. 2, the signal detection circuit 14 includes an amplifying transistor 22 (also referred to as a "readout transistor") and a reset transistor 26. In this example, the signal detection circuit 14 further includes an address transistor (also referred to as a "row select transistor") 24. As will be described in detail later with reference to the drawings, the amplifying transistor 22, the reset transistor 26, and the address transistor 24 of the signal detection circuit 14 are typically field effect transistors (FETs: field Effect Transistor) formed on the semiconductor substrate 60 supporting the photoelectric conversion portion 12. Hereinafter, unless otherwise specified, an example in which an N-channel MOS (Metal Oxide Semiconductor) transistor is used as a transistor will be described. In addition, which of the 2 diffusion layers of the FET corresponds to the source and drain is determined by the polarity of the FET and the level of the potential at that point. Therefore, which source and drain may vary depending on the operating state of the FET.

As schematically shown in fig. 2, the gate of the amplifying transistor 22 is electrically connected to the photoelectric conversion portion 12. The charge generated by the photoelectric conversion portion 12 is stored in a charge storage region on a charge storage node (also referred to as a "floating diffusion node") ND connected between the photoelectric conversion portion 12 and the amplifying transistor 22. The charge storage node ND is a wiring and a charge storage region that electrically connect the charge storage region, the gate of the amplifying transistor 22, and the lower electrode of the photoelectric conversion unit 12.

The drain of the amplifying transistor 22 is connected to a power supply wiring (also referred to as a source follower power supply) 32 that supplies a predetermined power supply voltage VDD (for example, about 3.3V) to each pixel 10A during operation of the image pickup device 100A. In other words, the amplifying transistor 22 outputs a signal voltage corresponding to the amount of signal charge generated by the photoelectric conversion portion 12. The source of the amplifying transistor 22 is connected to the drain of the address transistor 24.

A vertical signal line 35 is connected to the source of the address transistor 24. As shown in the figure, the vertical signal lines 35 are provided for each column of the plurality of pixels 10A, and a load circuit 42 and a column signal processing circuit (also referred to as a "row signal storage circuit") 44 are connected to each of the vertical signal lines 35. The load circuit 42 forms a source follower circuit together with the amplifying transistor 22.

An address signal line 34 is connected to the gate of the address transistor 24. The address signal lines 34 are provided for each row of the plurality of pixels 10A. The address signal line 34 is connected to the vertical scanning circuit 46, and the vertical scanning circuit 46 applies a row selection signal to the address signal line 34, which controls the on and off of the address transistor 24. Thus, the row to be read is scanned in the vertical direction (column direction), and the row to be read is selected. The vertical scanning circuit 46 can read out the output of the amplifying transistor 22 of the selected pixel 10A to the corresponding vertical signal line 35 by controlling the on and off of the address transistor 24 via the address signal line 34. The arrangement of the address transistor 24 is not limited to the example shown in fig. 2, and may be between the drain of the amplifying transistor 22 and the power supply wiring 32.

The signal voltage from the pixel 10A outputted to the vertical signal line 35 via the address transistor 24 is inputted to a corresponding column signal processing circuit 44 of a plurality of column signal processing circuits 44 provided for each column of the plurality of pixels 10A corresponding to the vertical signal line 35. The column signal processing circuit 44 and the load circuit 42 may be part of the peripheral circuit 40 described above.

The column signal processing circuit 44 performs noise suppression signal processing typified by correlated double sampling, analog-to-digital conversion (AD conversion), and the like. The column signal processing circuit 44 is connected to a horizontal signal readout circuit 48. The horizontal signal reading circuit 48 sequentially reads out signals from the plurality of column signal processing circuits 44 to the horizontal common signal line 49.

In the structure illustrated in fig. 2, the signal detection circuit 14 includes a reset transistor 26 whose drain is connected to the charge accumulation node ND. A reset signal line 36 having a connection to the vertical scanning circuit 46 is connected to the gate of the reset transistor 26. The reset signal lines 36 are provided for each row of the plurality of pixels 10A, similarly to the address signal lines 34. The vertical scanning circuit 46 can select the pixel 10A to be reset in row units by applying a row selection signal to the address signal line 34. Further, the vertical scanning circuit 46 can turn on the reset transistor 26 of the selected row by applying a reset signal that controls the on and off of the reset transistor 26 to the gate of the reset transistor 26 via the reset signal line 36. The potential of the charge accumulation node ND is reset by the reset transistor 26 being turned on.

In this example, the source of the reset transistor 26 is connected to 1 of the feedback lines 53 provided for each column of the plurality of pixels 10A. That is, in this example, as a reset voltage for initializing the charge of the photoelectric conversion portion 12, the voltage of the feedback line 53 is supplied to the charge accumulation node ND. Here, the feedback lines 53 described above are connected to the output terminals of the corresponding 1 of the inverting amplifiers 50 provided for each column of the plurality of pixels 10A. The inverting amplifier 50 may be part of the peripheral circuit 40 described above.

Focusing on 1 of the columns of the plurality of pixels 10A. As shown, the inverting input terminal of the inverting amplifier 50 is connected to the vertical signal line 35 of the column. Further, the output terminal of the inverting amplifier 50 and 1 or more pixels 10A belonging to the column are connected via the feedback line 53. During operation of the image pickup apparatus 100A, a predetermined voltage Vref (for example, a positive voltage around 1V or 1V) is supplied to the non-inverting input terminal of the inverting amplifier 50. By selecting 1 of the 1 or more pixels 10A belonging to the column, the address transistor 24 and the reset transistor 26 are turned on, and a feedback path for negatively feeding back the output of the pixel 10A can be formed. By the formation of the feedback path, the voltage of the vertical signal line 35 converges to the input voltage Vref to the non-inverting input terminal of the inverting amplifier 50. In other words, by the formation of the feedback path, the voltage of the charge accumulation node ND is reset to a voltage such that the voltage of the vertical signal line 35 becomes Vref. As the voltage Vref, a voltage having any magnitude in a range of a power supply voltage (for example, 3.3V) and a ground voltage (0V) can be used. Inverting amplifier 50 may also be referred to as a feedback amplifier. In this way, the image pickup apparatus 100A has the feedback circuit 16 including the inverting amplifier 50 in a part of the feedback path.

As is well known, thermal noise called kTC noise occurs as the transistor turns on or off. The noise occurring with the turning on or off of the reset transistor is referred to as reset noise. After resetting the potential of the charge accumulation region, reset noise generated by turning off the reset transistor remains in the charge accumulation region before accumulation of the signal charge. However, reset noise occurring with the reset transistor turned off can be reduced by using feedback. Details of suppression of reset noise by feedback are described in international publication No. 2012/147302. For reference, the entire disclosure of international publication No. 2012/147302 is incorporated in this specification.

In the configuration illustrated in fig. 2, the ac component of thermal noise is fed back to the source of the reset transistor 26 by the formation of the feedback path. In the structure illustrated in fig. 2, since the feedback path is formed immediately before the reset transistor 26 is turned off, reset noise occurring with the turning off of the reset transistor 26 can be reduced.

Fig. 3 is a plan view showing a layout in the pixel 10A according to the embodiment. Fig. 4 is a schematic cross-sectional view of the device configuration of the pixel 10A. Fig. 3 schematically shows the arrangement of the elements (the amplifying transistor 22, the address transistor 24, the reset transistor 26, and the like) formed on the semiconductor substrate 60 when the pixel 10A shown in fig. 4 is viewed from the direction perpendicular to the semiconductor substrate 60. Here, the amplifying transistor 22 and the address transistor 24 are arranged in a straight line along the up-down direction of the paper surface.

Fig. 4 is a schematic cross-sectional view of the device structure of the pixel 10A of the embodiment. Fig. 4 is a cross-sectional view taken along line A-A in fig. 3, in which the pixel 10A is cut and developed in the direction of the arrow.

In fig. 3 and 4, the 1 st diffusion region 67n, which is an n-type impurity region, is a drain region of the reset transistor 26, and is a charge storage region (FD).

As shown in fig. 3 and 4, the pixel 10A in the image pickup device 100A according to the present embodiment includes a 1 st transistor (here, the reset transistor 26). The 1 st transistor is provided in the semiconductor substrate, includes an impurity of 1 st conductivity type (hereinafter referred to as n-type), includes a 1 st diffusion region 67n for accumulating the photo-charges converted by the photoelectric conversion unit 12 as one of a source and a drain, and includes a 2 nd diffusion region 68an as an n-type impurity region containing n-type impurities as the other of the source and the drain. In the present embodiment, the concentration of the n-type impurity in the 1 st diffusion region 67n is smaller than the concentration of the n-type impurity in the 2 nd diffusion region 68 an.

Further, the pixel 10A includes a 2 nd transistor (here, the amplifying transistor 22 or the address transistor 24) different from the reset transistor 26, and the 2 nd transistor is located in the semiconductor substrate 60 and includes a 3 rd diffusion region (hereinafter, referred to as other n-type impurity regions 68bn, 68cn, 68 dn) containing n-type impurities as a source or a drain. At this time, the concentration of the n-type impurity in the 1 st diffusion region 67n may be smaller than the concentrations of the n-type impurities in the other n-type impurity regions 68bn, 68cn, and 68dn (hereinafter, 68bn to 68 dn). At this time, the concentration of the n-type impurity in the 1 st diffusion region 67n may be at least 1/10 or less than 1/15 of the concentration of the n-type impurity in the 2 nd diffusion region 68an and the other n-type impurity regions 68bn to 68 dn. Accordingly, the bonding concentration at the bonding portion between the 1 st diffusion region 67n and the semiconductor substrate 60 becomes small, so that the electric field strength at the bonding portion can be relaxed. Therefore, leakage current from the 1 st diffusion region 67n as a charge accumulation region or to the 1 st diffusion region 67n is reduced.

In the imaging device 100A according to the present embodiment, the semiconductor substrate 60 contains an impurity of the 2 nd conductivity type (hereinafter, referred to as p-type), and the concentration of the n-type impurity contained in the 1 st diffusion region 67n and the p-type impurity contained in the portion of the semiconductor substrate 60 adjacent to the 1 st diffusion region 67n may be 1×10 ¹⁶ atoms/cm ³ Above 5×10 ¹⁶ atoms/cm ³ The following is given. As a result, the bonding concentration between the 1 st diffusion region 67n and the semiconductor substrate 60 becomes small, and an increase in the electric field strength at the bonding portion can be suppressed. Therefore, leakage current at the junction can be reduced.

As schematically shown in fig. 4, the pixel 10A generally includes a semiconductor substrate 60, a photoelectric conversion portion 12 disposed above the semiconductor substrate 60, and a wiring structure 80. The wiring structure 80 includes a structure which is disposed in the interlayer insulating layer 90 formed between the photoelectric conversion portion 12 and the semiconductor substrate 60 and electrically connects the amplifying transistor 22 formed on the semiconductor substrate 60 and the photoelectric conversion portion 12. Here, the interlayer insulating layer 90 has a laminated structure of 4 insulating layers including insulating layers 90a, 90b, 90c, and 90d (hereinafter referred to as 90a to 90 d), and the wiring structure 80 has 4 wiring layers of the wiring layers 80a, 80b, 80c, and 80d (hereinafter referred to as 80a to 80 d), and plugs (plug) pa1, pa2, pb, pc, and pd arranged between these wiring layers. The wiring layer 80a includes contact plugs cp1, cp2, cp3, cp4, cp5, cp6, and cp7 (hereinafter referred to as cp1 to cp 7). Note that the number of insulating layers in the interlayer insulating layer 90 and the number of wiring layers in the wiring structure 80 are not limited to this example, and may be arbitrarily set.

The photoelectric conversion portion 12 is disposed on the interlayer insulating layer 90. The photoelectric conversion portion 12 includes a pixel electrode 12a formed over the interlayer insulating layer 90, a transparent electrode 12c opposed to the pixel electrode 12a, and a photoelectric conversion layer 12b disposed between these electrodes. The photoelectric conversion layer 12b of the photoelectric conversion unit 12 is formed of an inorganic material such as an organic material or amorphous silicon, and receives light incident through the transparent electrode 12c, and generates positive and negative charges by photoelectric conversion. The photoelectric conversion layer 12b is typically formed across a plurality of pixels 10A. The photoelectric conversion layer 12b may include a layer made of an organic material and a layer made of an inorganic material.

The transparent electrode 12c is formed of a transparent conductive material such as ITO, and is disposed on the light-receiving surface side of the photoelectric conversion layer 12b. The transparent electrode 12c is typically formed across a plurality of pixels 10A, as is the case with the photoelectric conversion layer 12b. Although not shown in fig. 4, the transparent electrode 12c has a connection to the accumulation control line 39. In the operation of the image pickup device 100A, the potential of the storage control line 39 is controlled to make the potential of the transparent electrode 12c different from the potential of the pixel electrode 12a, so that the signal charges generated by photoelectric conversion can be collected by the pixel electrode 12 a. For example, the potential of the accumulation control line 39 is controlled so that the potential of the transparent electrode 12c becomes higher than the potential of the pixel electrode 12 a. Specifically, a positive voltage of, for example, about 10V is applied to the accumulation control line 39. Thus, holes in the hole-electron pair generated by the photoelectric conversion layer 12b can be collected by the pixel electrode 12 a. The signal charges collected by the pixel electrode 12a are accumulated in the 1 st diffusion region 67n via the wiring structure 80.

The pixel electrode 12a is an electrode formed of a metal such as aluminum or copper, a metal nitride, or polysilicon to which conductivity is imparted by doping impurities. The pixel electrode 12a is spatially separated from the pixel electrode 12a of the adjacent other pixel 10A, and is electrically separated from the pixel electrode 12a of the other pixel 10A.

The semiconductor substrate 60 includes a support substrate 61 and 1 or more semiconductor layers formed on the support substrate 61. Here, a p-type silicon (Si) substrate is exemplified as the support substrate 61. In this example, the semiconductor substrate 60 has a p-type semiconductor layer 61p on the support substrate 61, an n-type semiconductor layer 62n on the p-type semiconductor layer 61p, a p-type semiconductor layer 63p on the n-type semiconductor layer 62n, and a p-type semiconductor layer 65p on the p-type semiconductor layer 63 p. The p-type semiconductor layer 63p is formed over the entire surface of the support substrate 61. The p-type semiconductor layer 65p includes a p-type impurity region 66p having a lower impurity concentration than the p-type semiconductor layer 65p, a 1 st diffusion region 67n, a 2 nd diffusion region 68an, n-type impurity regions 68bn to 68dn, and an element isolation region 69 formed in the p-type impurity region 66 p.

The p-type semiconductor layer 61p, the n-type semiconductor layer 62n, the p-type semiconductor layer 63p, and the p-type semiconductor layer 65p are each typically formed by ion implantation of impurities into a semiconductor layer formed by epitaxial growth. The impurity concentrations in the p-type semiconductor layer 63p and the p-type semiconductor layer 65p are the same level as each other and are higher than the impurity concentration of the p-type semiconductor layer 61 p. The n-type semiconductor layer 62n arranged between the p-type semiconductor layer 61p and the p-type semiconductor layer 63p suppresses inflow of a small amount of carriers from the support substrate 61 or the peripheral circuit 40 into the 1 st diffusion region 67n which is a charge accumulation region for accumulating signal charges. During operation of the imaging device 100A, the potential of the n-type semiconductor layer 62n is controlled via a well contact portion (not shown) provided outside the imaging region R1 (see fig. 1).

In this example, the semiconductor substrate 60 has a p-type region 64 provided between the p-type semiconductor layer 63p and the support substrate 61 so as to penetrate the p-type semiconductor layer 61p and the n-type semiconductor layer 62 n. The p-type region 64 has a higher impurity concentration than the p-type semiconductor layer 63p and the p-type semiconductor layer 65p, and electrically connects the p-type semiconductor layer 63p and the support substrate 61. During operation of the imaging device 100A, the potentials of the p-type semiconductor layer 63p and the support substrate 61 are controlled via a substrate contact portion (not shown) provided outside the imaging region R1. By disposing the p-type semiconductor layer 65p so as to contact the p-type semiconductor layer 63p, the potential of the p-type semiconductor layer 65p can be controlled via the p-type semiconductor layer 63p during operation of the imaging device 100A.

On the semiconductor substrate 60, the amplifying transistor 22, the address transistor 24, and the reset transistor 26 are formed. The reset transistor 26 includes a 1 st diffusion region 67n and a 2 nd diffusion region 68an, an insulating layer 70 formed on the semiconductor substrate 60, and a gate electrode 26e formed on the insulating layer 70. The 1 st diffusion region 67n and the 2 nd diffusion region 68an function as drain regions and source regions of the reset transistor 26, respectively. The 1 st diffusion region 67n functions as a charge accumulation region for temporarily accumulating the signal charges generated by the photoelectric conversion unit 12.

The amplifying transistor 22 includes n-type impurity regions 68bn and 68cn, a portion of the insulating layer 70, and a gate electrode 22e on the insulating layer 70. The n-type impurity regions 68bn and 68cn function as a drain region and a source region of the amplifying transistor 22, respectively.

An element separation region 69 is arranged between the n-type impurity region 68bn and the 1 st diffusion region 67 n. The element separation region 69 is, for example, a p-type impurity diffusion region. The amplifying transistor 22 and the reset transistor 26 are electrically separated by an element separation region 69.

As schematically shown in fig. 4, the 1 st diffusion region 67n and the element separation region 69 are arranged so as not to contact each other by forming the 1 st diffusion region 67n in the p-type impurity region 66 p. For example, in the case of using a p-type impurity layer as the element separation region 69, if the 1 st diffusion region 67n is in contact with the element separation region 69, both the p-type impurity concentration and the n-type impurity concentration at the junction portion become high. Therefore, a leakage current due to the high junction concentration easily occurs around the junction between the 1 st diffusion region 67n and the element isolation region 69. In other words, by disposing the 1 st diffusion region 67n and the element isolation region 69 so as not to contact each other, even if a high-concentration p-type impurity layer is used in the element isolation region 69, the rise in the pn junction concentration can be suppressed, and the leakage current can be suppressed. In addition, although there is a method using STI (Shallow Trench Isolation: shallow trench isolation) as the element isolation region 69, in this case, it is preferable that the 1 st diffusion region 67n and STI are arranged so as not to contact each other in order to reduce leakage current due to crystal defects at the STI sidewall portion.

The element separation region 69 is also arranged between the pixels 10A adjacent to each other, and electrically separates the signal detection circuits 14 from each other therebetween. Here, the element separation region 69 is provided around the group of the amplifying transistor 22 and the address transistor 24 and around the reset transistor 26.

The address transistor 24 includes n-type impurity regions 68cn and 68dn, a portion of an insulating layer 70, and a gate electrode 24e on the insulating layer 70. In this example, the address transistor 24 is electrically connected to the amplifying transistor 22 by sharing the n-type impurity region 68cn with the amplifying transistor 22. The n-type impurity region 68cn functions as a drain region of the address transistor 24, and the n-type impurity region 68dn functions as a source region of the address transistor 24.

In this example, the insulating layer 72 is provided so as to cover the gate electrode 26e of the reset transistor 26, the gate electrode 22e of the amplifying transistor 22, and the gate electrode 24e of the address transistor 24. The insulating layer 72 is, for example, a silicon oxide film. In this example, an insulating layer 71 is interposed between the insulating layer 72 and the gate electrode 26e, the gate electrode 22e, and the gate electrode 24e. The insulating layer 71 is, for example, a silicon oxide film. The insulating layer 71 may have a laminated structure including a plurality of insulating layers. Similarly, the insulating layer 72 may have a laminated structure including a plurality of insulating layers.

The stacked structure of the insulating layer 72 and the insulating layer 71 has a plurality of contact holes. Here, the insulating layers 72 and 71 are provided with contact holes h1 to h7. The contact holes h1 to h4 are formed at positions overlapping the 1 st diffusion region 67n, the 2 nd diffusion region 68an, and the other n-type impurity regions 68bn and 68dn, respectively. Contact plugs cp1 to cp4 are disposed at the positions of the contact holes h1 to h4, respectively. Contact holes h5 to h7 are formed at positions overlapping with the gate electrode 26e, the gate electrode 22e, and the gate electrode 24e, respectively. Contact plugs cp5 to cp7 are respectively arranged at the positions of the contact holes h5 to h7.

In the structure illustrated in fig. 4, the wiring layer 80a is a layer having contact plugs cp1 to cp7, typically a polysilicon layer doped with n-type impurities. The wiring layer 80a is disposed closest to the semiconductor substrate 60 among the wiring layers included in the wiring structure 80. The wiring layer 80b and the plugs pa1 and pa2 are disposed in the insulating layer 90 a. The plug pa1 connects the contact plug cp1 and the wiring layer 80b, and the plug pa2 connects the contact plug cp6 and the wiring layer 80 b. That is, the 1 st diffusion region 67n and the gate electrode 22e of the amplifying transistor 22 are electrically connected to each other via the contact plugs cp1 and cp6, the plugs pa1 and pa2, and the wiring layer 80 b.

The wiring layer 80b is disposed in the insulating layer 90a, and may include the vertical signal line 35, the address signal line 34, the power supply wiring 32, the reset signal line 36, the feedback line 53, and the like in a part thereof. The vertical signal line 35, the address signal line 34, the power supply wiring 32, the reset signal line 36, and the feedback line 53 are connected to the n-type impurity region 68dn, the gate electrode 24e, the n-type impurity region 68bn, the gate electrode 26e, and the 2 nd diffusion region 68an through the contact plugs cp4, cp7, cp3, cp5, and cp2, respectively.

The plug pb disposed in the insulating layer 90b connects the wiring layer 80b and the wiring layer 80 c. Similarly, a plug pc disposed in the insulating layer 90c connects the wiring layer 80c and the wiring layer 80 d. The plug pd disposed in the insulating layer 90d connects the wiring layer 80d to the pixel electrode 12a of the photoelectric conversion portion 12. The wiring layers 80b to 80d and the plugs pa1, pa2, pb to pd are typically formed of a metal such as copper or tungsten, a metal compound such as a metal nitride or a metal oxide, or the like.

The plugs pa1, pa2, pb to pd, the wiring layers 80b to 80d, and the contact plugs cp1, cp6 electrically connect the photoelectric conversion portion 12 to the signal detection circuit 14 formed on the semiconductor substrate 60. The plugs pa1, pa2, pb to pd, the wiring layers 80b to 80d, the contact plugs cp1, cp6, the pixel electrode 12a of the photoelectric conversion portion 12, the gate electrode 22e of the amplifying transistor 22, and the 1 st diffusion region 67n store signal charges (holes in this case) generated by the photoelectric conversion portion 12.

Here, attention is paid to an n-type impurity region formed on the semiconductor substrate 60. The 1 st diffusion region 67n among the n-type impurity regions formed on the semiconductor substrate 60 is arranged in the p-type impurity region 66p formed in the p-type semiconductor layer 65p as a p-well. The 1 st diffusion region 67n is formed near the surface of the semiconductor substrate 60, and at least a part thereof is located on the surface of the semiconductor substrate 60. The junction capacitance formed by the pn junction between the p-type impurity region 66p and the 1 st diffusion region 67n functions as a capacitance for accumulating at least a part of the signal charge, and constitutes a part of the charge accumulation region.

In the structure illustrated in fig. 4, the 1 st diffusion region 67n includes a 1 st region 67a and a 2 nd region 67b. The 1 st region 67a of the 1 st diffusion region 67n has an impurity concentration lower than that of the 2 nd diffusion region 68an and other n-type impurity regions 68bn to 68 dn. The 2 nd region 67b of the 1 st diffusion region 67n is formed within the 1 st region 67a, and has a higher impurity concentration than the 1 st region 67 a. Further, the contact hole h1 is located on the 2 nd region 67b, and the contact plug cp1 is connected to the 2 nd region 67b via the contact hole h 1.

As described above, by disposing the p-type semiconductor layer 65p adjacent to the p-type semiconductor layer 63p, the potential of the p-type semiconductor layer 65p can be controlled via the p-type semiconductor layer 63p during operation of the imaging device 100A. By adopting such a structure, regions (here, the 1 st region 67a and the p-type impurity region 66p of the 1 st diffusion region 67 n) having relatively low impurity concentrations can be arranged around a portion (here, the 2 nd region 67b of the 1 st diffusion region 67 n) where the contact plug cp1 electrically connected to the photoelectric conversion portion 12 contacts the semiconductor substrate 60. The formation of the 2 nd region 67b in the 1 st diffusion region 67n is not necessary. However, by making the impurity concentration of the 2 nd region 67b, which is the connection portion between the contact plug cp1 and the semiconductor substrate 60, relatively high, the effect of diffusing the depletion layer around (depleting) the connection portion between the contact plug cp1 and the semiconductor substrate 60 can be obtained. In this way, by suppressing depletion around the portion where the contact plug cp1 contacts the semiconductor substrate 60, leakage current due to crystal defects (may also be referred to as interface levels) of the semiconductor substrate 60 at the interface of the contact plug cp1 and the semiconductor substrate 60 can be suppressed. Further, by connecting the contact plug cp1 to the 2 nd region 67b having a relatively high impurity concentration, an effect of reducing contact resistance can be obtained.

In this example, the 1 st region 67a having a lower impurity concentration than the 2 nd region 67b is sandwiched between the 2 nd region 67b of the 1 st diffusion region 67n and the p-type impurity region 66p, and the 1 st region 67a is also sandwiched between the 2 nd region 67b of the 1 st diffusion region 67n and the p-type semiconductor layer 65 p. By disposing the 1 st region 67a having a relatively low impurity concentration around the 2 nd region 67b, the electric field strength formed by the pn junction between the 1 st diffusion region 67n and the p-type semiconductor layer 65p or the p-type impurity region 66p can be relaxed. By relaxing the electric field strength, leakage current due to an electric field formed by the pn junction is suppressed.

As schematically shown in fig. 3, the pixel 10A includes a separation region (hereinafter, referred to as an element separation region 69) for separating the reset transistor 26 having the 1 st diffusion region 67n and the 2 nd diffusion region 68an as a source and a drain from other transistors (here, the amplifying transistor 22 and the address transistor 24) included in the pixel 10A. The element isolation region 69 contains, for example, an impurity of the 2 nd conductivity type (hereinafter referred to as p-type) different from the n-type. At this time, the 1 st diffusion region 67n and the element separation region 69 formed around the 1 st diffusion region 67n are arranged so as not to contact each other in the surface of the semiconductor substrate 60.

Specifically, the 1 st diffusion region 67n is formed in the p-type impurity region 66p having a lower concentration of impurities than the p-type semiconductor layer 65 p. A depletion layer region is formed between the 1 st diffusion region 67n and the p-type impurity region 66 p. In general, the crystal defect density near the surface of the semiconductor substrate 60 is higher than the crystal defect density in the interior of the semiconductor substrate 60. Therefore, of the depletion layer region formed at the junction (pn junction) where the 1 st diffusion region 67n and the p-type impurity region 66p are joined, the depletion layer region formed at the junction near the surface of the semiconductor substrate 60 has a larger leakage current than the depletion layer region formed at the pn junction inside the semiconductor substrate 60.

Further, if the area of a depletion layer region (hereinafter, referred to as an interface depletion layer) formed at the junction portion of the surface of the semiconductor substrate 60 increases, the leakage current tends to increase. Therefore, it is desirable to minimize the area of the interface depletion layer exposed on the surface of the semiconductor substrate 60. In order to reduce the area of the interface depletion layer, the area of the 1 st diffusion region 67n may be smaller than the 2 nd diffusion region 68an when viewed from the direction perpendicular to the semiconductor substrate 60. For example, the area of the 1 st diffusion region 67n may be 1/2 or less of the area of the 2 nd diffusion region 68an when viewed from the direction perpendicular to the semiconductor substrate 60. In this case, the width of the 1 st diffusion region 67n in the channel width direction may be 1/2 or less of the width of the 2 nd diffusion region 68an in the channel width direction. The 1 st diffusion region 67n and the 2 nd diffusion region 68an may have the same width in the channel width direction and the same length in the channel length direction. In addition, as for the other n-type impurity regions 68bn to 68dn in the pixel 10A, the area of the 1 st diffusion region 67n may be formed smaller than the area of the other n-type impurity regions 68bn to 68dn when viewed from the direction perpendicular to the semiconductor substrate 60.

The areas of the 1 st diffusion region 67n and the 2 nd diffusion region 68an may be areas of portions of the 1 st diffusion region 67n and the 2 nd diffusion region 68an that do not overlap with the gate electrode 26e of the reset transistor 26 when viewed from the direction perpendicular to the semiconductor substrate. Similarly, the area of the other n-type impurity regions 68bn to 68dn may be an area of a portion of the other n-type impurity regions 68bn to 68dn that does not overlap with the gate electrode 22e of the amplifying transistor 22 and the gate electrode 24e of the address transistor 24 when viewed from the direction perpendicular to the semiconductor substrate 60. When viewed from a direction perpendicular to the semiconductor substrate 60, the portions that do not overlap the gate electrodes 22e, 24e, and 26e are less susceptible to damage during fabrication than the portions that overlap the gate electrodes 22e, 24e, and 26e of these transistors. Examples of the damage to be caused during the production include damage caused by plasma treatment used in the dry etching step and damage caused by ashing treatment when the resist is peeled off. Therefore, leakage current is less likely to occur in the portions overlapping the gate electrodes 22e, 24e, 26 e. Therefore, the reason why the area of the interface depletion layer is reduced is that the 1 st diffusion region 67n and the other n-type impurity regions 68bn to 68dn can be considered to be affected by the area of the portion that does not overlap with the gate electrode.

Further, by reducing the area of the 1 st diffusion region 67n, the distance between the contact hole h1 formed in the 1 st diffusion region 67n and the gate electrode 26e is smaller than the distance between the contact hole h2 formed in the 2 nd diffusion region 68an and the gate electrode 26e, for example. That is, when viewed from a direction perpendicular to the semiconductor substrate 60, the distance between the gate electrode 26e and the connection portion of the contact plug cp1 and the 1 st diffusion region 67n is smaller than the distance between the gate electrode 26e and the connection portion of the contact plug cp2 and the 2 nd diffusion region 68 an. As described above, since the 1 st diffusion region 67n has a low impurity concentration, the resistance value is higher than that of the 2 nd diffusion region 68 an. Accordingly, by decreasing the distance between the contact hole h1 and the gate electrode 26e, the current path in the 1 st diffusion region 67n is shortened, and therefore the resistance value in the 1 st diffusion region 67n is decreased. In addition, the distance between the contact hole h1 formed in the 1 st diffusion region 67n and the gate electrode 26e may be smaller than the distance between the contact holes h3 and h4 formed in the n-type impurity regions 68bn and 68dn and the gate electrodes 22e and 24e, similarly to the other n-type impurity regions 68bn and 68 dn. That is, the distance between the gate electrode 26e and the connection portion between the contact plug cp1 and the 1 st diffusion region 67n may be smaller than the distance between the gate electrode 22e and the connection portion between the contact plug cp3 and the n-type impurity region 68bn when viewed from the direction perpendicular to the semiconductor substrate 60. Further, the distance between the gate electrode 26e and the connection portion of the contact plug cp1 and the 1 st diffusion region 67n may be smaller than the distance between the gate electrode 24e and the connection portion of the contact plug cp4 and the n-type impurity region 68dn, when viewed from the direction perpendicular to the semiconductor substrate 60.

Modification 1

Fig. 5 is a diagram showing a circuit configuration of an image pickup apparatus 100B according to modification 1 of the present embodiment. The main difference between the pixel 10B shown in fig. 5 and the pixel 10A shown in fig. 2 is that the burn-in preventing transistor 28 is formed on the semiconductor substrate 60. Hereinafter, the point different from the embodiment will be mainly described, and detailed description of the common point will be omitted.

As shown in fig. 5, the charge accumulation node ND electrically connects the drain of the reset transistor 26, the gate of the amplifying transistor 22, the lower electrode of the photoelectric conversion portion 12, and the source and gate of the burn-preventing transistor 28. Here, the drain of the reset transistor 26 is the 1 st diffusion region 67n as a charge accumulation region. The source of the burn-preventing transistor 28 is connected to a VDD wiring or a power line 41 dedicated to the burn-preventing transistor 28. Here, if excessive light is incident into the photoelectric conversion film 12b, the potential of the 1 st diffusion region 67n may exceed VDD. By setting the threshold voltage of the burn-in prevention transistor 28 to be on when the potential of the 1 st diffusion region 67n is equal to VDD, excess charge can be discharged from the 1 st diffusion region 67n to the power supply line 41. As a result, a failure such as burn can be prevented.

Fig. 6 is a plan view showing a layout in the pixel 10B of modification 1 of the present embodiment. As shown in fig. 6, the pixel 10B in the present modification further includes a 3 rd transistor (here, burn-in preventing transistor 28) different from the 1 st transistor (here, reset transistor 26). The burn-preventing transistor 28 includes a gate electrode 28e, a source region, and a drain region. Here, the 1 st diffusion region 67n functions as a drain region of the burn-preventing transistor 28. The 1 st diffusion region 67n also functions as a drain region of the reset transistor 26. Thus, in the above 2 transistors, the 1 st diffusion region 67n is shared as a drain region. The n-type impurity region 68en functions as a source region of the burn-in preventing transistor 28.

Here, the concentration of the n-type impurity in the 1 st diffusion region 67n may be smaller than that in the n-type impurity region 68 en. Thus, the concentration of the n-type impurity in the 1 st diffusion region 67n becomes smaller than the concentrations of the n-type impurities in the other n-type impurity regions 68bn to 68ec in the pixel 10B. Accordingly, the bonding concentration between the 1 st diffusion region 67n and the semiconductor substrate 60 becomes small, and thus the leakage current can be reduced.

Fig. 7 is a schematic cross-sectional view of the device structure of the pixel of the present modification. As shown in fig. 7, the gate electrode 28e of the burn-in preventing transistor 28 is formed on the semiconductor substrate 60 via the gate insulating film 70. An n-type impurity region 68en is formed on the surface of the semiconductor substrate 60.

If excessive light is incident on the photoelectric conversion film 12b, the potential of the 1 st diffusion region 67n rises to the same extent as the bias applied to the transparent electrode 12 c. If such an overvoltage is applied to the 1 st diffusion region 67n, there is a possibility that the 1 st diffusion region 67n is broken or the gate insulating film 70 of the amplifying transistor 22 is broken. As a result, a failure such as burn occurs.

On the other hand, according to this modification, dark current can be suppressed, and even when excessive light is incident, malfunction of each transistor due to overvoltage can be prevented.

Modification 2

Fig. 8 is a plan view showing a layout in a pixel 10C in an image pickup device 100C according to modification 2 of the present embodiment. In the present modification, the 1 st diffusion region (FD) 67n is circular when viewed from a direction perpendicular to the semiconductor substrate 60, which is different from the pixel 10A. Hereinafter, the point different from the embodiment will be mainly described, and detailed description of the common point will be omitted.

In the present modification, as described above, the 1 st diffusion region (FD) 67n is circular when viewed from the direction perpendicular to the semiconductor substrate 60. Thus, the area of the surface of the semiconductor substrate 60 in the 1 st diffusion region 67n is smaller than that in the case of being formed in a rectangular shape. Therefore, in the surface of the semiconductor substrate 60, the area of the interfacial depletion layer formed at the junction of the 1 st diffusion region 67n and the semiconductor substrate 60 becomes small. Thereby, leakage current at the joint portion can be reduced.

In this modification, the burn-preventing transistor 28 is not provided as in the image pickup apparatus 100A according to the embodiment, but the burn-preventing transistor 28 may be provided as in the image pickup apparatus 100B according to modification 1. Thus, even if excessive light is incident on the photoelectric conversion portion 12, malfunction of each transistor due to overvoltage can be prevented.

Modification 3

Fig. 9 is a diagram showing a circuit configuration of a pixel 10D in an image pickup device 100D according to modification 3 of the present embodiment. Fig. 10 is a plan view showing a layout in the pixel 10D according to the present modification. In the above embodiments and modifications, the image pickup apparatus having the photoelectric conversion portion using the photoelectric conversion film was described as an example, but in the present modification, the image pickup apparatus using the photodiode as the photoelectric conversion portion is described as an example.

As shown in fig. 9 and 10, the pixel 10D of the present modification includes a photodiode 13 and a transfer transistor 27. The photodiode 13 has an n-type impurity region 68fn and a pinning layer (not shown) located above the n-type impurity region 68 fn. The pinning layer is a p-type impurity region. The photodiode 13 photoelectrically converts light received during the exposure time to generate electric charges. After the predetermined exposure time has elapsed, a transfer signal for turning on the transfer transistor 27 is applied to the gate of the transfer transistor 27 via the transfer signal line 37. Thereby, the transfer transistor 27 is turned on, and the charge generated by the photodiode 13 is transferred to the charge storage node ND. The amplifying transistor 22 outputs a signal corresponding to the charge transferred to the charge accumulation node ND to the vertical signal line 35 (not shown). The signal output to the vertical signal line 35 is supplied to an AD converter (not shown) to be AD-converted.

As shown in fig. 10, the transfer transistor 27 includes a 1 st diffusion region 67n and an n-type impurity region 68fn as a source and a drain. Further, the transfer transistor 27 includes a gate electrode 27e. The transfer transistor 27 shares the 1 st diffusion region 67n as one of a source and a drain with the reset transistor 26.

As shown in fig. 9, the charge accumulation node ND electrically connects the drain of the reset transistor 26 and the gate of the amplifying transistor 22 with the source of the transfer transistor 27. Here, the drain of the reset transistor 26 in fig. 10 is the 1 st diffusion region 67n as a charge accumulation region.

In this modification, the pixel 10D includes the 1 st transistor (here, the reset transistor 26) as in the above embodiment and modification. The 1 st transistor is located on the semiconductor substrate and contains an n-type impurity, and includes a 1 st diffusion region 67n for accumulating the photo-charges converted by the photodiode 13 as one of a source and a drain, and a 2 nd diffusion region 68an as an n-type impurity region containing the n-type impurity as the other of the source and the drain. At this time, the concentration of the n-type impurity of the 1 st diffusion region 67n is smaller than that of the 2 nd diffusion region 68 an. Thus, the bonding concentration at the bonding portion of the 1 st diffusion region 67n and the semiconductor substrate becomes small, so that the leakage current in the 1 st diffusion region 67n is reduced.

Further, the pixel 10D includes a 2 nd transistor (here, the amplifying transistor 22) different from the reset transistor 26, and the 2 nd transistor includes a 3 rd diffusion region (hereinafter, referred to as other n-type impurity regions 68bn and 68 cn) containing an n-type impurity in the semiconductor substrate 60 as a source or a drain. At this time, the concentration of the n-type impurity in the 1 st diffusion region 67n may be smaller than the concentrations of the n-type impurities in the other n-type impurity regions 68bn and 68 cn. At this time, the concentration of the n-type impurity in the 1 st diffusion region 67n may be at least 1/10 or less than 1/15 of the concentration of the n-type impurity in the 2 nd diffusion region 68an and the other n-type impurity regions 68bn and 68 cn. Accordingly, the bonding concentration at the bonding portion between the 1 st diffusion region 67n and the semiconductor substrate 60 becomes small, so that the electric field strength at the bonding portion can be relaxed. Therefore, leakage current from the 1 st diffusion region 67n as the charge accumulation region or toward the 1 st diffusion region 67n is reduced.

In the imaging device 100D according to the present modification, the semiconductor substrate 60 contains p-type impurities, and the concentrations of the n-type impurities contained in the 1 st diffusion region 67n and the p-type impurities contained in the portion of the semiconductor substrate 60 adjacent to the 1 st diffusion region 67n may be 1×10 ¹⁶ atoms/cm ³ Above 5×10 ¹⁶ atoms/cm ³ The following is given. As a result, the bonding concentration between the 1 st diffusion region 67n and the semiconductor substrate 60 becomes small, and an increase in the electric field strength at the bonding portion can be suppressed. Therefore, leakage current at the junction can be reduced.

Further, if the area of a depletion layer region (hereinafter, referred to as an interface depletion layer) formed at the junction of the surface of the semiconductor substrate 60 increases, the leakage current tends to increase. Therefore, it is desirable to minimize the area of the interface depletion layer exposed on the surface of the semiconductor substrate 60. In order to reduce the area of the interface depletion layer, the area of the 1 st diffusion region 67n may be smaller than the 2 nd diffusion region 68an when viewed from the direction perpendicular to the semiconductor substrate 60. For example, the area of the 1 st diffusion region 67n may be 1/2 or less of the area of the 2 nd diffusion region 68an when viewed from the direction perpendicular to the semiconductor substrate 60. In this case, the width of the 1 st diffusion region 67n in the channel width direction may be 1/2 or less of the width of the 2 nd diffusion region 68an in the channel width direction. The 1 st diffusion region 67n and the 2 nd diffusion region 68an may have the same width in the channel width direction and the same length in the channel length direction. In addition, as for the other n-type impurity regions 68bn and 68cn in the pixel 10D, the area of the 1 st diffusion region 67n may be formed smaller than the area of the other n-type impurity regions 68bn and 68cn when viewed from the direction perpendicular to the semiconductor substrate 60.

The areas of the 1 st diffusion region 67n and the 2 nd diffusion region 68an may be areas of portions of the 1 st diffusion region 67n and the 2 nd diffusion region 68an that do not overlap with the gate electrode 26e of the reset transistor 26 when viewed from the direction perpendicular to the semiconductor substrate. Similarly, the areas of the other n-type impurity regions 68bn and 68cn may be areas of portions of the other n-type impurity regions 68bn and 68cn that do not overlap with the gate electrode 22e of the amplifying transistor 22 when viewed from the direction perpendicular to the semiconductor substrate 60. When viewed from a direction perpendicular to the semiconductor substrate 60, portions that do not overlap the gate electrodes 22e and 26e are less susceptible to damage during fabrication than portions that overlap the gate electrodes 22e and 26e of these transistors. Examples of the damage to be caused during the production include damage caused by plasma treatment used in the dry etching step and damage caused by ashing treatment when the resist is peeled off. Therefore, leakage current is less likely to occur in the portion overlapping the gate electrodes 22e and 26 e. Therefore, the reason why the area of the interface depletion layer is reduced is that the 1 st diffusion region 67n and the other n-type impurity regions 68bn and 68dn can be considered to be affected by the area of the portion that does not overlap with the gate electrode.

Further, by making the area of the 1 st diffusion region 67n smaller, the distance between the contact hole h1 formed in the 1 st diffusion region 67n and the gate electrode 26e is smaller than, for example, the distance between the contact hole h2 formed in the 2 nd diffusion region 68an and the gate electrode 26 e. As described above, since the 1 st diffusion region 67n has a low impurity concentration, the resistance value becomes higher than that of the 2 nd diffusion region 68 an. Accordingly, by decreasing the distance between the contact hole h1 and the gate electrode 26e, the current path in the 1 st diffusion region 67n is shortened, and therefore the resistance value in the 1 st diffusion region 67n is decreased. In addition, as for the other n-type impurity regions 68bn and 68cn, the distance between the gate electrode 26e and the contact hole h1 formed in the 1 st diffusion region 67n may be smaller than the distance between the gate electrode 22e and the contact holes h3 and h9 formed in the n-type impurity regions 68bn and 68 cn.

The imaging device according to the present disclosure has been described above based on the embodiments and the modifications, but the present disclosure is not limited to the embodiments and the modifications. Various modifications of the embodiments and modifications as will occur to those skilled in the art, or other modifications constructed by combining some of the constituent elements of the embodiments and modifications are also included in the scope of the present disclosure, as long as they do not depart from the gist of the present disclosure.

Further, according to the embodiments and modifications of the present disclosure, since the influence due to the leakage current can be reduced, an image pickup apparatus capable of performing image pickup with high image quality is provided. The amplifying transistor 22, the address transistor 24, the reset transistor 26, and the burn-preventing transistor 28 may be an N-channel MOS or a P-channel MOS. In the case where each transistor is a P-channel MOS, the impurity of the 1 st conductivity type is a P-type impurity, and the impurity of the 2 nd conductivity type is an n-type impurity. Nor is it necessary to unify all of these transistors to be of some kind of N-channel MOS or P-channel MOS. When the transistors in the pixel are each used as an N-channel MOS and as a signal charge, the source and drain of each of the transistors may be replaced with each other.

Industrial applicability

According to the present disclosure, an image pickup apparatus capable of performing image pickup with high image quality while suppressing an influence due to dark current is provided. The imaging apparatus of the present disclosure is useful, for example, for an image sensor, a digital camera, and the like. The imaging device of the present disclosure can be used in a medical camera, a robot camera, a security camera, a camera mounted in a vehicle and used, and the like.

Description of the reference numerals

10A, 10B, 10C, 10D pixels

12. Photoelectric conversion unit

13. Photodiode having a high-k-value transistor

14. Signal detection circuit

16. Feedback circuit

22. Amplifying transistor

22e, 24e, 26e, 27e, 28e gate electrodes

24. Address transistor

26. Reset transistor

27. Transfer transistor

28. Burn-preventing transistor

32. Power supply wiring

35. Vertical signal line

36. Reset signal line

40. Peripheral circuit

42. Load circuit

44. Column signal processing circuit

48. Horizontal signal reading circuit

50. Inverting amplifier

53. Feedback line

60. Semiconductor substrate

61. Support substrate

61p, 63p, 65p p semiconductor layer

62n n type semiconductor layer

64 p-type region

66p p type impurity region

67a zone 1

67b region 2

67n 1 st diffusion region

68an No. 2 diffusion region

68bn, 68cn, 68dn, 68en, 68fn n-type impurity regions

69. Element separation region

70. 71, 72, 90a, 90b, 90c, 90d insulating layer

80. Wiring structure

80a, 80b, 80c, 80d wiring layers

90. Interlayer insulating layer

100A, 100B, 100C, 100D imaging device

R1 imaging region

R2 peripheral region

cp1, cp2, cp3, cp4, cp5, cp6, cp7, cp8 contact plug

h1 Contact holes of h2, h3, h4, h5, h6, h7, h8, h9

pa1, pa2, pb, pc, pd plug

Claims

1. An image pickup apparatus, characterized in that,

the device is provided with:

a semiconductor substrate including a 1 st diffusion region containing an impurity of a 1 st conductivity type and a 2 nd diffusion region containing an impurity of a 1 st conductivity type; and

a plurality of pixels;

the plurality of pixels each include:

a photoelectric conversion unit that converts light into electric charges; and

a 1 st transistor including a source electrode, a drain electrode, and a gate electrode, wherein the 1 st diffusion region for accumulating at least a part of the electric charge is one of the source electrode and the drain electrode, and the 2 nd diffusion region is the other of the source electrode and the drain electrode;

the concentration of the 1 st conductive type impurity in the 1 st diffusion region is lower than the concentration of the 1 st conductive type impurity in the 2 nd diffusion region;

the 1 st diffusion region has a smaller area than the 2 nd diffusion region when viewed from a direction perpendicular to the semiconductor substrate.

2. The image pickup apparatus according to claim 1, wherein,

the semiconductor substrate further includes a 3 rd diffusion region containing an impurity of the 1 st conductivity type;

each of the plurality of pixels includes a 2 nd transistor including the 3 rd diffusion region as one of a source and a drain;

The concentration of the 1 st conductive type impurity in the 1 st diffusion region is lower than the concentration of the 1 st conductive type impurity in the 3 rd diffusion region.

3. The image pickup apparatus according to claim 1, wherein,

the plurality of pixels each include a 3 rd transistor including the 1 st diffusion region as one of a source and a drain.

4. The image pickup apparatus according to claim 1, wherein,

the area of the 1 st diffusion region is an area of a portion of the 1 st diffusion region that does not overlap with the gate electrode when viewed from a direction perpendicular to the semiconductor substrate;

the area of the 2 nd diffusion region is an area of a portion of the 2 nd diffusion region that does not overlap with the gate electrode when viewed from a direction perpendicular to the semiconductor substrate.

5. The image pickup apparatus according to claim 1, wherein,

the plurality of pixels each include:

a 1 st plug connected to a 1 st portion of the 1 st diffusion region; and

a 2 nd plug connected to a 2 nd portion of the 2 nd diffusion region;

the distance between the 1 st portion and the gate electrode is smaller than the distance between the 2 nd portion and the gate electrode when viewed from a direction perpendicular to the semiconductor substrate.

6. The image pickup apparatus according to claim 1, wherein,

the semiconductor substrate includes a 4 th diffusion region containing an impurity of a 2 nd conductivity type different from the 1 st conductivity type;

the plurality of pixels each include a transistor other than the 1 st transistor, and include the 4 th diffusion region as a separation region for separating the 1 st transistor from the other transistors;

the 4 th diffusion region is not in contact with the 1 st diffusion region in the surface of the semiconductor substrate.

7. The image pickup apparatus according to claim 1, wherein,

the semiconductor substrate contains impurities of a 2 nd conductivity type different from the 1 st conductivity type;

the concentration of the impurity of the 1 st conductivity type contained in the 1 st diffusion region is 1×10 ¹⁶ atoms/cm ³ Above and 5×10 ¹⁶ atoms/cm ³ The following are set forth;

the concentration of the impurity of the 2 nd conductivity type contained in the portion adjacent to the 1 st diffusion region in the semiconductor substrate is 1×10 ¹⁶ atoms/cm ³ Above and 5×10 ¹⁶ atoms/cm ³ The following is given.

8. The image pickup apparatus according to claim 1, wherein,

the 1 st diffusion region is circular when viewed from a direction perpendicular to the semiconductor substrate.

9. An image pickup apparatus, characterized in that,

The device is provided with:

a plurality of pixels;

the plurality of pixels each include:

a photoelectric conversion unit that converts light into electric charges;

a 1 st plug connected to a 1 st portion of the 1 st diffusion region; and

a 2 nd plug connected to a 2 nd portion of the 2 nd diffusion region;