CN109300903A - The three heap memory structures and manufacturing method stacked based on through silicon via - Google Patents
The three heap memory structures and manufacturing method stacked based on through silicon via Download PDFInfo
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- CN109300903A CN109300903A CN201811140666.1A CN201811140666A CN109300903A CN 109300903 A CN109300903 A CN 109300903A CN 201811140666 A CN201811140666 A CN 201811140666A CN 109300903 A CN109300903 A CN 109300903A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
Abstract
Disclose a kind of three heap memory structures stacked based on through silicon via, comprising: cmos circuit includes the first silicon substrate and the first insulating layer on the first silicon substrate, has multiple first external pads in the first insulating layer；Memory cell array includes the second silicon substrate and the second insulating layer on the second silicon substrate, has multiple second external pads in second insulating layer；Cmos circuit further includes the through silicon via through the first insulating layer and the first silicon substrate, is electrically connected with the first external pads；First silicon substrate is in contact with each other with second insulating layer, and through silicon via is bonded with the second external pads, to realize the electrical connection between cmos circuit and memory cell array.The embodiment of the present invention forms through silicon via on cmos circuit, the first external pads connection in the first end and cmos circuit of through silicon via, second end is bonded to realize electrical connection between the two with the second external pads of memory cell array, to improve storage density, reduces wiring density.
Description
Technical field
The present invention relates to memory technology fields, in particular to the three heap memory structures and manufacture stacked based on through silicon via
Method.
Background technique
The raising of the storage density of memory device and the progress of semiconductor fabrication process are closely related.With semiconductors manufacture
The aperture of technique is smaller and smaller, and the storage density of memory device is higher and higher.In order to further increase storage density, develop
The memory device (that is, three-dimensional memory structure) of three-dimensional structure out.Three-dimensional memory structure includes stacking along vertical direction
Multiple storage units can double up integrated level on the chip of unit area, and can reduce cost.
In the three-dimensional memory structure of NAND structure, one is being initially formed cmos circuit, then on cmos circuit
Form memory cell array.Many of technique due to memory cell array high-temperature technology, to the electrical property of cmos device and can
There is very big influence by property, and process cycle is also longer.
Another kind is to form cmos circuit using semiconductor substrate, forms memory cell array using laminated construction, this is folded
Layer structure includes the grid conductor of selection transistor and memory transistor, and then cmos circuit is bonded in memory cell array
Side.In the three-dimensional memory structure, biggish chip face is occupied through array contact (Through Array Contact)
Product, so that the area of nucleus becomes smaller, to reduce storage density；In addition, providing CMOS electricity using a large amount of metal lines
Being electrically connected between road and memory cell array, the increase of wiring density will will affect the yield of three-dimensional memory structure and reliable
Property.
It is expected that the structure and its manufacturing method of three-dimensional memory structure are further improved, to improve three-dimensional memory structure
Storage density.
Summary of the invention
In view of the above problems, the purpose of the present invention is to provide it is a kind of based on through silicon via stack three heap memory structures and
Manufacturing method, wherein through silicon via is formed on cmos circuit, outside first in the first end and cmos circuit of the through silicon via
Pad connection, second end are bonded to realize cmos circuit and the storage unit battle array with the second external pads of memory cell array
Electrical connection between column reduces wiring density to improve storage density.
According to an aspect of the present invention, a kind of three heap memory structures stacked based on through silicon via are provided, comprising: CMOS electricity
Road, the first insulating layer including the first silicon substrate and on first silicon substrate have in first insulating layer more
A first external pads；Memory cell array, the second insulation including the second silicon substrate and on second silicon substrate
Layer, there are multiple second external pads in the second insulating layer；Wherein, the cmos circuit further includes through the first insulating layer
With the through silicon via of the first silicon substrate, the first end of the through silicon via is electrically connected with first external pads, and second end is described
The bottom-exposed of first silicon substrate；The second insulating layer of first silicon substrate of the cmos circuit and the memory cell array that
This contact, the through silicon via is coupled with second external pads, to realize the cmos circuit and the storage unit battle array
Electrical connection between column.
Preferably, the cmos circuit includes the first wiring layer, and the memory cell array includes the second wiring layer, described
First wiring layer and second wiring layer are laterally extended.
Preferably, the through silicon via is electrically connected by the first wiring layer with first external pads.
Preferably, the cmos circuit includes multiple first conductive channels, is used to provide the described multiple first external pads
Electrical connection each other；The memory cell array includes multiple second conductive channels, is used to provide the described outside multiple second
Electrical connection between portion's pad.
Preferably, the through silicon via includes metal layer and glue-line and/or barrier layer.
Preferably, the cmos circuit further include: multiple transistors in first silicon substrate；Positioned at described
The multiple contact pads being connected in two insulating layers and with multiple transistors；First external pads and first conduction
Channel is located in first insulating layer；The multiple contact pad is via the multiple first external pads and the multiple
One conductive channel is connected to the corresponding through silicon via.
Preferably, the memory cell array further include: the public source zone in second silicon substrate；Positioned at described
Rhythmic structure of the fence on second silicon substrate, the rhythmic structure of the fence include the grid conductor of many levels；Through the gate stack
Multiple channel columns of structure；Multiple contact pads on the rhythmic structure of the fence；Wherein, the first of the multiple channel column
End extends to public source zone, and second end is connected to corresponding contact pad, and the grid conductor of the multiple level is respectively connected to
Corresponding contact pad；Second insulating layer is covered on the rhythmic structure of the fence；Second external pads and described second are led
Electric channel is located in the second insulating layer.
Preferably, the memory cell array further include: at least one through the second insulating layer is additional conductive logical
The first end in road, at least one additional conductive channel extends to the public source zone, and second end is connected to corresponding contact
Pad.
According to another aspect of the present invention, a kind of manufacturing method of three-dimensional memory structure is provided, comprising: form CMOS electricity
Road, the cmos circuit include the first silicon substrate and the first insulating layer on first silicon substrate, and described first absolutely
There are multiple first external pads in edge layer；Form the through silicon via for running through the first insulating layer and the first silicon substrate, the through silicon via
First end be electrically connected with first external pads, bottom-exposed of the second end in first silicon substrate；It is single to form storage
Element array, the memory cell array include the second silicon substrate and the second insulating layer on second silicon substrate, institute
Stating has multiple second external pads in second insulating layer；The cmos circuit and the memory cell array are bonded to described
Three-dimensional memory structure, wherein the second insulating layer of the first silicon substrate of the cmos circuit and the memory cell array that
This contact, the through silicon via is bonded with second external pads, to realize the cmos circuit and the storage unit battle array
Electrical connection between column.
Preferably, formation runs through the first insulating layer and the through silicon via of the first silicon substrate includes:
First insulating layer is etched to form groove, the groove extends to inside first silicon substrate；
It is sequentially depositing glue-line and/or barrier layer, metal layer in the groove；
The first end of the through silicon via is electrically connected with first external pads；
Reduction processing is carried out with the second end of the exposure through silicon via to first silicon substrate.
The three heap memory structures and manufacturing method provided by the invention stacked based on through silicon via, are formed on cmos circuit
Through silicon via, the first external pads connection in the first end and cmos circuit of the through silicon via, second end and memory cell array
The second external pads be bonded to realize the electrical connection between cmos circuit and the memory cell array.The three-dimensional storage knot
Without running through array contact (TAC) structure in structure, the area of memory cell array is saved, storage density is provided；In addition,
The two sides of cmos circuit are all routed, and wiring density is reduced.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings:
Fig. 1 a and Fig. 1 b respectively illustrate the circuit diagram and structural schematic diagram of the memory cell string of three-dimensional memory structure；
Fig. 2 a and 2b be shown respectively the internal structure of three-dimensional memory structure according to an embodiment of the present invention perspective view and
Overall perspective；
Fig. 3 shows three-dimensional memory structure sectional view according to an embodiment of the present invention；
Fig. 4 a to Fig. 4 i shows cutting for each stage of three-dimensional memory structure manufacturing method according to an embodiment of the present invention
Face figure.
Specific embodiment
The various embodiments that the present invention will be described in more detail that hereinafter reference will be made to the drawings.In various figures, identical element
It is indicated using same or similar appended drawing reference.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.
With reference to the accompanying drawings and examples, specific embodiments of the present invention will be described in further detail.
" top " described in the present invention refers to positioned at the top of base plan, can refer to directly connecing between material
Touching is also possible to interval setting.
In this application, term " semiconductor structure " refers to that is formed in each step of manufacture memory device entirely partly leads
The general designation of body structure, including all layers formed or region.Many specific details of the invention are described hereinafter,
Such as structure, material, size, treatment process and the technology of device, to be more clearly understood that the present invention.But as this field
Technical staff it will be appreciated that as, can not realize the present invention according to these specific details.
The present invention can be presented in a variety of manners, some of them example explained below.
The circuit diagram and structural schematic diagram of the memory cell string of three-dimensional memory structure is shown respectively in Fig. 1 a and 1b.In the reality
Apply the situation that memory cell string shown in example includes 4 storage units.It is appreciated that the invention is not limited thereto, storage unit
Number of memory cells in string can be it is any number of, for example, 32 or 64.
As shown in Figure 1a, the first end of memory cell string 100 is connected to bit line BL, and second end is connected to source electrode line SL.It deposits
Storage unit string 100 includes the multiple transistors being connected in series between the first end and a second end, comprising: first choice transistor
Q1, storage unit M1 to M4 and the second selection transistor Q2.The grid of first choice transistor Q1 is connected to string selection line
The grid of SSL, the second selection transistor Q2 are connected to the ground selection line GSL.The grid of storage unit M1 to M4 is respectively connected to word
The respective word of line WL1 to WL4.
As shown in Figure 1 b, the selection transistor Q1 and Q2 of memory cell string 100 respectively include the second conductor layer 122 and third
Conductor layer 123, storage unit M1 to M4 respectively include the first conductor layer 121.First conductor layer 121, the second conductor layer 122 and
Three conductor layers 123 are consistent with the stacking order of transistor in memory cell string 100, each other using exhausted between adjacent conductor layer
Edge layer separates, to form rhythmic structure of the fence.
Further, memory cell string 100 includes storage string 110.Storage string 110 is adjacent with rhythmic structure of the fence or runs through
Rhythmic structure of the fence.Tunneling medium layer is accompanied between the middle section of storage string 110, the first conductor layer 121 and channel layer 111
112, charge storage layer 113 and gate dielectric layer 114, to form storage unit M1 to M4.At the both ends of storage string 110, second
Gate dielectric layer 114 is accompanied between conductor layer 122 and 123 and channel layer 111, to form the choosing of first choice transistor Q1 and second
Select transistor Q2.
Channel layer 111 is for example made of DOPOS doped polycrystalline silicon, and tunneling medium layer 112 and gate dielectric layer 114 are respectively by oxide
Composition, such as silica, charge storage layer 113 is made of the insulating layer comprising quantum dot or nanocrystal, such as includes gold
The silicon nitride of the particle of category or semiconductor, the first conductor layer 121, the second conductor layer 122 and third conductor layer 123 are by metal group
At, such as tungsten.Channel layer 111 is used to provide selection transistor and control the channel region of transistor, the doping type of channel layer 111
It is identical as selection transistor and the control type of transistor.For example, selection transistor and control transistor for N-type, channel
Layer 111 can be the polysilicon of n-type doping.
In this embodiment, the core of storage string 110 is channel layer 111, tunneling medium layer 112,113 and of charge storage layer
Gate dielectric layer 114 forms the laminated construction for surrounding core wall.In alternate embodiments, the core of storage string 110 is additional
Insulating layer, channel layer 111, tunneling medium layer 112, charge storage layer 113 and gate dielectric layer 114 are formed around semiconductor layer
Laminated construction.
In this embodiment, first choice transistor Q1 and the second selection transistor Q2, storage unit M1 to M4 are used public
Total channel layer 111 and gate dielectric layer 114.In storage string 110, channel layer 111 provides the source-drain area and ditch of multiple transistors
Channel layer.In alternate embodiments, step independent of one another can be used, the choosing of first choice transistor Q1 and second is respectively formed
Select the semiconductor layer of transistor Q2 and the semiconductor layer and gate dielectric layer of gate dielectric layer and storage unit M1 to M4.In storage string
In 110, the semiconductor layer of first choice transistor Q1 and the second selection transistor Q2 and the semiconductor layer of storage unit M1 to M4
It is electrically connected to each other.
In write operation, memory cell string 100 writes data into storage unit M1 into M4 using FN tunneling efficiency
Selected memory cell.By taking storage unit M2 as an example, while source electrode line SL ground connection, ground selection line GSL is biased to about zero volt
Voltage, so that the second selection transistor Q2 for corresponding to ground selection line GSL is disconnected, string selection line SSL is biased to high voltage VDD,
So that corresponding to the selection transistor Q1 conducting of string selection line SSL.Further, bit line BIT2 is grounded, and wordline WL2 is offset to volume
Journey voltage VPG, such as 20V or so, remaining wordline is offset to low-voltage VPS1.Due to only having the wordline of selected memory cell M2 electric
Pressure is higher than tunneling voltage, and therefore, the electronics of the channel region of storage unit M2 reaches charge storage via tunneling medium layer 112
Layer 113, so that data are transformed into charge storage in the charge storage layer 113 of storage unit M2.
In read operation, the conducting shape of selected memory cell of the memory cell string 100 according to storage unit M1 into M4
State judges the quantity of electric charge in charge storage layer, to obtain the data of quantity of electric charge characterization.By taking storage unit M2 as an example, wordline
WL2, which is offset to, reads voltage VRD, remaining wordline is offset to high voltage VPS2.The on state of storage unit M2 and its threshold value electricity
Pressure is related, i.e., related to the quantity of electric charge in charge storage layer, to may determine that data according to the on state of storage unit M2
Value.Storage unit M1, M3 and M4 are in the conductive state always, and therefore, it is single that the on state of memory cell string 100 depends on storage
The on state of first M2.Control circuit judges the conducting of storage unit M2 according to the electric signal detected on bit line BL and source electrode line SL
State, to obtain the data stored in storage unit M2.
Fig. 2 a and 2b be shown respectively the internal structure of three-dimensional memory structure according to an embodiment of the present invention perspective view and
Overall perspective, Fig. 3 show three-dimensional memory structure sectional view according to an embodiment of the present invention.
For the sake of clarity, the internal structure of three-dimensional memory structure is only shown in fig. 2 a, wherein it is single that storage is not shown
The semiconductor substrate of element array and the insulating layer in cmos circuit and memory cell array only show 3D storage in figure 2b
The external structure of device.
The three-dimensional memory structure 200 shown in this embodiment includes cmos circuit 210 and memory cell array 220,
The cmos circuit 210 is stacked to 220 top of memory cell array.
Cmos circuit 210 includes the first silicon substrate 201, multiple contact pads on first silicon substrate 201
261, multiple first wiring layers 263 on multiple contact pads 261, multiple on multiple first wiring layers 263
One external pads 264 and the conductive channel 262 of interconnection is provided on the direction on the surface perpendicular to the first silicon substrate 201.?
In the present embodiment, the first insulating layer 202 is interlayer insulating film.Although being not shown, it being understood, however, that in the first silicon substrate 201
In be formed with multiple transistors.Between multiple first wiring layers 263 and multiple first wiring layers 263 and contact pad
261 and first are separated from each other between external pads 264 using interlayer insulating film, and logical using the conduction through interlayer insulating film
Road 262 is electrically connected to each other.Interlayer insulating film is not shown in fig. 2 a.
Cmos circuit 210 further includes the through silicon via 265 through the first insulating layer 202 and the first silicon substrate 201, and the silicon is logical
The first end in hole 265 is electrically connected with first external pads 264, bottom-exposed of the second end in first silicon substrate 201.
In cmos circuit 210, contact pad 261 is electrically connected with the transistor in the first silicon substrate 201, the contact pad
261 are connected to the first wiring layer 263 via conductive channel 262, are then connected to the first external pads via conductive channel 262
264；First external pads 264 are connected to through silicon via 265 via conductive channel 262 and the first wiring layer 263.The through silicon via
265 provide the electrical connection between the transistor and memory cell array 220 inside cmos circuit 210.
Memory cell array 220 includes that 4*3 amounts to 12 memory cell strings, and each memory cell string includes that 4 storages are single
Member, to form the memory array that 4*4*3 amounts to 48 storage units.It is appreciated that the invention is not limited thereto, three-dimensional storage
Device structure may include any number of memory cell strings, for example, 1024, the number of memory cells in each memory cell string can
Think it is any number of, for example, 32 or 64.
Memory cell array 220 includes the second silicon substrate 101, the rhythmic structure of the fence on the second silicon substrate 101, runs through
Channel column 110, the interconnection structure on rhythmic structure of the fence of rhythmic structure of the fence.The interconnection structure includes multiple second conductive logical
Road 161, the multiple contact pads 162 contacted respectively with multiple second conductive channels 161, on multiple contact pads 162
Multiple second wiring layers 164, multiple second external pads 165 on multiple second wiring layers 164 and perpendicular to
The conductive channel 163 of interconnection is provided on the direction on the surface of two silicon substrates 101.Rhythmic structure of the fence for example including grid conductor 121,
122 and 123.Multiple grid conductors in rhythmic structure of the fence for example formed it is step-like, for provide the second conductive channel 161 extend
Reach the space of corresponding grid conductor.
In memory cell array 220, memory cell string respectively includes respective channel column 110 and public grid
Conductor 121,122 and 123.Grid conductor 121,122 and 123 is consistent with the stacking order of transistor in memory cell string 100,
It is separated each other using interlayer insulating film between adjacent grid conductor, to form rhythmic structure of the fence.Layer is not shown in fig. 2 a
Between insulating layer.
In this embodiment, the internal structure of channel column 110 is as shown in Figure 1 b, is no longer described in detail herein.Channel
Column 110 runs through rhythmic structure of the fence, and is arranged in array.Semiconductor substrate is located above rhythmic structure of the fence, is formed with public affairs
Common source area (not shown).The first end of channel column 110 is commonly connected to public source zone, the second end of channel column 110 via
Conductive channel and wiring are connected to corresponding second external pads 165.The effect of conductive channel and wiring layer herein and bit line
BL is identical.
The grid conductor 122 of first choice transistor Q1 is divided into difference by grid line gap (gate line slit) 151
Grid line.Grid line with multiple channel columns 110 of a line is connected to outside corresponding second via conductive channel and wiring respectively
Pad 165.For the sake of clarity, in a part of conductive channel being not shown in the figure between grid conductor 122 and contact pad and
Wiring layer.The effect of conductive channel and wiring layer herein is identical as string selection line SSL.
The grid conductor 121 of memory transistor M1 and M4 are respectively connected to corresponding wordline.If memory transistor M1 and
The grid conductor 121 of M4 is divided into different grid lines by grid line gap 151, then the grid line of same level is respectively via conductive channel
Corresponding second external pads 165 are connected to wiring.For the sake of clarity, be not shown in the figure grid conductor 121 with contact
A part of conductive channel and wiring layer between pad.The effect of conductive channel and wiring layer herein and wordline WL1 to WL4 phase
Together.
The grid conductor of second selection transistor Q2 links into an integrated entity.If the grid conductor of the second selection transistor Q2
123 are divided into different grid lines by grid line gap 151, then grid line is connected to corresponding second via conductive channel and wiring respectively
External pads 165.The effect of conductive channel and wiring layer herein is identical as ground selection line GSL.
It preferably, in this embodiment can also include false channel column 130, the inside of false channel column 130 and channel column 110
Structure can be identical, and at least across at least part grid conductor in rhythmic structure of the fence.However, false channel column 130 is not
It is connected with the second external pads 165, so that mechanical support effect is provided solely for, without being used to form selection transistor and depositing
Store up transistor.Therefore, false channel column 130 does not form effective storage unit.
Preferably, in this embodiment can also include conductive channel 141 and insulation lining 142, and with gate stack knot
It is insulated from each other by insulation lining 142 between structure.The first end of conductive channel 141 extends to the semiconductor substrate above gate stack
In, public source zone is reached, second end is connected to wiring layer.The effect of conductive channel and wiring layer herein is identical as source line GL.
After forming cmos circuit 210 and memory cell array 220, the two is bonded to three-dimensional memory structure 200.
B referring to fig. 2, three-dimensional memory structure 200, the conductive channel and wiring layer of cmos circuit 210 are located at extremely according to this embodiment
In few first insulating layer 202, the conductive channel and wiring layer of memory cell array 220 are located at least one second insulating layer
In 102.Cmos circuit 210 and the bonding surface of memory cell array 220 are respectively the first silicon substrate 201 and second insulating layer
102 surfaces opposite to each other.Further, outside the through silicon via 265 of cmos circuit 210 and the second of memory cell array 220
The exposure on corresponding bonding surface respectively of pad 165, and it is positioned opposite to each other.Therefore, by cmos circuit 210 and storage
When cell array 220 is bonded to three-dimensional memory structure 200, the through silicon via 265 and memory cell array 220 of cmos circuit 210
The second external pads 165 be in contact with each other, to realize being electrically connected between cmos circuit 210 and memory cell array 220.
A large amount of wirings of cmos circuit 210 and memory cell array 220 are located near respective bonding surface.
Fig. 4 a to Fig. 4 g shows cutting for each stage of three-dimensional memory structure manufacturing method according to an embodiment of the present invention
Face figure, wherein Fig. 4 a to Fig. 4 d shows the manufacturing step of cmos circuit, and Fig. 4 e and Fig. 4 f show the manufacture step of memory cell array
Suddenly, Fig. 4 g shows being bonded for CMOS and memory cell array.The sectional view is intercepted along the AA line in Fig. 2 a.
This method starts from the semiconductor that the transistor (not shown) of cmos circuit is formed in the first silicon substrate 201
Structure, in this embodiment, the first silicon substrate 201 are, for example, monocrystalline substrate.In order to form transistor, in the first silicon substrate
Multiple doped regions are formed in 201.For example, the first silicon substrate 201 includes source region and the drain region of multiple transistors.
As shown in fig. 4 a, interconnection architecture is formed on first silicon substrate 201.
It is cmos circuit 210 in the semiconductor structure that the step is formed, wherein formed in the first silicon substrate 201 more
The doped region of a transistor provides external electrical connections via interconnection structure.
Interconnection structure includes the multiple contact pads 261 being located on the first silicon substrate 201, is located at multiple contact pads 261
On multiple wiring layers 263, multiple first external pads 264 on multiple wiring layers 263 and perpendicular to the first silicon
The conductive channel 262 of interconnection is provided on the direction on the surface of substrate 201.It is between multiple first wiring layers 263 and multiple
It is separated from each other between first wiring layer 263 and contact pad 261 and the first external pads 264 using the first insulating layer 202, and
It is electrically connected to each other using the conductive channel 262 in the first insulating layer 202.
As shown in Figure 4 b, it is formed in cmos circuit 210 through the first insulating layer 202 and extends to the first silicon substrate 201
Internal groove 266.
In this step, photoresist exposure mask is formed such as on the surface of the first insulating layer 202, then carry out it is each to
Anisotropic etch forms through silicon via 266 in the first insulating layer 202.Anisotropic etching can use dry etching, such as ion beam milling
Etching, plasma etching, reactive ion etching, laser ablation.For example, by control etching period, so that being etched in first absolutely
Stop at a certain distance from the interior surface of edge layer 202.After the etching by dissolving or being ashed removal photoresist in a solvent
Agent mask.
As illustrated in fig. 4 c, glue-line and/or barrier layer and metal layer are sequentially depositing in groove 266 to form through silicon via 265.
In the present embodiment, glue-line is for example made of Ti/TiN.Barrier layer 265a is for example made of Ti/TiN.Metal layer
265b is for example made of tungsten.Using atomic layer deposition (ALD) deposited metal layer, the forerunner source used in atomic layer deposition is for example
It is tungsten hexafluoride WF6, the reducing gas of use is, for example, silane SiH4 or diborane B2H6.In the atomic layer deposition the step of,
Tungsten material, which is obtained, using the chemisorption of tungsten hexafluoride WF6 and the reaction product of silane SiH4 realizes deposition process.
As shown in figure 4d, the first end of through silicon via 265 is electrically connected with the first external pads 264.
Specifically, the first wiring layer 263 is formed on the first insulating layer 202, so that through silicon via 265 and the first external pads
264 electrical connections, and a protective layer is covered above the first wiring layer 263.
As shown in fig 4e, reduction processing is carried out to expose through silicon via 265 to the first silicon substrate 201 of cmos circuit 210
Second end.
Specifically, cmos circuit 210 is overturn, reduction processing then is carried out to the first silicon substrate 201.
As shown in fig. 4f, multiple well regions are formed in the second silicon substrate 101, and are formed absolutely on the second silicon substrate 101
Edge laminated construction.
For the ease of being programmed operation to the storage unit in three-dimensional memory structure, the shape in the second silicon substrate 101
At multiple well regions.For example, the second silicon substrate 101 includes the public source zone of multiple channel columns.
The insulating laminate structure includes the multiple sacrificial layers 152 stacked, and adjacent sacrificial layer 152 is by second insulating layer 102
It is separated from each other.In this embodiment, second insulating layer 102 is for example made of silica, and sacrificial layer 152 is for example by silicon nitride group
At.
As described below, sacrificial layer 152 will be replaced as grid conductor 121 to 123, and 121 1 step of grid conductor is connected to string
Selection line, 123 1 step of grid conductor are connected to the ground selection line, and 122 1 step of grid conductor is connected to wordline.In order to be formed from grid
Conductor 121 to 123 reaches the conductive channel of wordline, and multiple sacrificial layers 152 are for example patterned step-like, that is, each sacrificial layer
152 marginal portion provides electrical connection area relative to the sacrificial layer exposure of top.In the patterning step of multiple sacrificial layers 152
Later, insulating laminate structure can be covered using insulating layer.In fig.4 by between multiple sacrificial layers 152 interlayer insulating film and
The interlayer insulating film of covering insulating laminate structure is integrally shown as second insulating layer 102.It, can be with however, the invention is not limited thereto
It is formed between multiple sacrificial layers 152 using multiple independent deposition steps and its multiple interlayer insulating films of top.
Further, channel hole is formed in insulating laminate structure.In this embodiment, for example, semiconductor structure table
Photoresist mask is formed on face, then carries out anisotropic etching, and channel hole is formed in insulating laminate structure.Respectively to different
Property etching can use dry etching, such as ion beam milling etching, plasma etching, reactive ion etching, laser ablation.For example, logical
Control etching period is crossed, so that the close beneath for being etched in public source zone stops, and is etched in the lower section of the first insulating regions
Nearby stop.After the etching by dissolving or being ashed removal photoresist mask in a solvent.
Further, channel column 110 is formed in channel hole.The lower part of channel column 110 includes semiconductor layer.Further
Ground, channel column 110 include the channel layer that semiconductor layer is extended to from upper part.For the sake of clarity, ditch is not shown in fig.4
The internal structure of road column 110.Referring to Fig. 1 b, in the middle section of channel column 110, channel column 110 includes being sequentially stacked on channel
Tunneling medium layer, charge storage layer and block media layer on layer, at the both ends of channel column 110, channel column 110 includes being stacked on
Block media layer on channel layer or semiconductor layer.The lower end of channel column 110 connects with the public source zone in the second silicon substrate 101
Touching.In final three-dimensional memory structure, the upper end of channel column 110 will be connected with wiring layer, effectively deposit to be formed
Storage unit.The structure of the channel column 110 is, for example, ONOP (oxidenitride oxide-polysilicon).
Preferably, false channel column 130 is formed in channel hole.The internal structure of false channel column 130 and channel column 110 can be with
It is identical, and at least across at least part grid conductor in rhythmic structure of the fence.However, in final three-dimensional memory structure
In, the upper end of false channel column 130 is not connected with wiring layer, so that mechanical support effect is provided solely for, without being used to form
Selection transistor and memory transistor.
Preferably, through hole is formed in insulating laminate structure, and conductive channel 141 and insulation are formed in through hole
Lining 142.Conductive channel 141 pass through insulating laminate structure, and between insulating laminate structure by insulation lining 142 each other every
It opens.One end of conductive channel 141 extends in the second silicon substrate 101 below insulating laminate structure, reaches public source zone, another
End will be connected to wiring layer.
As shown in figure 4g, in insulating laminate structure, sacrificial layer 152 is replaced as grid conductor 121 to 123, forms grid
Laminated construction.
In this step, grid line gap 151 is formed in insulating laminate structure (referring to fig. 2 a), using second insulating layer
102 are used as etching stopping layer, cavity are formed by etching removal sacrificial layer 152 via grid line gap 151, and use metal
Layer filling cavity is to form grid conductor 121 to 123, wherein multiple grid conductors 121 to 123 and second insulating layer 102 replace
It stacks.Correspondingly, multiple channel columns 110 run through rhythmic structure of the fence.
When forming grid line gap 151, anisotropic etching can be used, is lost for example, by using dry etching, such as ion beam milling
Quarter, plasma etching, reactive ion etching, laser ablation.For example, by control etching period, so that being etched in the second silicon lining
The surface at bottom 101 nearby stops.In this embodiment, grid conductor 121 to 123 is divided into a plurality of grid line by grid line gap 151.
It is folded using isotropic etching removal insulation using grid line gap 151 as etchant channel when forming cavity
Sacrificial layer 152 in layer structure is to form cavity.Isotropic etching can be using wet etching or the gas phase erosion of selectivity
It carves.Use etching solution as etchant in wet etching, wherein in the etch solution by semiconductor structure submergence.In gas
Mutually use etching gas as etchant in etching, wherein semiconductor structure is exposed in etching gas.
What second insulating layer 102 and sacrificial layer 152 in insulating laminate structure were made of silica and silicon nitride respectively
Under situation, in wet etching can using phosphoric acid solution as etchant, in gas phase etching can use C4F8, C4F6,
One of CH2F2 and O2 or a variety of.In an etching step, etchant is full of grid line gap 151.It is sacrificial in insulating laminate structure
The end of domestic animal layer 152 is exposed in the opening in grid line gap 151, and therefore, sacrificial layer 152 touches etchant.Etchant is by grid
The opening of linear slit gap 151 is gradually to the etched inside sacrificial layer 152 of insulating laminate structure.Due to the selectivity of etchant, the erosion
It carves and removes sacrificial layer 152 relative to the second insulating layer 102 in insulating laminate structure.
When forming grid conductor 121 to 123, using grid line gap 151 as deposit channel, using atomic layer deposition
(ALD), metal layer is filled in grid line gap 151 and cavity.
In this embodiment, metal layer is for example made of tungsten.The forerunner source used in atomic layer deposition is, for example, hexafluoro
Change tungsten WF6, the reducing gas of use is, for example, silane SiH4 or diborane B2H6.In the atomic layer deposition the step of, six are utilized
The chemisorption of the reaction product of tungsten fluoride WF6 and silane SiH4 obtains tungsten material and realizes deposition process.
As shown in figure 4h, above rhythmic structure of the fence, interconnection structure is formed.
The interconnection structure includes multiple conductive channels 161 above the rhythmic structure of the fence, divides with multiple conductive channels 161
Multiple contact pads 162 for not contacting, are located at multiple wiring layers at multiple wiring layers 164 on multiple contact pads 162
Multiple external pads 165 on 164 and the conduction of interconnection is provided on the direction on the surface perpendicular to the second silicon substrate 101
Channel 163.
It is memory cell array 220 in the semiconductor structure that the step is formed, wherein rhythmic structure of the fence is together with channel column
Form selection transistor and memory transistor.In the middle section of channel column 110, grid conductor 121 to 123 and channel column
Channel layer, tunneling medium layer, charge storage layer and block media layer inside 110 together, form memory transistor.In channel column
Channel layer (or semiconductor layer) and block media layer one inside 110 both ends, grid conductor 121 to 123 and channel column 110
It rises, forms selection transistor.
Grid conductor 121,122 and 123 in rhythmic structure of the fence for example formed it is step-like, for providing conductive channel 161
Extend up to the space of corresponding grid conductor.The conductive channel and wiring layer of memory cell array 220 be located at least one
In two insulating layers 102.As described above, being shown in figure second insulating layer 102 is single layer, however, second insulating layer 102 can be real
It is made of on border multiple interlayer insulating films, including the multiple interlayer insulating films and use for separating grid conductor 121,122 and 123
In the multiple interlayer insulating films for separating various wirings layer.In addition, contact pad 162 and external pads 165 can also be located at individually
Interlayer insulating film on.
Further, the first end of channel column 110 is commonly connected to the public source zone in the second silicon substrate 101, channel column
110 second end is connected to contact pad 162 via conductive channel 161, is then connected to accordingly via conductive channel and wiring
External pads 165.The first end of conductive channel 141 extends to the public source zone in the second silicon substrate 101, and second end is via leading
Electric channel 161 is connected to contact pad 162, is then connected to corresponding external pads 165 via conductive channel and wiring.
The bonding surface of memory cell array 220 is the first surface of second insulating layer 102.In this step, the first table
Face is exposed Free Surface.The contact surface of external pads 165 exposes on the first surface.
As shown in figure 4i, cmos circuit 210 and memory cell array 220 are bonded to three-dimensional memory structure 200.
When cmos circuit 210 and memory cell array 220 are bonded to three-dimensional memory structure 200, cmos circuit 210
Through silicon via 265 and the external pads 165 of memory cell array 220 be in contact with each other, to realize that cmos circuit 210 and storage are single
Electrical connection between element array 220.
Flow chart has been used to be used to illustrate operation performed by method according to an embodiment of the present application herein.It should be understood that
, the operation of front not necessarily accurately carries out in sequence.On the contrary, various steps can be handled according to inverted order or simultaneously
Suddenly.Meanwhile or during other operations are added to these, or from these processes remove a certain step or number step operation.For example, certain
A little steps not necessarily, thus can be omitted, or replace with other steps.
Above-described embodiment is formed by semiconductor structure, and using subsequent conventional steps, three-dimensional storage can be obtained
Part.
It is as described above according to the embodiment of the present invention, these embodiments details all there is no detailed descriptionthe, also not
Limiting the invention is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is principle and practical application in order to better explain the present invention, thus belonging to making
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention is only by right
The limitation of claim and its full scope and equivalent.
Claims (10)
1. a kind of three-dimensional memory structure stacked based on through silicon via characterized by comprising
Cmos circuit, the first insulating layer including the first silicon substrate and on first silicon substrate, first insulation
There are multiple first external pads in layer；
Memory cell array, the second insulating layer including the second silicon substrate and on second silicon substrate, described second
There are multiple second external pads in insulating layer；
Wherein, the cmos circuit further includes the through silicon via through the first insulating layer and the first silicon substrate, and the of the through silicon via
One end is electrically connected with first external pads, bottom-exposed of the second end in first silicon substrate；
First silicon substrate of the cmos circuit and the second insulating layer of the memory cell array are in contact with each other, the through silicon via
It is coupled with second external pads, to realize the electrical connection between the cmos circuit and the memory cell array.
2. three-dimensional memory structure according to claim 1, which is characterized in that the cmos circuit includes the first wiring
Layer, the memory cell array include the second wiring layer, and first wiring layer and second wiring layer are laterally extended.
3. three-dimensional memory structure according to claim 2, which is characterized in that the through silicon via by the first wiring layer with
The first external pads electrical connection.
4. three-dimensional memory structure according to claim 1, which is characterized in that the cmos circuit includes multiple first leading
Electric channel, the electrical connection being used to provide the described between multiple first external pads；
The memory cell array includes multiple second conductive channels, is used to provide the described between multiple second external pads
Electrical connection.
5. three-dimensional memory structure according to claim 4, which is characterized in that the through silicon via includes metal layer and glue
Layer and/or barrier layer.
6. three-dimensional memory structure according to claim 4, which is characterized in that the cmos circuit further include:
Multiple transistors in first silicon substrate；
The multiple contact pads being connected in the second insulating layer and with multiple transistors；
First external pads and first conductive channel are located in first insulating layer；
The multiple contact pad is connected to accordingly via the multiple first external pads and the multiple first conductive channel
The through silicon via.
7. three-dimensional memory structure according to claim 4, which is characterized in that the memory cell array further include:
Public source zone in second silicon substrate；
Rhythmic structure of the fence on second silicon substrate, the rhythmic structure of the fence include the grid conductor of many levels；
Through multiple channel columns of the rhythmic structure of the fence；
Multiple contact pads on the rhythmic structure of the fence；
Wherein, the first end of the multiple channel column extends to public source zone, and second end is connected to corresponding contact pad,
The grid conductor of the multiple level is respectively connected to corresponding contact pad；
Second insulating layer is covered on the rhythmic structure of the fence；
Second external pads and second conductive channel are located in the second insulating layer.
8. three-dimensional memory structure according to claim 7, which is characterized in that the memory cell array further include: pass through
At least one additional conductive channel of the second insulating layer is worn, the first end of at least one additional conductive channel extends to
The public source zone, second end are connected to corresponding contact pad.
9. a kind of manufacturing method of the three-dimensional memory structure stacked based on through silicon via characterized by comprising
Cmos circuit is formed, the cmos circuit includes the first silicon substrate and the first insulation on first silicon substrate
Layer, there are multiple first external pads in first insulating layer；
The through silicon via for running through the first insulating layer and the first silicon substrate is formed, the first end of the through silicon via and first outside are welded
Disk electrical connection, bottom-exposed of the second end in first silicon substrate；
Memory cell array is formed, the memory cell array includes the second silicon substrate and on second silicon substrate
Second insulating layer has multiple second external pads in the second insulating layer；
The cmos circuit and the memory cell array are bonded to the three-dimensional memory structure, wherein the CMOS electricity
First silicon substrate on road and the second insulating layer of the memory cell array are in contact with each other, outside the through silicon via and described second
Pad bonding, to realize the electrical connection between the cmos circuit and the memory cell array.
10. according to the method described in claim 9, it is characterized in that, forming the silicon for running through the first insulating layer and the first silicon substrate
Through-hole includes:
First insulating layer is etched to form groove, the groove extends to inside first silicon substrate；
It is sequentially depositing glue-line and/or barrier layer, metal layer in the groove；
The first end of the through silicon via is electrically connected with first external pads；
Reduction processing is carried out with the second end of the exposure through silicon via to first silicon substrate.
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