CN109300500B - Data management method and system for memory device - Google Patents
Data management method and system for memory device Download PDFInfo
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- G11—INFORMATION STORAGE
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Abstract
The invention discloses a data management method and a system of a memory device, wherein the data management method of the memory device comprises the following steps: counting a system time; designating a block number of a first block of the memory device to point to a maximum remaining retention time when at least a portion of the first block is accessed or updated or programmed for a first time or whenever the first block of the memory device is accessed or updated or programmed for the entire first block; when a first degradation trigger time is reached and the block number currently points to the maximum remaining storage time, pointing the block number to an intermediate remaining storage time; when a second degradation trigger time is reached and the block number currently points to the intermediate remaining storage time, pointing the block number to a minimum remaining storage time; and triggering the memory device to update the block once the block number points to the minimum remaining storage time, and pointing the block number to the maximum remaining storage time.
Description
Technical Field
The invention relates to a data management method and a data management system of a memory device.
Background
With the development of semiconductor technology, various semiconductor memories are continuously being developed. For example, flash memory (flash memory), magnetic memory (magnetic core memory) or Phase Change Memory (PCM) are widely used in electronic devices.
Phase change memory is a type of non-volatile random access memory. Phase change memory materials can be converted to a crystalline state (crystalline state) and an amorphous state (amorphous state) to store digital data. When reading, the digital data stored in the memory cell is judged to be logic 1 or logic 0 by judging the resistance value of the memory cell.
However, the resistance of the memory cell may drift (e.g., from a high resistance state to a low resistance state) over time, and thus the read data may be erroneously determined. To avoid erroneous data reading, one of the current practical approaches is to refresh (refresh) the memory cells (or memory pages) after a period of time to solve the resistance drift.
The invention provides a data management method and a data management system of a memory device, which are used for managing the storage time and the updating time of the memory device.
Disclosure of Invention
According to an example of the present invention, a data management system of a memory device is provided, the memory device including a plurality of blocks, the data management system comprising: a processor having a system timer for counting a system time, the processor coupled to the memory device; and a retention time memory unit coupled to the processor, the retention time memory unit including a remaining retention time storage area, a block number storage area, and a retention mode parameter storage area, the retention mode parameter storage area including a first retention mode, the remaining retention time storage area including a first maximum remaining retention time, a first minimum remaining retention time, and a first middle remaining retention time associated with the first retention mode, the block number storage area storing at least a first block number of a first block of the blocks of the memory device. The processor designates the first block number of the first block to point to the first maximum remaining retention time of the first retention mode when at least a portion of the first block of the memory device is accessed or updated or programmed for a first time or whenever the first block of the memory device is accessed or updated or programmed for the entire first block. When a first degradation trigger time is reached and the first block number of the first block currently points to the first maximum remaining holding time, the processor points the first block number of the first block from the first maximum remaining holding time to the first intermediate remaining holding time. When a second degradation trigger time is reached and the first block number of the first block currently points to the first intermediate remaining storage time, the processor points the first block number of the first block from the first intermediate remaining storage time to the first minimum remaining storage time. Once the first block number of the first block points to the first minimum remaining preservation time, the processor triggers the memory device to update the first block, and the processor points the first block number of the first block from the first minimum remaining preservation time to the first maximum remaining preservation time.
According to another example of the present invention, there is provided a data management method of a memory device, including: counting a system time; assigning a first block number of a first block of the memory device to point to a first maximum remaining retention time of a first retention mode when at least a portion of the first block of the memory device is accessed or updated or programmed for a first time or whenever the first block of the memory device is accessed or updated or programmed for the entire first block, the first retention mode including the first maximum remaining retention time, a first minimum remaining retention time, and a first intermediate remaining retention time; when a first degradation trigger time of the first maximum remaining holding time is reached and the first block number of the first block currently points to the first maximum remaining holding time, pointing the first block number of the first block from the first maximum remaining holding time to the first intermediate remaining holding time; when a second degradation trigger time of the first middle remaining holding time is reached and the first block number of the first block currently points to the first middle remaining holding time, pointing the first block number of the first block from the first middle remaining holding time to the first minimum remaining holding time; and triggering the memory device to update the first block once the first block number of the first block points to the first minimum remaining preservation time, and pointing the first block number of the first block from the first minimum remaining preservation time to the first maximum remaining preservation time.
Drawings
In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments is made with reference to the accompanying drawings:
FIG. 1 is a diagram of a data management system according to an embodiment of the invention.
FIG. 2 shows a schematic diagram of a retention time memory cell according to an embodiment of the invention.
FIGS. 3A-3H are schematic diagrams illustrating the retention time management according to an embodiment of the invention.
FIG. 4 is a diagram illustrating data management with two storage modes according to another embodiment of the present invention.
FIG. 5 is a flow chart of a method for managing data of a memory device according to an embodiment of the invention.
[ notation ] to show
100: the data management system 150: memory device
110: the processor 115: system timer
120: retention time memory cell
122: storage mode parameter storage area 124: remaining retention time storage area
126: block number storage area
PP 0-PPn: block numbering
510-530C: step (ii) of
Detailed Description
The technical terms in the specification refer to the common terms in the technical field, and if the specification explains or defines a part of the terms, the explanation of the part of the terms is based on the explanation or definition in the specification. Various embodiments of the present invention each have one or more technical features. In the present invention, the present invention provides a method for implementing a mobile communication system, which is capable of providing a mobile communication system with a plurality of mobile communication devices.
Referring now to FIG. 1, therein is shown a schematic diagram of a data management system 100 in accordance with an embodiment of the present invention. The data management system 100 is coupled to the memory device 150 for managing data storage of the memory device 150. That is, the data management system 100 determines the remaining retention time and the update time of the plurality of memory pages of the memory device 150.
The data management system 100 includes: a processor 110 and a save time memory unit 120. The processor 110 further includes a system time counter (system time counter) 115. The processor 110 is coupled to the memory device 150 and the retention time memory unit 120. The remaining retention time and the refresh time of the memory device 150 managed by the processor 110, and the operation of the processor 110 will be described in detail below. The system timer 115 is used to count the system time.
Referring now to FIG. 2, therein is shown a schematic diagram of a retention time memory unit 120 according to an embodiment of the invention. As shown in fig. 2, the save time memory unit 120 includes: a saving mode parameter storage area 122, a remaining saving time storage area 124 and a block number storage area 126.
The saving mode parameter storage area 122 is used for storing at least one saving mode parameter. The saving mode parameter is used for indicating the saving mode of the corresponding block. Herein, a "block" refers to a storage block of the memory device 150, such as a memory page (memory page). Memory device 150 includes a plurality of blocks. In this embodiment, for convenience of illustration, all the blocks of the memory device 150 corresponding to the same storage mode are taken as an example for illustration, but the invention is not limited thereto at first. When a portion or all of a block of the memory device 150 is accessed or updated or programmed for the first time, the processor 110 predicts a predetermined retention time of the block and assigns a retention mode of the block. In an embodiment of the present invention, a worst case scenario may be when a portion or all of the block of memory device 150 is accessed or updated or programmed for the first time. Because, this means that the corresponding memory cells within the block that were accessed the first time or updated or programmed the first time are likely to be the fastest to hold time. As used herein, the term "first access or first update or first program" means that the block of the memory device 150 is accessed or updated or programmed for the first time after the memory device 150 is manufactured.
In another embodiment of the present invention, each time a block of the memory device 150 is accessed or updated or programmed in its entirety, the processor 110 predicts the predetermined saving time of the block and designates the saving mode of the block. Since the entire block is accessed or updated or programmed, the same retention time may be assigned to all memory cells of the block.
When the storage mode is 10000 seconds, the maximum remaining storage time of the corresponding block is 10000 seconds. That is, in the embodiment of the present invention, after the block is updated or accessed, the block is updated before the retention time expires. Similarly, if the retention mode is 107 seconds, the embodiment of the present invention updates the block after the block is updated or accessed before the retention time (107 seconds) expires.
The remaining storage time storage area 124 is used to indicate the current remaining storage time corresponding to each block. Taking 10000 seconds as an example for the preservation mode, in the embodiment of the present invention, 10000 seconds are divided into 10 groups, the 1 st group represents 10000 seconds, the 2 nd group represents 9000 seconds, and the rest can be analogized, although the present invention is not limited thereto. In other possible embodiments of the present invention, the maximum remaining saving time may be divided into a plurality of groups in other manners, for example, exponentially or logarithmically.
In the embodiment of the invention, the blocks are grouped according to the respective remaining storage time of the blocks, and the blocks with the same remaining storage time belong to the same group.
For example, at a time point when the remaining storage time of block P9 is 10000 seconds, processor 110 groups block number PP9 (related to block P9) into group 1; the remaining holding time of block P8 is 9000 seconds, processor 110 groups block PP8 (related to block P8) into group 2, the remaining holding time of block P0 is 1000 seconds, processor 110 groups block PP0 (related to block P0) into group 10, and so on. 10000 seconds may also be referred to as maximum remaining hold time, 1000 seconds may also be referred to as minimum remaining hold time, and 2000 seconds-9000 seconds may also be referred to as intermediate remaining hold time.
The block number area 126 is used to store all block numbers of all blocks belonging to the memory device 150. When a block is updated or accessed or programmed, the processor 110 points a block number of the block to the maximum remaining saving time; when the degradation condition is triggered, the processor 110 degrades a block number meeting the degradation condition, and the block number points to the next remaining saving time. In the embodiment of the invention, each group has a respective degradation triggering condition.
Referring now to fig. 3A-3H, shown are schematic diagrams of retention time management according to an embodiment of the present invention. For convenience of explanation, the description is made starting from the System Time (ST) of the system timer 115 being equal to 0 second (ST ═ 0). Please note that, in the present invention, the reference symbols PP0-PP6 appearing in the block number storage area 126 represent respective block numbers pointing to the blocks P0-P6 (not shown, the blocks P0-P6 are located in the memory device 150). in practice, the block numbers may be implemented, for example and without limitation, as "pointers" pointing to corresponding blocks in the memory device 150.
As shown in fig. 3A, when the system time is equal to 0 second (ST ═ 0), the block P0 is accessed or updated, and the processor 110 sets the remaining storage time of the block P0 to 10000 seconds, so that the processor 110 classifies the block number PP0 of the block P0 as the 1 ST group, and the block number PP0 of the block P0 points to 10000 seconds (this means that the remaining storage time of the block P0 is 10000 seconds). That is, in the embodiment of the present invention, before the system time is 10000 seconds, the block corresponding to the block number in the 1 st group is updated to avoid misjudging the data of the block.
In the embodiment of the invention, the processor 110 may predict the retention time of the block according to the condition (such as the pulse voltage) of programming, accessing or updating the block, or the chip temperature of the memory device 150. For example, the processor 110 predicts the retention time of a worst cell of the block as the retention time of the block. How to predict the retention time is not particularly limited in the embodiments of the present invention.
That is, in the embodiment of the present invention, each block corresponds to a save mode. Embodiments of the present invention may have one or more save modes. For convenience of explanation, all blocks corresponding to the same storage mode are used as examples, but it should be understood that the invention is not limited thereto.
As shown in fig. 3B, when the system time equals 1000 seconds (ST ═ 1000), the processor 110 knows that the 1 ST group degradation is to be triggered (i.e., the degradation condition of the 1 ST group is triggered), so the processor 110 degrades the block number PP0 of the 1 ST group to the 2 nd group. Here, "downgrade" means that the processor 110 changes the block number belonging to the same group from pointing to the current group to pointing to the next group. The principle of the processor 110 triggering "downgrading" is that the processor 110 knows the remaining reserved time corresponding to each group in advance, so that the processor 110 can trigger when the system time reaches the trigger time. Taking the 1 st group as an example, the remaining storage time of the 1 st group is 10000 seconds, and the remaining storage time of the 2 nd group is 9000 seconds, so that the "group remaining storage time interval" of the 1 st group is 10000-. Processor 110 downgrades group 1 (i.e., downgrades once every 1000 seconds) when the system time is 1000 seconds, 2000 seconds, …, 9000 seconds, 10000 seconds, 11000 seconds, 12000 seconds …. Similarly, taking the 2 nd group as an example, the remaining holding time of the 2 nd group is 9000 seconds, and the remaining holding time of the 3 rd group is 8000 seconds, so when the system time is 2000 seconds, 3000 seconds, …, 9000 seconds, 10000 seconds, 11000 seconds, 12000 seconds …, the processor 110 downgrades the 2 nd group. The rest can be analogized. That is, in the embodiment of the present invention, when the degradation condition is triggered, the processor 110 degrades the block number of the block from the current group to the next group, which means that the processor 110 decreases the remaining saving time of the block.
Although in the above example, the group remaining storage time interval of each group is the same, in other possible embodiments of the present invention, the group remaining storage time interval of each group may be different, and this is within the spirit of the present invention. For example, in other possible embodiments of the present invention, 5 groups are taken as an example, the remaining storage time of the 1 st group is 10000, the remaining storage time of the 2 nd group is 9000, the remaining storage time of the 3 rd group is 7500, the remaining storage time of the 4 th group is 5500, and the remaining storage time of the 5 th group is 1000. In this case, the difference between the remaining retention time intervals for the two groups is used as the basis for the degradation. In the above example, the remaining holding time of the 1 st group is 10000, the remaining holding time of the 2 nd group is 9000, and the difference between the remaining holding time intervals is 1000 seconds, so the processor 110 downgrades the 1 st group every 1000 seconds. Likewise, processor 110 downgrades the 2 nd group every 1500 seconds. The rest can be analogized. Processor 110 downgrades the 3 rd group every 2000 seconds. Processor 110 destages the 4 th group every 4500 seconds.
As shown in fig. 3C, when the system time is equal to 1500 seconds (ST is 1500), the block P1 is accessed or updated, the processor 110 sets the remaining storage time of the block P1 to 10000 seconds, the processor 110 classifies the block number PP1 of the block P1 as the 1 ST group (remaining storage time is 10000 seconds), and the block number PP0 of the block P0 is still the 2 nd group (remaining storage time is 9000 seconds).
As shown in fig. 3D, when the system time is equal to 2000 seconds (ST ═ 2000), the processor 110 triggers the degradation of group 1 and group 2, so that the block number PP0 (originally belonging to group 2) of the block P0 is degraded to group 3 (remaining retention time is 8000 seconds), and the block number PP1 (originally belonging to group 1) of the block P1 is degraded to group 2 (remaining retention time is 9000 seconds).
Thereafter, when the system time is equal to 3000 seconds (ST is 3000) (not shown), processor 110 triggers demotion, so that tile number PP0 (originally belonging to group 3) of tile P0 is demoted to group 4 (remaining retention time is 7000 seconds), and tile number PP1 (originally belonging to group 2) of tile P1 is demoted to group 3 (remaining retention time is 8000 seconds). And so on. When the system time equals 7000 seconds (ST 7000) (not shown), processor 110 triggers demotion, so that tile number PP0 (originally belonging to group 7) of tile P0 is demoted to group 8 (remaining retention time is 3000 seconds), and tile number PP1 (originally belonging to group 6) of tile P1 is demoted to group 7 (remaining retention time is 4000 seconds).
As shown in fig. 3E, assuming that the access or update of the blocks P2-P4 is performed (more specifically, the internal data of the whole blocks of the blocks P2-P4 are all updated once) when the system time is equal to 7950 seconds (ST ═ 7950), the processor 110 sets the remaining storage time of the blocks P2-P4 to 10000 seconds, the processor 110 classifies the block numbers PP2-PP4 of the blocks P2-P4 as the 1 ST group, the block number PP0 of the block P0 is still the 8 th group, and the block number PP1 of the block P1 is still the 7 th group. Here, the access or update times to blocks P2-P4 are not necessarily all at the same time. That is, assuming that the block P2 is accessed or updated first (but the blocks P3 and P4 are not accessed or updated yet), and then the blocks P3 and P4 are accessed or updated while the block number PP2 of the block P2 still belongs to the 1 st group, the processor 110 groups the block numbers PP2-PP4 of the blocks P2-P4 together into the 1 st group.
When the system time is 8000 seconds (ST 8000) (not shown), the system downgrades the block numbers PP0-PP4 of the blocks P0-P4, the processor 110 downgrades the block numbers PP2-PP4 of the blocks P2-P4 to the 2 nd group (9000 seconds remaining), downgrades the block number PP0 of the block P0 to the 9 th group (2000 seconds remaining), and downgrades the block number PP1 of the block P1 to the 8 th group (3000 seconds remaining).
As shown in fig. 3F, when the system time is 8950 seconds (ST — 8950), the block P5 is accessed or updated, the processor 110 sets the remaining storage time of the block P5 to 10000 seconds, the processor 110 classifies the block number PP5 of the block P5 as the 1 ST group (remaining storage time is 10000 seconds), the block number PP0 of the block P0 is still the 9 th group (remaining storage time is 2000 seconds), the block number PP1 of the block P1 is still the 8 th group (remaining storage time is 3000 seconds), and the block numbers PP2-PP4 of the blocks P2-P4 are still the 2 nd group (remaining storage time is 9000 seconds).
As shown in fig. 3G, when the system time equals 9000 seconds (ST 9000), block P6 is accessed or updated, and processor 110 downgrades blocks P0-P5. The processor 110 sets the remaining storage time of the block P6 to 10000 seconds, and the processor 110 classifies the block number PP6 of the block P6 as the 1 st group (remaining storage time is 10000 seconds). Processor 110 demotes block number PP5 of block P5 to group 2 (9000 seconds remaining retention time), demotes block numbers PP2-PP4 of blocks P2-P4 to group 3 (8000 seconds remaining retention time), demotes block number PP0 of block P0 to group 10 (1000 seconds remaining retention time), and demotes block number PP1 of block P1 to group 9 (2000 seconds remaining retention time).
In the embodiment of the present invention, when the block number is downgraded to the lowest group (i.e. 10 th group, the remaining storage time is 1000 seconds), the processor 110 triggers the upgrade of the block number, and upgrades the block number from the lowest group to the 1 st group, and at the same time, the processor 110 triggers the memory device 150 to update the corresponding block (the block number of which is upgraded from the lowest group to the 1 st group). As shown in fig. 3H, when the system time is 9000 seconds (ST 9000), the processor 110 triggers the upgrade of the block number PP0 of the block P0, and upgrades the block number PP0 of the block P0 to the 1 ST group. Since the block number PP6 of the block P6 is also the 1 st group, the processor 110 can point the block number PP0 of the block P0 to the block number PP6 of the block P6, and point the block number PP6 of the block P6 to 10000 seconds.
In addition, in the embodiment of the invention, because the block numbers in the same group point to each other, when block updating is carried out, which blocks are updated can be conveniently known. For example, the block numbers PP2-PP4 belong to the same group, and when the processor 110 downgrades the block numbers PP2-PP4 to the last group, the processor 110 notifies the memory device 150 to update the blocks P2-P4. In detail, since the block number PP2 points to the lowest remaining saving time, the block number PP3 points to the block number PP2, and the block number PP4 points to the block number PP3, through these pointing relationships, the processor 110 can know that the group pointing to the lowest remaining saving time includes the block numbers PP2-PP4, and therefore, the processor 110 can know that the block P2-P4 corresponding to the block numbers PP2-PP4 is updated. In the present specification, among one or more block numbers referring to the same remaining holding time, one block number refers to "directly" the remaining holding time (e.g., block number PP2 in fig. 3E), and the other block numbers refer to "indirectly" the remaining holding time (e.g., block numbers PP3-PP4 in fig. 3E, refer to the remaining holding time through block number PP 2).
In the embodiment of the present invention, if a block is accessed or updated, the processor 110 upgrades the block number of the block to the 1 st group, regardless of which group the block number originally belongs to. That is, if a block is accessed, the processor 110 sets the remaining saving time of the block to 10000 seconds (i.e., the maximum remaining saving time). In addition, when the block is accessed or updated, the block number of the block is currently pointing to the 1 st group, and the block number of the block remains pointing to the 1 st group.
In addition, in the embodiment of the present invention, after performing the downgrade, if a plurality of block numbers point to the minimum holding time at the same time, the processor 110 sequentially triggers the update of the blocks (i.e. the update times of the blocks may be different from each other). For example, after demotion, block numbers PP0 and PP1 both point to the minimum retention time (1000 s). When the system time equals 9000 seconds, the processor 110 triggers the memory device 150 to update the block P0. When the system time equals 9050 seconds, the processor 110 triggers the memory device 150 to update the block P1. Therefore, the blocks P0 and P1 can be updated before the remaining storage time of the blocks P0 and P1 is less than 0, so as to prevent the resistance values of the blocks P0 and P1 from drifting and being misjudged.
In short, in the embodiment of the present invention, when a block is accessed or updated, the processor upgrades the block number of the block to the 1 st group to point to the maximum remaining saving time. In addition, the processor regards a plurality of block numbers pointing to the same remaining saving time as the same group, and among the block numbers belonging to the same group, one of the block numbers points to the corresponding remaining saving time, and the remaining block numbers may point to each other (as shown in fig. 3F, block numbers PP2-PP4, PP2 point to the corresponding remaining saving time, PP3 point to PP2, and PP4 point to PP 3).
When the processor knows that a group's "degradation trigger time point" has been reached, the processor degrades all block numbers in the group to the next group. In practice, under the control of the processor, the 1 st block number in the group (e.g., block number PP2 in fig. 3F) points from the current remaining holding time to the next remaining holding time, and the pointing relationship of other block numbers belonging to the same group (e.g., block numbers PP3 and PP4 in fig. 3F) is not changed. Therefore, by modifying the direction of the 1 st block number in the group, the group can be changed to point to the next remaining storage time.
FIG. 4 is a diagram illustrating data management with two storage modes according to another embodiment of the present invention. As shown in fig. 4, the saving mode may include two types: 104 seconds and 107 seconds. These saving modes may include different remaining saving times. For example, the 104 second save mode includes: remaining holding times of 10000 seconds, 9000 seconds, …, 1000 seconds (block numbers PP0, PP1, and PP4 point to 10000 seconds, 9000 seconds, and 1000 seconds, respectively); and the 107 second save mode includes: the remaining storage time was 100 days (D), 90 days (D), …, 10 days (D) (block numbers PP5, PP6 and PPn point to 100D (days) seconds, 90D (days) and 10D (days), respectively). Of course, other possible embodiments of the invention may include more storage modes, all within the spirit of the invention.
Taking fig. 4 as an example, when a block is programmed, accessed or updated, the processor 110 may predict the predetermined saving time of the block, and accordingly find the corresponding saving mode. For example, taking fig. 4 as an example, when accessing block P0, processor 110 predicts that the saving time of block P0 may be 20000 seconds, so processor 110 designates the saving mode of block P0 as 10000(104) seconds, and lets block number PP0 of block P0 point to the maximum remaining saving time (10000 seconds) of the saving mode (104 seconds). In another example, when accessing block P5, processor 110 predicts that the saving time of block P5 may be 150 days, so processor 110 designates the saving mode of block P5 as 107 seconds and points the block number PP5 of block P5 to the maximum remaining saving time 100D (days) of the saving mode (107 seconds). That is, in the embodiment of the present invention, each block corresponds to a save mode.
Referring to fig. 5, a flow chart of a data management method of a memory device according to an embodiment of the invention is shown. As shown in fig. 5, in step 510, a system time is counted. In step 520, when accessing or updating or programming the first block of the memory device 150 for the first time (or whenever the first block is accessed or updated or programmed for the first time), the processor 110 assigns a first block number of the first block to point to a first maximum remaining saving time of a first saving mode, wherein the first saving mode includes the first maximum remaining saving time, a first minimum remaining saving time and a first intermediate remaining saving time. In step 530A, when a first degradation trigger time of the first maximum remaining saving time is reached and the first block number of the first block currently points to the first maximum remaining saving time, the processor 110 points the first block number of the first block from the first maximum remaining saving time to the first intermediate remaining saving time. In step 530B, when a second degradation trigger time of the first middle remaining saving time is reached and the first block number of the first block currently points to the first middle remaining saving time, the processor 110 points the first block number of the first block from the first middle remaining saving time to the first minimum remaining saving time. In step 530C, once the first block number of the first block points to the first minimum remaining preservation time, the processor 110 triggers the memory device to update the first block and points the first block number of the first block from the first minimum remaining preservation time to the first maximum remaining preservation time.
In the embodiment of the invention, through group management of the remaining retention time of the blocks of the memory device, the blocks can be effectively updated before the remaining retention time of the blocks expires, so as to avoid data error reading caused by resistance drift of the blocks. In addition, the management mechanism can be greatly simplified due to the remaining retention time of the grouped management blocks.
In summary, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope of the appended claims.
Claims (8)
1. A data management system for a memory device, the memory device including a plurality of blocks, the data management system comprising:
a processor having a system timer for counting a system time, the processor coupled to the memory device; and
a retention time memory unit coupled to the processor, the retention time memory unit including a remaining retention time storage area, a block number storage area, and a retention mode parameter storage area, the retention mode parameter storage area including a first retention mode, the remaining retention time storage area including a first maximum remaining retention time, a first minimum remaining retention time, and a first middle remaining retention time associated with the first retention mode, the block number storage area storing at least a first block number of a first block of the blocks of the memory device;
wherein:
the processor designating the first block number of the first block to point to the first maximum remaining retention time of the first retention mode when at least a portion of the first block of the memory device is accessed or updated or programmed for a first time or whenever the first block of the memory device is accessed or updated or programmed for the entire first block;
when a first degradation trigger time of the first maximum remaining holding time is reached and the first block number of the first block currently points to the first maximum remaining holding time, the processor points the first block number of the first block from the first maximum remaining holding time to the first intermediate remaining holding time;
when a second degradation trigger time of the first intermediate remaining holding time is reached and the first block number of the first block currently points to the first intermediate remaining holding time, the processor points the first block number of the first block from the first intermediate remaining holding time to the first minimum remaining holding time; and
once the first block number of the first block points to the first minimum remaining preservation time, the processor triggers the memory device to update the first block, and the processor points the first block number of the first block from the first minimum remaining preservation time to the first maximum remaining preservation time.
2. The data management system of claim 1, wherein the processor assigns a second block number of the second block to point to the first block number of the first block if at least a portion of a second block of the memory device is accessed or updated or programmed for a first time or each time the second block of the memory device is accessed or updated or programmed in its entirety while the first block number of the first block still points to the first maximum remaining holding time.
3. The data management system of claim 1, wherein the storage area further comprises a second storage mode,
when a third block of the memory device is accessed or updated or programmed, the processor predicts a remaining saving time of the third block, and assigns the second saving mode to a third block number of the third block according to the remaining saving time of the third block, and the processor points the third block number of the third block to a second maximum remaining saving time in the second saving mode.
4. The data management system of claim 1, wherein the processor triggers the memory device to update the first block and a fourth block at different times when the first block number of the first block and a fourth block number of the fourth block both point to the first minimum remaining storage time.
5. A data management method for a memory device, the memory device including a plurality of blocks, the data management method comprising:
counting a system time;
assigning a first block number of a first block of the memory device to point to a first maximum remaining retention time of a first retention mode when at least a portion of the first block of the memory device is accessed or updated or programmed for a first time or whenever the first block of the memory device is accessed or updated or programmed for the entire first block, the first retention mode including the first maximum remaining retention time, a first minimum remaining retention time, and a first intermediate remaining retention time;
when a first degradation trigger time of the first maximum remaining holding time is reached and the first block number of the first block currently points to the first maximum remaining holding time, pointing the first block number of the first block from the first maximum remaining holding time to the first intermediate remaining holding time;
when a second degradation trigger time of the first middle remaining holding time is reached and the first block number of the first block currently points to the first middle remaining holding time, pointing the first block number of the first block from the first middle remaining holding time to the first minimum remaining holding time; and
triggering the memory device to update the first block once the first block number of the first block points to the first minimum remaining preservation time, and pointing the first block number of the first block from the first minimum remaining preservation time to the first maximum remaining preservation time.
6. The data management method of claim 5, wherein a second block number of a second block of the memory device is assigned to point to the first block number of the first block if at least a portion of the second block is accessed or updated or programmed for a first time or each time the second block of the memory device is accessed or updated or programmed in its entirety while the first block number of the first block still points to the first maximum remaining holding time.
7. The data management method of claim 5,
when a third block of the memory device is accessed or updated or programmed, a remaining saving time of the third block is predicted, a second saving mode is assigned to a third block number of the third block according to the remaining saving time of the third block, and the third block number of the third block points to a second maximum remaining saving time in the second saving mode, wherein the second saving mode is different from the first saving mode.
8. The data management method of claim 5, wherein the memory device is triggered to update the first block and a fourth block at different time points when the first block number of the first block and a fourth block number of the fourth block both point to the first minimum remaining storage time.
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