CN109290160A

CN109290160A - Micro-machined ultrasonic transducer and relevant apparatus and method

Info

Publication number: CN109290160A
Application number: CN201811294704.9A
Authority: CN
Inventors: 乔纳森·M·罗思伯格; 苏珊·A·阿列; 基思·G·菲费; 内华达·J·桑切斯; 泰勒·S·拉尔斯顿
Original assignee: Butterfly Network Inc
Current assignee: Butterfly Network Inc
Priority date: 2014-07-14
Filing date: 2015-07-14
Publication date: 2019-02-01
Anticipated expiration: 2035-07-14
Also published as: KR20170030605A; US20180003678A1; TWI723955B; KR102073317B1; CN106536067B; US20200400620A1; US20240044846A1; EP3169450B1; WO2016011000A1; KR102111245B1; AU2015289853A1; KR20200011594A; US10228353B2; CN106536067A; US10175206B2; TW201607333A; US9910017B2; TW202127912A; US10247708B2; US11828729B2

Abstract

The present invention relates to micro-machined ultrasonic transducer and relevant apparatus and methods.Manufacture can be related to two individual wafer bonding steps.Chip engagement can be used for manufacturing seal chamber (306) in substrate (302).Chip engagement can also be used for substrate (302) being bonded to another substrate (304), such as CMOS wafer.The engagement of at least the second chip can carry out at low temperature.

Description

Micro-machined ultrasonic transducer and relevant apparatus and method

The application be entitled " micro-machined ultrasonic transducer and relevant apparatus and method ", application No. is 201580038431.X Chinese patent application divisional application, patent application 201580038431.X is according to patent cooperation The international application (PCT/US2015/040342) that treaty was submitted on July 14th, 2015 enters the national Shen of National Phase in China Please.

Cross reference to related applications

The application is according to the attorney number that 35U.S.C. § 119 (e) requires on July 14th, 2014 to submit B1348.70013US00, entitled " Microfabricated Ultrasonic Transducers and Related U.S. Provisional Patent Application Serial Article No. 62/024179 equity of Apparatus and Methods ", it is whole by quoting Body is incorporated herein.

The application is also part continuation application, requires on May 19th, 2015 to submit according to 35U.S.C. § 120 entitled " Microfabricated Ultrasonic Transducers and Related Apparatus and Methods's " Attorney number is U.S. Patent Application Serial the 14/716152nd equity of B1348.70013US02, passes through reference It is integrally incorporated herein.

U.S. Patent Application Serial the 14/716152nd is to continue with application, is required 2015 according to 35U.S.C. § 120 The attorney docket submitted on March 2 is B1348.70013US01, entitled " Microfabricated Ultrasonic The U.S. Patent Application Serial the 14/635,197th of Transducers and Related Apparatus and Methods " Number equity, be incorporated herein by reference in their entirety.

U.S. Patent Application Serial the 14/635197th requires on July 14th, 2014 to mention according to 35U.S.C. § 119 (e) The attorney number of friendship is B1348.70013US00, entitled " Microfabricated Ultrasonic Transducers U.S. Provisional Patent Application Serial Article No. 62/024179 equity of and Related Apparatus and Methods ", During it is incorporated herein by reference in their entirety.

Technical field

Techniques described herein is related to complementary metal oxide semiconductor (CMOS) energy converter and forming method thereof.

Background technique

Capacitance type micromachined ultrasonic energy converter (CMUT) be it is known above micro Process chamber include diaphragm device.Diaphragm It can be used for converting acoustical signals into electric signal, or convert electrical signals to acoustic signal.Therefore, CMUT may be used as surpassing Sonic transducer.

Two kinds of technique can be used to manufacture CMUT.Sacrifice layer process shape on the first substrate above sacrificial layer At the diaphragm of CMUT.Removal sacrificial layer causes diaphragm to be suspended in above chamber.Wafer bonding process by two chips be bonded together with It is formed and has chaffy chamber.

Summary of the invention

The many aspects of the application are related to the manufacture of CMUT and CMOS wafer and integrate, to form CMOS ultrasonic transducer (CUT).According to the one aspect of the application, proposes and be related to the wafer level process of two wafer bonding steps.First chip connects The chamber of sealing, obtained engagement can be formed and two silicon-on-insulator (SOI) chips are bonded together by closing step Structure is considered as engineered substrates.Relatively high temperature (such as during annealing) can be used, in order to realize strong engagement. Then the operation layer that one of two SOI wafers of engineered substrates can be removed, can execute the second wafer bonding step later Engineered substrates to be engaged with the CMOS wafer for being formed with integrated circuit (IC) thereon.Second wafer bonding step can be used Relatively low temperature is to avoid the IC in damage CMOS wafer.Then the operation of the second SOI wafer of engineered substrates can be removed Layer, leaves diaphragm on the chamber of engineered substrates.Being electrically connected between CMOS IC and engineered substrates allows for controllable ultrasound Energy converter.

Above-mentioned wafer level process can produce the Vltrasonic device with integrated CMUT and CMOS IC.The chamber of CMUT can be with It is formed between two silicon layers of the silicon device layer for representing two SOI wafers for being used to form engineered substrates.However, in completion The operation layer of two SOI wafers can be not present in device, this is advantageously implemented thin plant bulk among other benefits, Therefore it is advantageously implemented small size.Therefore, in some respects, which may include for removing operation layer while allowing engineering The suitable step that substrate is engaged with CMOS wafer.The use of silicon perforation (TSV) can also be not present in resulting device, wherein Suitable alternative structure is for providing the electrical connection for reaching resulting ultrasonic transducer.

According to the another aspect of the application, body silicon wafer can be used to replace one or two of above-mentioned SOI wafer. In this case, the operation layer of chip is not removed, it can be for example using the erosion of the doped layer expression by body silicon wafer It carves barrier layer or uses timed-etch by wafer grinding to desired point.Therefore, using the combination of SOI or body silicon wafer or both Substantially the same structure may be implemented.

Therefore, the one aspect of the application provides a kind of wafer level process comprising by by SOI chip and body silicon Chip by between them there are chamber in a manner of be joined together to the first wafer bonding step of seal chamber, it is obtained to connect Closing structure is considered as engineered substrates.Relatively high temperature (such as during annealing) can be used, in order to realize strong connect It closes.Body silicon wafer can be carried out it is thinned, can execute later the second wafer bonding step with by engineered substrates with formed thereon There is the CMOS wafer of integrated circuit (IC) to engage.Relatively low temperature can be used to avoid damage in second wafer bonding step IC in CMOS wafer.Then the operation layer that the SOI wafer of engineered substrates can be removed, leaves film on the chamber of engineered substrates Piece.

According to the one aspect of the application, provide a method comprising: in the first silicon device of the first SOI wafer Multiple chambers are formed in silicon oxide layer on layer；Then first SOI wafer is engaged with the second SOI wafer to the first SOI Chip and second SOI wafer are annealed；And the operation layer and buried oxide layer (buried of removal first SOI wafer oxide layer).This method further includes that the first silicon device layer is bonded to the third crystalline substance for being formed at least one metal layer thereon Piece, and remove after the first silicon device layer is bonded to third wafer the operation layer of the second SOI wafer.

It according to the one aspect of the application, provides a method comprising by will be formed with open cavity One chip is engaged with the second chip, then forms the first wafer grinding to less than about 30 microns of thickness with multiple sealings The engineered substrates of chamber.This method further include no more than 450 DEG C at a temperature of engineered substrates are engaged with third wafer, and After engaging engineered substrates with third wafer, by the second wafer grinding to less than about 30 microns of thickness.In some implementations In scheme, the second chip or part of it are configured for use as the diaphragm of ultrasonic transducer, therefore its thickness after being thinned It is adapted to allow for vibrating.In contrast, in such a case, it may be desirable to which the first chip does not vibrate, therefore it is passed through after being thinned Thickness sufficiently large can be vibrated with minimizing or preventing.In another embodiment, the first chip and the second chip can be matched It is set to and is for example vibrated with different frequencies to generate multi-frequency transducers.For example, primary diaphragm may be configured in secondary diaphragm Centre frequency half at resonance.

It according to the one aspect of the application, provides a method comprising in the first silicon device layer of the first SOI wafer Upper formation silicon oxide layer, first SOI wafer include operation layer, bury oxygen (BOX) layer and with the back close to operation layer The first silicon device layer before face and separate operation layer.This method further include multiple chambers are formed in silicon oxide layer, and Second SOI wafer is engaged with the first SOI wafer, so that the second silicon device layer contact silicon oxide layer of the second SOI wafer is simultaneously Seal multiple chambers in the layer of Si oxide.This method further includes being bonded together by the first SOI wafer and the second SOI wafer It anneals later to the first SOI wafer and the second SOI wafer, annealing utilizes the temperature for being higher than 500 DEG C.This method further include: Remove the operation layer of the first SOI wafer；Multiple grooves are etched in the first silicon device layer, multiple groove limits the first silicon device The multiple electrodes region corresponding to multiple chambers of layer；And multiple grooves are filled with insulating materials.This method further includes first Metal contact element is formed on the back side of silicon device layer, at least some metal contact elements correspond to multiple electrodes region.This method is also Including using the metal contact element on the back side of the first silicon device layer to make the first silicon device layer and being formed with integrated circuit CMOS wafer engagement, to contact the junction in CMOS wafer, wherein being bonded on the first silicon device layer with CMOS wafer 450 DEG C performed below.This method further includes the operation layer for removing the second SOI wafer.

According to the one aspect of the application, a kind of device is provided comprising: the CMOS for being formed with integrated circuit is brilliant Piece；And with CMOS wafer single-chip integration and including the substrate less than three silicon layers.The of first silicon layer of substrate and substrate Two silicon layers are arranged to has multiple chambers therebetween.

According to the one aspect of the application, a kind of device is provided comprising: the CMOS for being formed with integrated circuit is brilliant Piece；And with the single chip integrated substrate of CMOS wafer, the substrate has close to the first side of the CMOS wafer and separate Second side of CMOS wafer.Substrate successively includes the first silicon layer, the first silicon layer of direct contact to second side from the first side and has The silicon oxide layer of multiple chambers formed therein, and directly contact Si oxide and form the film for being used for the multiple chamber Second silicon layer of piece.

According to the one aspect of the application, providing a kind of engage has the first chip and the second chip being bonded together Engineered substrates method.First chip has the isolated groove of the electrode zone of the first chip of isolation.This method comprises: having Redistributing layer is formed on integrated circuit (IC) chip for having IC；Solder bump array is formed on redistributing layer；And by engineering Substrate is engaged with IC wafer welding material projected block so that the first chip of engineered substrates the second chip of IC chip and engineered substrates it Between.First solder projection of solder bump array is in electrical contact the electrode zone of the first chip.

According to the one aspect of the application, a kind of device is provided comprising engineered substrates, the engineered substrates include engagement The first substrate and the second substrate together.First substrate has the isolated groove for limiting electrode zone.The device further includes tool There is IC in conjunction with the first substrate of engineered substrates and the integrated circuit including redistributing layer (IC) substrate.The device further include The solder bump array that the solder projection between the first substrate of formation and IC substrate on redistributing layer engages.Solder bump array The first solder projection be in electrical contact electrode zone.

As used herein term " SOI wafer " has its conventional sense, including operation layer, bury oxygen (BOX) layer and The silicon device layer of operation layer is isolated from by BOX layer.

Term as used herein " engineered substrates " refer to be designed to it is different from basic silicon wafer or standard SOI wafer Substrate.Engineered substrates are also possible to " compound substrate " by combining multiple and different elements (for example, multiple and different chips) to be formed.

Through present disclosure, unless the context requires otherwise, otherwise the use of term " about " includes " accurately ".Example Such as, distance is described as will be understood to comprise the case where wherein distance is less than 10 microns less than about 10 microns.

Detailed description of the invention

Multiple and different aspects and embodiment of the application are described with reference to the accompanying drawings.It should be understood that attached drawing is different It is fixed drawn to scale.The item appeared in multiple attached drawings is indicated by the same numbers in the attached drawing for occurring this.

Fig. 1 is changed according to the ultrasound integrated with CMOS wafer that is used to manufacture of the non-limiting embodiments of the application The flow chart of the manufacturing process of energy device.

The flow chart of the specific embodiment for the step of Fig. 2 is technique 100 for showing Fig. 1.

Fig. 3 is integrated according to the engineered substrates for including with having seal chamber of the non-limiting embodiments of the application CMOS wafer device sectional view.

Fig. 4 A to Fig. 4 T shows the device for being used to form Fig. 3 of a non-limiting embodiments according to the application With the consistent manufacturing process of manufacturing process of Fig. 1.

Fig. 5 is the sectional view with the device of Fig. 3 of other encapsulation.

Fig. 6 is the Vltrasonic device according to the feature of the device including Fig. 3 of the non-limiting embodiments of the application Top view.

Fig. 7 is changed according to the ultrasound integrated with CMOS wafer that is used to manufacture of the non-limiting embodiments of the application The flow chart of the manufacturing process of energy device, and the method including Fig. 1.

Fig. 8 A to Fig. 8 D shows the part in Fig. 4 A to Fig. 4 T of a non-limiting embodiments according to the application The change programme of manufacturing process.

Fig. 9 is shown according to the wherein super to limit using patterning doping of the non-limiting embodiments of the application The implementation of the device 300 of Fig. 3 of the electrode of sonic transducer.

Figure 10 is shown to be provided to according to the contact embedded wherein of the non-limiting embodiments of the application The change programme of the device 300 of Fig. 3 of the electrical connection of ultrasonic transducer diaphragm.

Figure 11 is shown to be provided to according to the contact embedded wherein of the non-limiting embodiments of the application The alternative of the device of the change programme and Figure 10 of the device 300 of Fig. 3 of the electrical connection of ultrasonic transducer diaphragm.

Figure 12 is shown according to unencapsulated Fig. 3's of the chamber in wherein ultrasonic transducer of a non-limiting embodiments The change programme of device 300.

Figure 13 is the reality for showing the isolated groove profile of the isolation ultrasonic transducer according to a non-limiting embodiments The top view of example.

Figure 14 is shown according to the non-limiting embodiments of the application as can be used for manufacturing engineering substrate Silicon wafer with TSV.

Figure 15 A to Figure 15 F, which is shown, is used to form the engineering with seal chamber according to non-limiting embodiments Substrate and the manufacturing process for engaging engineered substrates with circuit chip.

Figure 16 is shown to be included engineered substrates and utilize that be used for wafer scale attached according to non-limiting embodiments It is connected to the reconstructed wafer of the soldered ball preparation of the second chip.

Figure 17 shows Figure 15 E being provided only on a chip according to the wherein soldered ball of a non-limiting embodiments Device alternative.

Specific embodiment

Present aspects are related to the manufacture of CMUT and CMOS wafer and integrate, to form CMOS ultrasonic transducer (CUT).Described method provide can scale, low cost, the scheme of rate of good quality rate, to cope with use in commercial semiconductor Feasible technology integrates the challenge of CMUT and CMOS wafer in manufactory, to utilize the supply chain being easily obtained.Some In embodiment, instead of CMUT or other than CMUT, use piezoelectricity micro-machined ultrasonic transducer (PMUT).

According to the one aspect of the application, proposes and be related to the wafer level process of two wafer bonding steps, two chips At least one of engagement step can use wafer-class encapsulation technology.First wafer bonding step can be by will be on two insulators Silicon (SOI) chip is bonded together and forms seal chamber, and resulting connected structure is considered as engineered substrates, and is represented embedding Chamber SOI wafer.Relatively high temperature (such as during annealing) can be used, in order to realize strong combination.Then it can go Except one operation layer in two SOI wafers of engineered substrates, the second wafer bonding step can be executed later with by engineering Substrate is engaged with the CMOS wafer for being formed with integrated circuit (IC) thereon.Relatively low temperature can be used in second wafer bonding step It spends to avoid the IC in damage CMOS wafer.Then the operation layer of the second SOI wafer of engineered substrates can be removed.

In some embodiments, the engagement for being used to form the engineered substrates with seal chamber may include welding.One In a little such embodiments, engagement can execute at low temperature.However, it is possible to execute the annealing of relative high temperatures to ensure jail Solid combination.Because of the manufacturing engineering substrate before this structure and CMOS wafer is integrated, the manufacture of seal chamber with Heat budget (budget) separation of CMOS IC manufacture, therefore allow using the annealing of relative high temperatures without damaging resulting device In IC.

In some embodiments, the engagement executed will have the engineered substrates of seal chamber and CMOS wafer to integrate can Including hot compression (also referred herein as " hot pressing "), eutectic bonding or silicide bond (its be by make the silicon of a substrate with Metal on second substrate is contacted under enough pressure and temperatures to form metal silicide, and what generation mechanically and electrically engaged connects Close), as non-limiting embodiment.This combination can execute at temperatures sufficiently low, to avoid in damage CMOS wafer IC, while strong engagement is still provided and the electricity of the seal chamber that additionally aids the IC in CMOS wafer and engineered substrates mutually Even.Therefore, many aspects of the application realize that low temperature (for example, being lower than 450 DEG C) chip engagement is super to be formed on a cmos wafer Sonic transducer diaphragm.In some embodiments, low temperature can be lower than 450 DEG C, be lower than 400 DEG C, be lower than 350 in this background DEG C, between 200 DEG C and 450 DEG C, any temperature within the scope of this or any conjunction for protecting the structure in CMOS wafer Suitable temperature.Therefore, joint technology and can to form other manufacturing steps of CUT for integrating seal chamber and CMOS IC Avoid any annealing higher than 450 DEG C.

According to the one aspect of the application, device including engineered substrates and the CMOS wafer for being formed with CMOS IC thereon Engagement.Engineered substrates may include being bonded together to form multiple chips of seal chamber.Then can by engineered substrates with CMOS wafer engagement.Engineered substrates may include be configured for use as vibration diaphragm a substrate and be used as supporting member and Its another substrate for being not intended to vibration.Latter substrate can sufficiently thick (for example, greater than about 5 microns) to prevent undesirable vibration It is dynamic, but also sufficiently thin (for example, being less than about 30 microns) to facilitate small plant bulk.

According to the one aspect of the application, device including engineered substrates and the CMOS wafer for being formed with CMOS IC thereon Engagement, and engineered substrates include the multiple chips being bonded together to form seal chamber and be configured to vibrate.Engineered substrates A chip may be configured to first frequency resonance, and the second chip of engineered substrates may be configured to difference Frequency resonance.Therefore, multiple frequency ultrasonic energy converter can be created.As a non-limiting embodiment, a frequency can be used It is operated in sending, and another frequency can be used for receiving operation.For example, first is lower as a non-limiting embodiment Frequency can be used for sending operation, and the second upper frequency (for example, twice frequency of lower frequency) can be used for receiving Operation.

Aspects described above and embodiment described further below and other aspect and embodiment.These sides Face and/or embodiment can be used alone, all be used together or in the form of two or more any combination It uses, because the application is not limited to this respect.

As described, present aspects are provided for manufacturing with integrated CMUT and CMOS IC and utilizing Two individually in conjunction with the technique of the CUT of step.It includes relatively thin engineered substrates, the work that the technique, which can permit resulting structures, Journey substrate be formed in and thereon with CMOS IC single chip integrated two silicon layers of CMOS wafer between chamber.Fig. 1 shows One embodiment of technique is gone out.

As shown, method 100 can start at step 102, the engineered substrates with seal chamber are formed.Two SOI Chip can be combined together, such as the silicon device layer of two SOI wafers is facing with each other.One or two in two SOI wafers It is a to can have multiple chambers formed therein, CMUT is suitable as so that two SOI wafers are bonded together can produce Chamber seal chamber.In order to ensure the strong engagement between two SOI wafers, high-temperature process can be used.For example, can be in low temperature Chip uses high annealing after engaging (such as low-temperature welding).Therefore, in some embodiments, engineering lining can formed The combination of high temperature and low temperature is used during bottom.In some embodiments, high temperature in this context can be higher than 450 DEG C, It would generally be damaged higher than temperature threshold CMOS IC.

The engagement of two SOI wafers can carry out in a vacuum, so that obtained seal chamber has low pressure (for example, pressure About 1 × 10^-3Support and about 1 × 10^-5Between support, pressure be less than about 1 atmospheric pressure or other any suitable pressure).One In a little embodiments, engaged in an inert atmosphere, such as use N₂。

At step 104, in any suitable manner, such as by the combination of grinding then etching two can be removed First operation layer in SOI wafer.Therefore, technique on this point, engineered substrates may include three silicon layers: first The operation layer of the silicon device layer of SOI wafer, the silicon device layer of the second SOI wafer and the second SOI wafer.Although the silicon of SOI wafer Device layer can be it is thin, such as with a thickness of 20 microns or smaller (for example, 10 microns, 5 microns, 2.5 microns, 2 microns, it is 1 micro- Rice is smaller, including any range or value in the range of less than 20 microns), but the applicants have appreciated that, the 2nd SOI The operation layer of chip can provide enough structure supports to allow the further processing to engineered substrates.

At step 106, engineered substrates can be engaged with the CMOS wafer with integrated circuit to form integrating device.It can With lower than 450 DEG C at a temperature of executes engagement, with prevent damage CMOS chip circuit.In some embodiments, wherein Using hot press, although the alternative including eutectic bonding and silicide bond etc. is also possible.Such as by by The back side of the silicon device layer of one SOI wafer is engaged with CMOS wafer, the silicon device layer of the first SOI wafer can be arranged in CMOS Near the engagement surface of chip.Therefore, obtained structure can successively include CMOS chip, the first silicon device layer, second Second silicon device layer of SOI wafer and the operation layer of the second SOI wafer.

At step 108, in any suitable manner, such as by grinding and then the combination of etching, engineering can be removed The operation layer of second SOI wafer of substrate.Therefore, in some embodiments, engineered substrates can be only including being chamber therebetween Two silicon layers (two silicon device layers for being used to form the SOI chip of engineered substrates).Only tool can contribute to there are two silicon layer The advantages that realizing the thin size of engineered substrates.For example, engineered substrates at this stage can be relatively thin, such as overall thickness is less than 100 microns, overall thickness less than 50 microns, overall thickness less than 30 microns, overall thickness less than 20 microns, overall thickness less than 10 microns (for example, about 8 microns or about 5 microns) or other any suitable thickness.Structure with this small thickness lacks enough knots Structure rigidity be subjected to include chip engage many manufacturing process.Therefore, according to some embodiments of the application, engineered substrates Until being just reduced to such size until engaging with CMOS wafer, CMOS wafer can provide machinery for engineered substrates Bearing.In addition, as further described below with reference to Fig. 7, in some embodiments it is preferred that ground, two crystalline substances of engineered substrates A chip in piece is sufficiently thick, to minimize or prevent the vibration of chip.Therefore, although engineered substrates can be it is thin, It is its thickness that can have for example, at least 4 microns in some embodiments, there are at least 5 microns in some embodiments Thickness, in some embodiments at least 7 microns of thickness, in some embodiments at least 10 microns of thickness It spends or other is to prevent the undesirable suitable thickness vibrated.

It can be electrically connected between IC on a cmos wafer and the seal chamber of engineered substrates, to provide effective ultrasound Energy converter.For example, the silicon device layer of the close CMOS wafer of engineered substrates may be used as the hearth electrode of ultrasonic transducer, and it is separate The silicon device layer of CMOS wafer may be used as diaphragm, and these structures can be carried out with suitable electrical connection to control diaphragm Operation (for example, activating diaphragm (or the vibration for causing diaphragm) by applying voltage).In some embodiments, can pass through The engagement of step 106 is electrically connected to carry out (or can be at least partly completed).For example, connecing engineered substrates with CMOS wafer Close the conductive bonding material (for example, metal) that can be related to using both bond material and electrical connection is used as.Alternatively or separately Other places can be electrically connected after engaging engineered substrates with CMOS wafer.For example, engineered substrates and CMOS wafer are connect Conjunction can be formed to the electrical connection of the hearth electrode of ultrasonic transducer, and can be subsequently formed metal on chip and be interconnected and/or draw Wire bonding is electrically connected with providing with the diaphragm of ultrasonic transducer or top electrode.

Fig. 2 provides the further details of the embodiment of the implementation of the step 102 about method 100 it should be appreciated that , the alternative for implementation steps 102 is possible.It in the non-limiting illustrated embodiment, can be by first Chamber is formed in thermal oxide (oxide formed by thermal oxide) on first in two SOI wafers to form engineering The chamber of substrate.That is, the first SOI wafer may include operation layer (for example, operation silicon layer), bury oxygen (BOX) layer and silicon device Part layer can form thermal oxide and carrying out thermal oxide to silicon device layer at step 202 in silicon device layer.It should manage Solution, thermal oxide represents a non-limiting embodiment of oxide, and can alternatively be formed other kinds of Oxide.

It, can be for example by being formed in any appropriate thermal oxide for being etched in the first SOI wafer at step 204 Chamber.In some embodiments, chamber is not completely to silicon device layer, so that (thin) oxide skin(coating) limits chamber boundary.However, In other embodiments, chamber extends to the surface of silicon device layer or further extends.It in some embodiments, can be with Thermal oxide is etched into the surface of silicon device layer, then can form other thermal oxide layer, so that being limited by oxide skin(coating) Determine chamber.

At step 206, have the first SOI wafer of the chamber in the thermal oxide being formed thereon can be for example using low Warm welding is engaged with the second SOI wafer.In some embodiments, the second SOI wafer includes operation layer (for example, operation silicon Layer), BOX layer and silicon device layer, and the engagement is related to making the silicon of the thermal oxide layer of the first SOI wafer and the second SOI wafer Device layer is directly contacted, to form Si-SiO₂Engagement.In alternative embodiment, the second SOI wafer may include Oxide skin(coating) in silicon device layer, so that the first SOI wafer and the second SOI wafer, which are bonded together, can be related to and two The oxide skin(coating) of SOI wafer directly contacts, to form SiO₂-SiO₂Engagement.

As by two SOI wafers be bonded together as a result, the chamber in the first SOI wafer can be sealed.For example, one In a little embodiments, chamber can be vacuum-packed, but can not form vacuum sealing in other embodiments.

At step 208, annealing can be executed to promote the formation engaged by force between two SOI wafers.As previously mentioned, In some embodiments, annealing can be high annealing, for example, about 500 DEG C with about 1500 DEG C (such as 500 DEG C, 750 DEG C, 1000 DEG C, 1250 DEG C) between carry out, including in the range any temperature or temperature range (such as about 500 DEG C with about Between 1200 DEG C), but can alternatively use other temperature.In some embodiments, can about 300 DEG C with about It anneals between 1200 DEG C.

Fig. 3 is integrated according to the engineered substrates for including with having seal chamber of the non-limiting embodiments of the application CMOS wafer Vltrasonic device sectional view.Device 300 can be formed by implementing the method for Fig. 1 to Fig. 2.

Device 300 includes the engineered substrates 302 integrated with CMOS wafer 304.Engineered substrates 302 include being formed in first Multiple chambers 306 between silicon device layer 308 and the second silicon device layer 310.Silicon oxide layer 312 is (for example, the thermal oxide for passing through silicon Hot Si oxide-the Si oxide formed) it can be formed between the first silicon device layer 308 and the second silicon device layer 310, have Chamber 306 formed therein.In this nonlimiting, the first silicon device layer 308 can be configured as hearth electrode, and And second silicon device layer 310 can be configured as diaphragm.Therefore, the first silicon device layer 308, the second silicon device layer 310 and chamber 306 Combination can form ultrasonic transducer (for example, CMUT), wherein showing six in the non-limiting sectional view.In order to just In the operation as hearth electrode or diaphragm, one or two of the first silicon device layer 308 and the second silicon device layer 310 can be by It is doped to act as conductor, and is that high doped (is greater than 10 for example, having in some cases¹⁵A dopant/cm³Or more Big doping concentration).

Engineered substrates 302 can also include the oxide skin(coating) 314 on the top of the second silicon device layer 310, can be with table Show the BOX layer for being used to form the SOI of engineered substrates.In some embodiments, oxide skin(coating) 314 may be used as passivation layer, and And as shown, it can be patterned as being not present on chamber 306.It may include retouching on engineered substrates further below The contact 324 and passivation layer 330 stated.Passivation layer 330 can be patterned to allow close to (access to) one or more Multiple contacts 324, and can be formed by any appropriate passivating material.In some embodiments, passivation layer 330 by Si₃N₄It is formed, and in some embodiments by SiO₂And Si₃N₄Stacking formed, but alternative is possible.

Engineered substrates 302 can be bonded together with CMOS wafer 304 at binding site 316a and 316b.Junction can be with It indicates eutectic bonding point, such as is total to by what the eutectic bonding of the layer on engineered substrates 302 and the layer in CMOS wafer 304 was formed Brilliant junction, or can be other any suitable bond types as described herein (for example, silicide bond or thermo-compression bonding It closes).In some embodiments, binding site 316a and 316b can be conduction, such as be formed by metal.In some embodiment party In case, binding site 316a can be used only as binding site, and in some embodiments, and binding site 316a can form such as gas The thickly sealing ring of the ultrasonic transducer of sealing device 300, as further described below with reference to Fig. 6.In some embodiments In, binding site 316a, which can be limited, also provides the sealing ring of the electrical connection between engineered substrates and CMOS wafer.Similarly, one In a little embodiments, binding site 316b can be used for dual purpose, be used for example as binding site, and also provide engineered substrates 302 Ultrasonic transducer and the IC of CMOS wafer 304 between be electrically connected.Wherein engineered substrates do not engaged with CMOS wafer with Under will be described in the embodiment of embodiment, junction 316b can provide appointing on the substrate in conjunction with engineered substrates The electrical connection of what electric structure.

CMOS wafer 304 includes basal layer (such as body silicon wafer) 318, insulating layer 320 and metallization (metallization)322.Metallization 322 can be formed by aluminium, copper or other any suitable metallization materials, and can To indicate at least part for the integrated circuit being formed in CMOS wafer.For example, metallization 322 may be used as wiring layer (routing layer), can be patterned to form one or more electrodes, or can be used for other function.In reality In trampling, CMOS chip 304 may include the redistributing layer of multiple metalization layers and/or post-processing, but for simplicity, Illustrate only single metal part.

Binding site 316b can provide the metallization 322 of CMOS wafer 304 and the first silicon device layer 308 of engineered substrates Between electrical connection.In this way, the integrated circuit of CMOS wafer 304 can be with the ultrasonic transducer electrode of engineered substrates And/or diaphragm is communicated (for example, be sent to it electric signal and/or receive from it electric signal).In the embodiment illustrated, Individual junction 316b is illustrated as being provided to the electrical connection of each seal chamber (and being accordingly used in each ultrasonic transducer), But not all embodiment is limited to this mode.For example, in some embodiments, the number of provided electrical contact Mesh can be less than the number of ultrasonic transducer.

In this nonlimiting, the electrical contact of the ultrasonic transducer diaphragm indicated by the second silicon device layer 310 by Contact 324 provides, and contact 324 can be formed by metal or other any suitable conductive contact materials.In some implementations In scheme, electrical connection can be provided between the landing pad 326 on contact 324 and CMOS wafer.Draw for example, can provide Wire bonding 325 can deposit conductive material (for example, metal) on the upper surface of device, and pattern with formed from Contact 324 arrives the conductive path of landing pad 326.However, it is possible to use contact 324 is connected in CMOS wafer 304 IC alternative mode.In some embodiments, it can provide from 308 to the second silicon device layer of the first silicon device layer The embedded through-hole of 310 bottom side, therefore avoid any need of the contact 324 on the top side to the second silicon device layer 310 It wants.Embodiment is described below in conjunction with Figure 11.In such embodiments, it is suitable to provide relative to any this through-hole It is electrically isolated, to avoid the first silicon device layer and the second silicon device layer electric short circuit is made.

Device 300 further include be configured as be electrically isolated ultrasonic transducer group (referred to herein as " ultrasound transducer element ") or The isolation structure (for example, isolated groove) 328 of person's individual ultrasonic transducer as shown in Figure 3.In some embodiments, every From the groove filled with insulating materials that structure 328 may include by the first silicon device layer 308.Alternatively, such as following knot It closes what Fig. 9 was further described, isolation structure 328 can be formed by doping appropriate.Isolation structure 328 is optional.

The various features of device 300 are pointed out now.For example, it should be appreciated that engineered substrates 302 and CMOS wafer 304 Chip can be with single-chip integration, to provide the single-chip integration of ultrasonic transducer Yu CMOS IC.In the embodiment illustrated, surpass Sonic transducer is arranged with respect to CMOS IC vertical (or stacking), this can be by reducing integrated ultrasonic transducer and CMOS Chip area needed for IC promotes the formation of compact Vltrasonic device.

In addition, engineered substrates 302 include only two silicon layers 308 and 310, it is formed with chamber 306 therebetween.First silicon device layer 308 and second silicon device layer 310 can be thin, such as thickness is respectively less than 50 microns, thickness is less than less than 30 microns, thickness 20 microns, thickness less than 10 microns, be less than with a thickness of 5 microns, thickness less than 3 microns or with a thickness of about 2 microns and other Non-limiting embodiment.This size helps to realize small device, and can promote with ultrasonic transducer diaphragm (for example, Second silicon device layer 310) electrical contact without TSV.TSV is usually complicated and implementation cost is high, therefore avoids using them Manufacture yields can be improved and reduce installation cost.Many commercialization semiconductor manufacturing factories are needed not have in addition, forming TSV Standby special manufacture tool, therefore avoid the need for that this tool can be improved the supply chain for being used to form device, so that it If than using TSV having more commercial practicability.

Engineered substrates 302 as shown in Figure 3 can be relatively thin, such as overall thickness is micro- less than 50 less than 100 microns, overall thickness Rice, overall thickness are less than 30 microns, overall thickness less than 20 microns, overall thickness less than 10 microns or other any suitable thickness. The meaning of this thin size has just lacked structural intergrity above and cannot have been executed with the layer of this thin size various types of It is described in terms of the manufacturing step (for example, chip engagement) of type.Therefore, it is notable that can be in device 300 Realize this thin size.

In addition, silicon device layer 308 and 310 can be formed by monocrystalline silicon.It should be understood that the mechanically and electrically performance of monocrystalline silicon, therefore It can contribute to the design of ultrasonic transducer behavior using this material in ultrasonic transducer (for example, diaphragm as CMUT) And control.

Noticeable another feature is between the part and the first silicon device layer 308 of CMOS wafer 304 there are gap, Because the two engages at discrete junction 316b, rather than combined by the whole surface of covering CMOS wafer 304.Between being somebody's turn to do The meaning of gap is, if the first silicon device layer 308 is sufficiently thin, can vibrate.This vibration may not be desirable, example As indicated the undesirable vibration opposite with the expectation vibration of the second silicon device layer 310.Therefore, at least some embodiments In, it is beneficial to the first silicon device layer 308 is sufficiently thick to minimize or avoid this vibration.

In alternative embodiment, it may be desirable to which the first silicon device layer 308 and the second silicon device layer 310 are all vibrated. For example, they, which may be constructed such that, is presented different resonance frequencies, to generate multi-frequency device.In such as ultrasonic transducer Multiple resonance frequencies (harmonic wave can be referred to as in some embodiments) can be used in different operating states.For example, first Silicon device layer 308 may be configured to the resonance at the half of the centre frequency of the second silicon device layer 310.

Fig. 4 A to Fig. 4 T shows the manufacturing process one with Fig. 1 of a non-limiting embodiments according to the application The manufacturing process of the device 300 for being used to form Fig. 3 caused.Previously retained phase in Fig. 4 A to Fig. 4 T in conjunction with the structure of Fig. 3 description Same appended drawing reference.

Initially, the formation of engineered substrates has been illustrated starting at the first SOI wafer 400 as shown in Figure 4 A.SOI wafer 400 Including operation layer 402 (for example, silicon operation layer), BOX layer 404 and the first silicon device layer 308.Oxide skin(coating) 405 also can be set At the back side of operation layer 402.

First silicon device layer 308 can be formed by monocrystalline silicon, and be mixed as previously mentioned, can be in some embodiments Miscellaneous.As previously described in connection with figure 3, the first silicon device layer 308 may be used as the hearth electrode of ultrasonic transducer, therefore suitable Doping desired electric behavior can be provided.In addition, in some embodiments, avoiding use using doping silicon device layer The needs of TSV.In some embodiments, the first silicon device layer 308 can be the p-type of high doped, although also can be used N-type doping.When using doping, doping can be uniform or can be patterned (such as by injecting pattered region In), for example, such as below with reference to Fig. 7 further describe to provide isolation electrode.First silicon device layer 308 can obtain It is doped when SOI wafer, or can be adulterated by ion implanting, because the mode of doping is not limiting.

In some embodiments, the first silicon device layer 308 can be formed by polysilicon or amorphous silicon.In either case Under, the first silicon device layer 308 can optionally be doped or not be doped to provide desired electrical property.

As shown in Figure 4 B, silicon oxide layer 312 can be formed in SOI wafer 400.Silicon oxide layer 312 can be used for The chamber 306 of ultrasonic transducer is at least partially defined, and can have any appropriate thickness therefore to provide desired chamber Depth.Silicon oxide layer 312 can be hot Si oxide it should be appreciated that can be alternatively using except thermal oxide Oxide except object.

Fig. 4 B, which is also shown, can form alignment mark 406 (for example, the appropriate patterning for passing through oxide skin(coating) 405).Such as By what is further illustrated below in conjunction with Fig. 4 E, because to remove operation layer 402, alignment mark 406 can be transferred to later Second SOI wafer.

As shown in Figure 4 C, any appropriate technology (for example, using suitable etching) can be used to silicon oxide layer 312 are patterned to form chamber 306.In this non-limiting example embodiment, chamber 306 does not extend to the first silicon device layer 308 Surface, although they are the surfaces for extending to the first silicon device layer 308 in alternative embodiment.In some implementations In scheme, silicon oxide layer 312 can be etched into the surface of silicon device layer, then can form other oxide skin(coating) (example Such as, hot Si oxide) so that limiting chamber by oxide skin(coating).In some embodiments, chamber extends to the first silicon device layer In 308.In addition, in some embodiments, it can be in the intracavitary structure for forming such as insulated column.

The chamber 306 of any suitable number and construction can be formed, because many aspects of the application are not limited in this respect System.Therefore, although showing only six chambers 306 in the non-limiting sectional view of Fig. 4 C it should be appreciated that one It can be formed in a little embodiments more.For example, the array of chamber 306 may include hundreds of chambers, thousands of chambers or more, To form the ultrasound transducer array of desired size.

Chamber 306 can have the desired operation (for example, for operating frequency) for finally formed ultrasonic transducer And the depth D designed.In some embodiments, depth D can be about 2 microns, about 0.5 micron, about 0.25 micron, about Between 0.05 micron to about 10 microns, between about 0.1 micron to about 5 microns, between about 0.5 micron to about 1.5 microns, therebetween Any depth or depth bounds or other any suitable depth.

Chamber 306 can have width W, also be shown in FIG. 3.The non-limiting embodiment of the value of W is described further below. Width dimensions can be also used for the aperture size of identification chamber, therefore chamber 306 can have in the value herein for width W description Any value aperture.

When ultimately forming ultrasonic transducer, chamber 306 can take one of various shape (from top side) to provide Desired diaphragm shapes.For example, chamber 306 can have circular contour or polygonal profile (for example, rectangular profile, hexagon wheel Wide, octagonal profile).As described below, the embodiment of circular contour is shown in FIG. 13.

As shown in Figure 4 D, the first SOI wafer 400 can with include the second operation layer (for example, silicon operation layer) 410, oxidation The engagement of second SOI wafer 408 of nitride layer 314 (for example, BOX layer) and the second silicon device layer 310.Second SOI wafer 408 can be another Other places includes oxide skin(coating) 414.The engagement can execute (for example, be lower than 450 DEG C welding) at low temperature, but then can be with Annealing is at high temperature (for example, in the case where being greater than 500 DEG C) to ensure enough bond strengths.In the first silicon device layer 308 and/or Two silicon device layers 310 those of are doped in embodiment, and annealing can be used for activation doping, it means that single anneal can To execute multiple functions.In the embodiment illustrated, engagement can be Si-SiO₂Engagement, although alternative is possible. For example, in some embodiments, the second SOI wafer 408 may include the oxide skin(coating) (example in the second silicon device layer 310 Such as, hot Si oxide) so that the engagement between the first SOI wafer 400 and the second SOI wafer 408 can be SiO₂-SiO₂It connects It closes.

As the first silicon device layer 308, the second silicon device layer 310 can be monocrystalline silicon, polysilicon or amorphous silicon, and It can be doping in some embodiments.Doping can avoid the formation of TSV to provide the needs of electrical connection, and can be with It is any appropriate type and level.

As shown in Figure 4 E, alignment mark 406 can be transferred to the second SOI wafer as alignment mark 416.

Then, as illustrated in figure 4f, oxide skin(coating) 405, operation layer 402 and BOX layer can be removed in any suitable manner 404.It is, for example, possible to use grinding, etching or the combinations of other any suitable technologies or technology.Therefore, from the first SOI wafer The 400 only layers left include the first silicon device layer 308 and silicon oxide layer 312.As previously described in conjunction with Figure 3, this A little layers can be thin.However, because they are bonded to the second SOI wafer 408 with its corresponding operation layer, it is possible to keep Enough structural intergrities are for further processing.

Described by the isolation structure 328 of Fig. 3 as previously explained, in some embodiments, it may be desirable to be electrically isolated device 300 one or more ultrasonic transducers.Thus, as shown in Figure 4 G, can be formed in the first silicon device layer 308 one or More isolated grooves 418.In the embodiment illustrated, isolated groove 418 extends to silicon oxygen from the back side of silicon device layer 308 Compound layer 312, and (in the accompanying drawings along direction from left to right) than each isolated groove 418 contact on cover Si oxide The part of layer 312 is narrow, enters chamber 306 to prevent from penetrating unintentionally silicon oxide layer 312.Therefore, isolated groove 418 does not influence chamber 306 structural intergrity.However, alternative construction is possible.

Fig. 4 H, which is shown, can be used any appropriate technology (for example, suitable deposition) with insulating materials 420 (for example, silicon Oxide) filling isolated groove 418.It should be noted that in the embodiment illustrated, insulating materials 420 be filled up completely every From groove 418, rather than it is simply 418 lining of groove (line), this can further help in the knot of device at this stage Structure integrality, makes it more suitable for being further processed.

In Fig. 4 I, such as using any appropriate deposition and patterning techniques, on the lower surface of insulating materials 420 Optionally form flow barrier feature 422.Flow barrier feature can execute one or more functions.For example, they can be with Prevent the undesirable flowing of the metal layer then deposited.Alternatively or additionally, flow barrier feature can be provided in it Desired gap when engaging afterwards between engineered substrates and CMOS wafer.It is, therefore, possible to provide flow barrier feature 422 Any suitable number and positioning are to realize one or two function, and flow barrier feature 422 can be by any appropriate material Material is formed.For example, in some non-limiting embodiments, flow barrier feature 422 can be formed by silicon nitride (SiN).So And as described above, the use of flow barrier feature 422 is optional.For example, in some embodiments, such as when using hot Compression is come when engaging engineered substrates with another chip, it is convenient to omit this feature.

As shown in fig. 4j, insulating materials 420 can be patterned (using any appropriate etching technique) to prepare Form the bonding station for then engaging engineered substrates with CMOS wafer.In addition, patterning can further limit previous knot Close the isolation structure 328 of Fig. 3 description.

In Fig. 4 K, the first silicon device layer 308, silicon oxide layer 312, the second silicon device layer 310 and oxidation can be passed through Nitride layer 314, which is formed, removes region 424.Removing region 424 can make ultrasonic transducer group be isolated from each other (for example, separating different Ultrasound transducer array), as further described below in conjunction with Fig. 6.For example, in some embodiments, the first silicon device Layer 308 and second silicon device layer 310 be retained in the region for corresponding only to ultrasound transducer array, wherein remove region 424 every Open ultrasound transducer array.Removing region 424 can make it easier to close to the CMOS at the periphery of ultrasound transducer array Chip, such as allow close to landing pad or other electrical connection features.Removing region 424 can shape in any suitable manner At, such as use grinding, deep reactive ion etching (DRIE) and the plasma for etching silicon device layer and oxide skin(coating) One of etching or more.In some embodiments, using grinding, followed by DRIE.It is formed and removes replacing for region 424 Mode is selected to be possible.

Then grafting material 426 can be formed on engineered substrates, to prepare to engage engineered substrates with CMOS wafer, As illustrated in fig. 4l.The type of grafting material 426 can depend on the type of engagement to be formed.For example, grafting material 426 can be with It is adapted for the metal of hot press, eutectic bonding or silicide bond.In some embodiments, grafting material can be conduction , electric signal is transmitted between engineered substrates and CMOS wafer, as retouched above in conjunction with Fig. 3 and junction 316b It states.For example, in some embodiments, grafting material 426 can be gold, and can be formed by plating.In some realities It applies in scheme, the material and technology for wafer-class encapsulation can be applicable in the background for engaging engineered substrates with CMOS wafer. The metal stack of desired adherency, mutual diffusion barrier functions and high bond quality is provided thus, for example, can be used and be selected as Body, and grafting material 426 may include this metal stack body.

Fig. 4 M to Fig. 4 P is related to the preparation of the CMOS wafer 304 for engaging with engineered substrates.As shown in fig. 4m, CMOS is brilliant Piece 304 includes basal layer (such as body silicon wafer) 318, insulating layer 320 and metallization 322.Insulating layer 428 can be with optional landform At on the back side of basal layer 318.

As shown in Fig. 4 N, layer 430 and 432 can be formed in CMOS wafer 304.Layer 430 can be such as nitride Layer, and can be formed by plasma enhanced chemical vapor deposition (PECVD).Layer 432 can be oxide skin(coating), such as It is formed by the PECVD of oxide.

In Fig. 4 O, the opening 434 from layer 432 to metallization 322 can be formed.Such opening can be prepared to be used for Form junction.For example, in Fig. 4 P, (deposition appropriate and patterning can be passed through) in CMOS wafer 304 at one or Multiple suitable positions form grafting material 436, for engaging engineered substrates 302 with CMOS wafer 304.Grafting material 436 can be any appropriate material for engaging with the grafting material 426 on engineered substrates.As previously mentioned, some In embodiment, low temperature eutectic engagement can be formed, and in such an implementation, grafting material 426 and grafting material 436 Eutectic pair can be formed.For example, grafting material 426 and grafting material 436 can form indium-tin (In-Sn) eutectic to, Jin-tin (Au-Sn) eutectic to and aluminium-germanium (Al-Ge) eutectic to or tin-silver-copper (Sn-Ag-Cu) combine.The Sn-Ag-Cu the case where Under, two kinds of materials can be formed on engineered substrates as grafting material 426, remaining material is formed as grafting material 436.

As shown in Fig. 4 Q, then engineered substrates 302 and CMOS wafer 304 can be bonded together, this is in some implementations Generating in scheme includes the seal chamber 306 being vertically set on above the IC in CMOS wafer 304 (for example, metallization 322) Monolithic integrated structure.As previously mentioned, in some embodiments, this engagement can be only related to using low temperature (for example, being lower than 450 DEG C), this can prevent metalization layer and other component in damage CMOS wafer 304.

In the non-limiting illustrated embodiment, engagement can be eutectic bonding, so that grafting material 426 and engagement material Material 436 may be combined to form junction 316a and 316b.As another non-limiting embodiment, Au can be used as engagement material Material is to form hot press.For example, grafting material 426 may include the seed layer for being formed with the Ti/TiW/Au of plating Au thereon (being formed by sputtering or other methods), and grafting material 436 may include the TiW/Au for being formed with coating Ni/Au thereon Seed layer (by sputtering or other methods formed).Titanium layer may be used as adhesion layer.TiW layers may be used as adhesion layer and diffusion Barrier layer.Nickel may be used as diffusion barrier layer.Au can form engagement.Other grafting materials can alternatively be used.

Next, the second operation layer 410 and oxide skin(coating) can be removed in any appropriate mode as shown in Fig. 4 R 414.It is, for example, possible to use grinding and/or etchings.Oxide skin(coating) 314 may be used as the etching for removing the second operation layer 410 Barrier layer.

Then, as shown in fig. 4s, can be used any appropriate etching technique to oxide skin(coating) 314 patterned with Form opening 438.Opening 438 provides connecing to the back side (or the top side) of the separate CMOS wafer 304 of the second silicon device layer 310 Closely.It, then can be for example by depositing and patterning suitable conductive material (for example, aluminium, copper or other are suitable as shown in Fig. 4 T Material) form the contact 324 and landing pad 326 of Fig. 3.Furthermore, it is possible to optionally be gone from the region of covering chamber 306 Except (in any suitable manner) oxide skin(coating) 314.That is, deoxygenation can be gone from the ultrasonic transducer region of Vltrasonic device Compound layer 314.

It may then pass through deposition and patterned passivation layer 330 carry out realization device 300.As previously described in conjunction with Figure 3, Passivation layer 330 can be patterned to provide to the close of one or more contacts 324.

The various features of the manufacturing process of Fig. 4 A to Fig. 4 T are paid attention to now.For example, it should be appreciated that manufacturing process does not relate to And the use of TSV, if so that the process costs are lower compared with using TSV the case where and complexity is lower.Therefore, may be used To improve the yields of this method.

In addition, this method is without using chemically mechanical polishing (CMP).For example, in preparing any zygophase not Using CMP, therefore compared with executing CMP step, joint reliability (and therefore improving yields) can be increased, while can drop Low cost.Similarly, it is notable that shown in manufacturing process do not include being connect for the low temperature of engineered substrates and CMOS wafer Any densification anneal closed.The use of this annealing reduces joint reliability and therefore reduces yields.In addition, as before Described, the manufacture of the seal chamber for ultrasonic transducer is separated with CMOS heat budget, therefore is allowed by the chip of engineered substrates High-temperature process (for example, high annealing) is used when being bonded together.

The technique for being used to form seal chamber 306 can also contribute to being formed the chamber with desired size and interval.For example, Chamber 306 can have about 50 microns, about 5 microns to about 500 microns, about 20 microns to about 100 microns, any width therebetween Or the width W of width range or other any suitable width (referring to Fig. 3 and Fig. 4 C).In some embodiments, Ke Yixuan Width W is selected so that void fraction (ratio for the amount of area that the amount of area that i.e. chamber occupies is occupied with surrounding structure) maximizes.Chamber 306 Can have about 2 microns, about 0.5 micron, about 0.25 micron, about 0.05 micron to about 10 microns, about 0.1 micron to about 5 it is micro- Rice, about 0.5 micron to about 1.5 microns, any depth therebetween or depth bounds, or the depth D of other any suitable depth (see Fig. 4 C).In some embodiments, chamber has about 50 microns of width W and about 0.2 micron of depth D.In some implementations In scheme, the ratio of width W and depth D can be greater than 50, be greater than 100, is greater than 150, between 30 and 300, or other any conjunctions Suitable ratio.Ratio be can choose to provide the desired operation of energy converter diaphragm, such as the operation under target frequency.

Despite the fact that the amount of space between epicoele 306 influences engageable region when forming engineered substrates, but between chamber 306 Interval can also be made smaller.That is, the distance between chamber 306 is smaller, available engagement surface is fewer, this increasing The difficulty of engagement is added.However, being formed herein in conjunction with engineering described in Fig. 1, Fig. 2, Fig. 4 A to Fig. 4 D and Fig. 7 (being described below) The technique (including forming chamber, low-temperature welding and high annealing in the oxide layer) of substrate, so that actually making chamber 306 tight It is thickly spaced apart, while still realizing the engineered substrates of high bond quality and yield.Typically, since the formation of engineered substrates is not By using the heat budget of technology described herein to be limited, thus using design rule so that engageable area between chamber 306 It minimizes aspect and provides flexibility.For example, method described herein can be used to realize less than 5 microns, less than 3 microns or be less than Interval between 2 microns and the chamber of other possibilities.

In some embodiments, device 300 further can be encapsulated and/or be packed.For example, as by Fig. 5 Shown by packaging system 500, device 300 can be cut and be engaged with substrate 506, substrate 506 can be circuit board, Plastic Package backing (backing) (for example, there is contact pin in some embodiments) or other substrates.Acoustic medium 502 can be set the ultrasonic transducer overlying regions in device 300.Acoustic medium by silicone resin, Parylene or can mention It is formed for any other materials of desired acoustic characteristic.Further encapsulation can be provided by sealant 504.As previously tied It closes described in Fig. 3, in some embodiments, wire bonding can be formed between contact 324 and landing pad 326, Such as wire bonding 325.Sealant 504 can be set to cover this wire bonding, with protect them from damage (therefore Wire bonding 325 is not shown in Fig. 5).Any appropriate encapsulating material can be used thus.It is understood, therefore, that Fig. 3 The mode that can be packaged, and encapsulate of device 300 do not limit multiple and different aspects of the application.

Fig. 6 shows the top view that can use a part of the Vltrasonic device of general structure of device 300.As shown , Vltrasonic device 600 includes the array of ultrasonic transducer 602, can correspond to previous CMUT described in conjunction with Figure 3.It is close Seal ring 604 can substantially or entirely surround ultrasonic transducer 602, but for simplicity, illustrate only sealing ring 604 A part.Sealing ring can be by previously combining the junction 316a of Fig. 3 description to be formed.In some embodiments, sealing ring 604 There is provided gas-tight seal, gas-tight seal is the sealing by the complete enclosing region of continual profile.In some embodiments, close Seal ring 604 provides the feature in engineered substrates and CMOS wafer (for example, the redistribution wiring layer in CMOS wafer, CMOS wafer On integrated circuit or other features) between electrical interconnection.In some embodiments, sealing ring 604 provide it is gas-tight seal and It is electrically interconnected.

The perimeter in sealing ring 604 previously can be set in conjunction with the removing region 424 of Fig. 4 K description.As shown , removing region 424 may include multiple and different features, such as landing pad 606, can correspond to the seam welding of Fig. 3 Disk 326.

The alternative of the manufacturing process of Fig. 4 A to Fig. 4 T is possible.For example, not being to form work using SOI chip Journey substrate 302, but one or more individual silicon wafers can be used.For example, the first SOI wafer 400 and/or the 2nd SOI are brilliant Piece 408 can be replaced with body silicon wafer.It the use of the reason of SOI wafer 400 and 408 is when removal operation layer 402 referring to Fig. 4 D When with 410, BOX layer 404 and 314 may be used as etch stop layer.It can use body silicon wafer and generated using suitable doping and mixed Diamicton realizes similar function.That is, body silicon wafer a part (for example, correspond to silicon device layer 308 or 310, and And with any thickness as described herein about these layers) can be doped so that the erosion lower than most silicon body chip is presented Etching speed.It is then possible to body silicon wafer is thinned from the back side (for example, etching), until in doped layer (that is, changing in doping Become the depth of etch-rate) at it is slack-off or effectively stop.In this way, doping gradient can effectively serve as etching blocking Layer, and most of body chip therefore can be removed, while only leaving desired part (for example, corresponding to silicon device layer 308 Or 310 doped layer).Alternatively, body silicon wafer can be used and be thinned to desired thickness using timed-etch.Fig. 4 A is extremely The rest part of the manufacturing process of Fig. 4 T can be carried out by about substantially similar way in a manner of using described in SOI wafer, Therefore the device 300 of manufacture Fig. 3 can be similarly used for.Using an advantage of body silicon wafer it is and SOI wafer in this way The cost relatively low compared to them.

From foregoing teachings, it should be appreciated that the method for Fig. 1 can be generalized to SOI wafer with being not particularly limited, such as Shown in Fig. 7.As shown, method 700 may begin at step 702, (can be wherein being formed and being had from the first chip SOI wafer or body silicon wafer) and the second chip (being also possible to SOI wafer or body silicon wafer) seal chamber engineered substrates.Cause This, it should be appreciated that the step 702 of method 700 can be related to two SOI wafers (as shown in Figure 1), two individual silicon wafers or The use of one SOI wafer of person and an individual silicon wafer.

One or two of two chips used in a step 702 can have multiple chambers formed therein, make It obtains for two chips to be bonded together and can produce the seal chamber for the chamber for being suitable as CMUT.In order to ensure between two chips Strong engagement, can be used high-temperature process.For example, can be moved back after low-temperature chip engages (such as low-temperature welding) using high temperature Fire.Therefore, in some embodiments, the combination of high temperature and low temperature can be used in forming engineered substrates.Such as combine Fig. 1 Described, in some embodiments, high temperature can be higher than 450 DEG C, will usually damage higher than temperature threshold CMOS IC It is bad.In addition, the engagement of two chips can carry out in a vacuum at step 702 as the engagement at step 102.

At step 704, change the thickness of the first chip.If the first chip is SOI wafer, the first chip is removed Operation layer.If the first chip is body silicon wafer on the contrary, for example it can be carried out by etching thinned.Timing can be used Etching or body silicon wafer may include the doping gradient as etch stop layer, as previously described herein.

As step 704 as a result, the first chip can have relatively small thickness.For example, after step 704 The thickness of one chip can less than 50 microns, less than 30 microns, less than 20 microns or less than 10 microns.As will be further retouched below It states, in some embodiments, the first chip will then be engaged with CMOS wafer, so that it is arranged in CMOS wafer and second Between chip.It can be with the CMOS wafer 304 and the first silicon device layer above for Fig. 3 between the first chip and CMOS wafer There are gaps for the mode of gap description between 308.Applicants have realized that the gap can if the first chip is too thin The first chip is allowed to vibrate.This vibration may not be desirable, such as be not intended to because it can be generated from ultrasonic transducer Harmonic wave.Therefore, Applicants have realized that, the first chip preferably should have enough thickness to provide rigidity, thus Avoid this undesirable vibration.Therefore, according to embodiment, step 704 is executed, so that the thickness of the first chip is at 4 microns With 50 microns between, between 5 microns and 30 microns, between 6.5 microns and 20 microns, between 8 microns and 15 microns, Or take any thickness or thickness range in such range.Although therefore the first chip can be thin, application People, which has realized that, can provide enough structure supports in step the second chip of method 700 to allow to engineered substrates Further processing.

At step 706, by with combine Fig. 1 step 106 description in a manner of same way, engineered substrates can with have The CMOS wafer of integrated circuit is engaged to form integrated device.First chip can be placed close to the table of joint of CMOS wafer Face, such as by engaging the back side of the first chip with CMOS wafer.Therefore, obtained structure can successively include CMOS brilliant Piece, the first chip and the second chip.As previously mentioned, according to the type of performed engagement, such as the first silicon as combined Fig. 3 Described in device layer 308 and CMOS wafer 304, there may be gaps between CMOS wafer and the first chip.

At step 708, change the thickness of the second chip.If the second chip is SOI wafer, with any appropriate side Formula, such as the combination then etched by grinding, remove the operation layer of the second chip of engineered substrates.If the second chip is opposite It is body silicon wafer, then for example it can be carried out by etching thinned.Timed-etch or body silicon wafer, which can be used, can wrap Include the doping gradient as etch stop layer.

Such as the method 100 of Fig. 1, in some embodiments, method 700 generates the engineering integrated with CMOS chip and serves as a contrast Bottom, wherein engineered substrates include only two silicon layers.This structure has previously in conjunction with the benefit of Fig. 1 description.

It can be electrically connected between IC on a cmos wafer and the seal chamber of engineered substrates, come to be retouched in conjunction with Fig. 1 The identical mode of the mode stated provides function ultrasonic transducer.

According to method 700, the alternative of the manufacturing process of Fig. 4 A to 4T is wherein to use a SOI wafer and one Body silicon wafer is come the embodiment that forms engineered substrates.Referring to Fig. 4 A, SOI chip 400 is had in its front surface and rear surface The body silicon wafer of oxide replaces.That is, the structure that Fig. 4 B can be used subtracts BOX layer 404.Then, with Fig. 4 C institute The identical mode of the mode shown can form chamber in the silicon oxide layer on the front of body silicon wafer.That is, because Body silicon wafer is used in the present embodiment, so the difference of embodiment shown in current embodiment and Fig. 4 C can be only It is that there is no BOX layers 404.

It then can be by the body silicon wafer bonding with chamber to SO1 chip, such as SOI wafer 408.Therefore, the present embodiment Can be only that with the difference of the structure of Fig. 4 D can be not present BOX layer 404.

Hereafter, the processing in the present embodiment can by with shown in Fig. 4 E to Fig. 4 T in a manner of identical mode carry out.

Another alternative of the manufacturing process of Fig. 4 A to Fig. 4 T, and itself and method are shown in conjunction with Fig. 8 A to Fig. 8 D 700 is consistent.Here, manufacture as shown in Figure 8 A starts from the SOI wafer 400 of Fig. 4 A.Next step shown in Fig. 8 B and Fig. 4 B The step of it is identical.

Next, as shown in Figure 8 C, forming chamber 806 in silicon oxide layer 312.Chamber 806 extends through silicon oxide layer 312, stop in the first silicon device layer 308.This construction can be stopped by being used as etching with wherein the first silicon device layer 308 The etching of layer is etched silicon oxide layer 312 to realize.The first silicon device layer 308 is used to facilitate as etch stop layer Accurately control the depth of chamber 806.

Next, as in fig. 8d, SOI wafer 400 (there is the chamber 806 for extending through silicon oxide layer 312) and body silicon Chip 808 engages.Body silicon wafer 808 include silicon layer 810, silicon layer 810 front surface on oxide skin(coating) 314 and in silicon layer Oxide skin(coating) 414 in 810 rear surface (or back side).It therefore, can be with seal chamber 806 in this stage of manufacture.

Hereafter, can by with shown in Fig. 4 E to Fig. 4 T in a manner of substantially similar way manufactured.That is, After the step shown in Fig. 8 D, alignment mark can be transferred to body silicon wafer.It then can be from the back side (from being provided with The side of oxide skin(coating) 414) body silicon wafer 808 is carried out it is thinned, with realize be similar to Fig. 4 F structure.Since the step, It identical mode can be handled through thinned body silicon wafer in a manner of the first silicon device layer 308 with Fig. 4 G to Fig. 4 T.

Various parameters associated with device be can choose to optimize the performance of device.The embodiment of these parameters includes chamber Depth D (being determined by the thickness of the silicon oxide layer 312 in the non-limiting embodiments of Fig. 8 D), oxide skin(coating) 314 thickness Degree, the width W of chamber, the pitch of chamber and resulting diaphragm thickness.For example, can choose the depth D and oxide skin(coating) 314 of chamber Thickness with the transmitting and receive capabilities of the model-based optimization ultrasonic transducer of the imagination, and also allows low voltage operating.As showing Example, the low frequency behaviour that can choose diaphragm thickness, chamber width and pitch to facilitate under high intensity focused ultrasound (HIFU) mode Make, and can be used for controlling the sensitivity and bandwidth of ultrasonic transducer.

Another alternative of the manufacturing process of Fig. 4 A to Fig. 4 T be related to corresponding to seal chamber 306 hearth electrode every From.As shown in figure 3, isolation structure 328 can be provided, and as combined shown by Fig. 4 G to Fig. 4 J, in some embodiments In, isolation structure 328 is the groove filled with insulating materials.However, it is possible to use the isolation structure of alternative, one of them includes The area of isolation formed by the first silicon device layer 308 of doping.That is, being formed at each position of expectation isolation Groove (for example, groove 418 in Fig. 4 G) but doping boundary can be used and substitute, such as it is one or more anti-to limit To biasing diode.One embodiment is shown in Fig. 9.

The device 900 of Fig. 9 indicates the implementation of the device 300 of Fig. 1, wherein doping boundary is for generating isolation structure 328.? In Fig. 9, the first silicon device layer 308 is shown to have three kinds of different types of regions for indicating doping difference.Region 902 indicates silicon The basis doping of material.Region 904 indicates electrode zone and adulterates on the contrary with region 902.Optional region 906 indicates tool There is dopant type identical with electrode zone 904 but there is the region compared with low doping concentration.As region 902 and 904 Phase contra-doping as a result, the isolation between electrode zone 904 can be generated by using suitable dopant patterns as shown, To generate pn-junction between electrode zone 904.In some embodiments, pn-junction can be reverse biased.

It is lightly doped n type that a kind of suitable doped scheme, which is region 902, and region 904 is heavy doping P type, and region 906 is P-type is lightly doped.However, region 902, which can be, is lightly doped p-type, and region 904 can be heavy doping N in alternative embodiment Type, region 906 can be lightly doped n type.In any case, boron may be used as P-type dopant, and phosphorus or arsenic may be used as N type dopant, but alternative is possible.The doping concentration that can choose region 902,904 and 906 is desired to provide Electric behavior.

The doping in region 902,904 and 906 can generate in any suitable manner.It, can be with according to some embodiments Use the combination of ion implanting and diffusion (for example, via high annealing).As shown in figure 9, region 904 and 906 can extend through The whole thickness of the first silicon device layer 308 is crossed, is had been noted above before thickness.In order to extend through doped region 904 and 906 Such thickness, can will be for example between 750keV, 1MeV, 500keV and 2MeV or up to the ion implanting and diffusion of 10MeV Annealed combination, the combination can be repeated in some embodiments, until doped region 904 and/or 906 extends through first Silicon device layer 308.However, because the injection of this high-energy can be penetrated into depth in the first silicon device layer 308, it is possible to In addition lower energy injection is used, to ensure that the first silicon device layer 308 of slight depth is also doped.It the energy of injection and moves back Fiery duration and temperature can depend on the type of used dopant, because some dopants can be than other dopants More easily reach bigger depth (for example, for identical given Implantation Energy, boron can inject deeper than phosphorus).

The size in region 902,904 and 906 be can choose to provide desired electrical property.For example, size can be optimised To reduce the parasitic capacitance for example between different electrode zones 904.Since region 904 indicates the electrode for corresponding to chamber 306 Region, it is possible to limit their size to provide desired electrode size.For example, region 904 can have substantially etc. In the width of the width W of chamber 306, but in alternative embodiment, region 904 can have the width W than chamber (referring to figure 3) small width, this may be beneficial to reduce dead (parasitism) capacitor.

As previously mentioned, region 906 is optional, therefore can be omitted in some embodiments.Region 906 can reduce Dead capacitor between electrode zone 904, and can have any appropriate size when included therefore to execute this function Energy.For example, in some embodiments, compared with the width of electrode zone 904, region 904 can be relatively large.Therefore, may be used With the position of control area 904 and 906 to provide desired size and the interval relative to chamber 306.

Region 902 can be electrically connected to any appropriate voltage.In some embodiments, region 902 can be floating 's.In other embodiments, region 902 may be constrained to (tied t_o) bias voltage.For example, region 902 can be It is electrically grounded when doped p-type, or may be constrained to high voltage (for example, high voltage rail) when doped N-type.In some embodiment party In case, as can ultrasonic imaging apply background used in, region 902 may be constrained to about 20 volts to 300 volts Between voltage (for example, between about 30 volts to 120 volts, between about 50 volts to 250 volts, between about 60 volts to 90 volts or at this The value of any value or any range in a little ranges), as non-limiting embodiment.In some embodiments, region 902 can It is identical (or substantially as the voltage of the second silicon device layer 310 of diaphragm of ultrasonic transducer to be biased in and for bias It is identical) voltage.

Although Fig. 9 shows the patterning doping of the first silicon device layer 308 it should be appreciated that patterning doping It can also be to be used for the second silicon device layer 310 with for identical mode in a manner of described in the first silicon device layer 308.Therefore, The ultrasonic transducer diaphragm of interconnection and doping can be formed in the second silicon device layer 310.For example, the second silicon device layer 310 Multiple isolated areas of higher-doped can more low-doped region alternating with identical dopant species.Other patterns are also can be with 's.

It those of is all doped in embodiment in wherein the first silicon device layer 308 and the second silicon device layer 310, Ke Yixuan The opposite doping between two layers is selected to provide desired electric behavior.For example, region 904 and the second silicon device layer 310 can phases Different concentration is adulterated and is doped into, instead to amplify bias voltage.For example, region 904 can be doping P+, and the second silicon Device layer 310 can be doping N-.This configuration can produce by the different work functions of N and P doping generate across chamber 306 Additional electric pressure drop (for example, 1 volt magnitude).If region 904 is doped to N-type, advantageously also by the second silicon device Layer 310 is doped to N-type, loses voltage drop to avoid due to work function.

Another alternative of the manufacturing process of Fig. 4 A to Fig. 4 T is related to the item that engineered substrates are bonded to.As for example about What device 300 had been described, in some embodiments, engineered substrates are engaged with CMOS wafer.In some embodiments, CMOS wafer includes integrated circuit.In some embodiments, CMOS wafer includes the integrated circuit handled on it and divides again Layer of cloth.In some embodiments, CMOS wafer can only include the redistributing layer handled on it.Other alternatives are can With.For example, engineered substrates can be engaged alternatively with insert layer, device electrically (and sometimes physically) is configured two Among a device, and has and be configured to two devices (for example, engineered substrates and such as ball grid array or other devices Another device) electric coupling interconnection.In some embodiments, engineered substrates can wrap with not including integrated circuit It includes for being engaged with the chip of the wiring of the first silicon device layer and/or the second silicon device layer transmission electric signal.For example, in some realities Apply in scheme, engineered substrates can with include the routing traces for being configured to for electric signal to be re-assigned to smaller or biggish substrate Chip engagement, therefore it can be referred to as " redistribution chip " herein.

Another alternative is related to the mode being in electrical contact with the second silicon device layer 310.As previously mentioned, in the reality of Fig. 3 It applies in scheme, can be for example in electrical contact between contact 324 and landing pad 326 using wire bonding 325.Such as Figure 10 Shown, the device 1000 of alternative structure is using from junction 316a to the through-hole 1002 of the second silicon device layer 310.With this side Formula, can be used embedded contact and can be to avoid wire bonding.When the first silicon device layer of expectation and the second silicon device layer When being electrically isolated from each other, dielectric features appropriate (for example, insulation lining) can be used in some embodiments to make through-hole 1002 It insulate with the first silicon device layer 308.However, as previously mentioned, in some embodiments, it may be desirable to by the first silicon device layer 308 region (for example, when included, the region 902 of Fig. 9) electricity is constrained to identical with the current potential of the second silicon device layer 310 Current potential, and in such embodiments, no dielectric features can be provided in through-hole 1002.

It should be understood that through-hole 1002 is not conventional TSV, because of its thickness for passing through, i.e. the second silicon device layer 310, silicon oxide layer 312 and the thickness of the first silicon device layer 308 can be relatively small, such as with previously described herein Any size about this structure.

As another alternative, indicate that the through-hole 1002 of embedded contact can be not passed through the second silicon device layer 310, and It is that can extend between junction 316a and the bottom side of the close chamber 306 of the second silicon device layer 310, while passing through suitably Dielectric features (for example, insulation lining) insulate with the first silicon device layer 308 again.One embodiment is shown in Figure 11, wherein Device 1100 includes extending to the surface of the second silicon device layer 310 from junction 316a but being not passed through the second silicon device layer 310 Embedded through-hole 1102.Additional interconnection 1104 from metallization 322 to junction 316a can be provided, and metallized Part 322 can be connected to landing pad 326 as shown in the figure, form the continuous circuits diameter from landing pad 326 to through-hole 1102.So And it is also possible for providing other configurations being electrically accessed to through-hole 1102.

In the configuration similar to Figure 11, for example, first can be passed through before engaging engineered substrates with CMOS wafer Silicon device layer 308 and silicon oxide layer 312 (for example, after processing step shown in Fig. 4 J) manufacture through-hole are (for example, through-hole 1102) it, and by the movement that engineered substrates are engaged with CMOS chip can complete from junction 316a to the second silicon device layer 310 electrical connection.This configuration can eliminate any metal on the top side to the second silicon device layer 310 as shown in figure 11 It needs.This can simplify manufacture and improves the performance of the ultrasonic transducer diaphragm formed by the second silicon device layer 310.

Another alternative of device 300 combines the feature of the device of Figure 10 and Figure 11.It may include the through-hole of Figure 10 The through-hole 1002 of 1002 and Figure 10 can connect to the metallization on the top side of the second silicon device layer 310.Also may include The interconnection 1104 of Figure 11.In such embodiments, it can provide from metallization 322 to the top in the second silicon device 310 The electric pathway of metallization on side, without wire bonding.

Another alternative of the manufacturing process of device 300 and Fig. 4 A to Fig. 4 T is related to whether chamber 306 seals.Such as preceding institute It states, in some embodiments, chamber 306 can be seal chamber.However, chamber 306 can not be close in alternative embodiment Envelope, such as there are one or more openings for leading to chamber.An example is shown in Figure 12.

Device 1200 is similar to the device 300 of Fig. 3, but the difference is that is mentioned by the second silicon device layer 310 to chamber 306 For opening.Show two different non-limiting embodiments of opening.It in some embodiments, can be one or more Each of a (but being not necessarily whole) chamber 306 provides single opening 1202.It in some embodiments, can be one Or more each of (but being not necessarily whole) chamber multiple openings 1204 are provided.Although for illustrative purposes in Figure 12 In show the opening of two kinds of different patterns it should be appreciated that single pattern is (for example, only opening 1202 or be only open 1204) it can be used for whole device 1200.In addition, though opening 1202 and 1204 is shown as extending vertically through the second silicon device Part layer 310, but it is to be understood that, the opening of other paths and geometry can be used.For example, along the side shape of device At groove can be used for close to chamber 306.

Opening 1202 and/or 1204 can be in any suitable manner and in any appropriate processing step of device 300 Rapid place is formed.For example, opening 1202 and/or 1204 can utilize suitable etching shape after the fabrication stage shown in Fig. 4 T At.

The presence of opening 1202 and/or 1204 can influence the loss and reinforcement of ultrasonic transducer, and finally influence behaviour The frequency of work.For example, with do not include the case where opening compared with, opening 1202 and/or 1204 will lead to the device more for Broadband device, and lead to improved range behavior (ranging behavior).The size shadow of opening 1202 and/or 1204 Frequency characteristic is rung, and in some embodiments, can be selected as humorous with the Helmholtz of device 1200 (Helmholtz) Vibration frequency matching.

Therefore, opening 1202 and/or 1204 can be conducive to provide desired ultrasonic transducer frequency characteristic.For example, opening 1202 and/or 1204 can contribute to the expected frequency row that ultrasonic transducer is realized in outdoor application (lacking sensor information) For.

Figure 13 shows the top view of the embodiment of the shape of the isolation structure 328 of isolating seal chamber 306.As shown , in one embodiment, seal chamber 306 can have circular contour.Isolation structure 328 can have any appropriate shape Shape, to provide enough isolation between each ultrasonic transducer between ultrasound transducer element or as shown in figure 13.Cause This, in some embodiments, isolation structure 328 can substantially or entirely surround (or surrounding) seal chamber 306 and (see when from top side When examining), but in alternative embodiment, they can not surround seal chamber.In addition, in some embodiments, isolation structure can To have the profile in seal chamber (when viewed from the top).For example, when doped region is for limiting as combined described by Fig. 9 Isolation structure when, doped region may be positioned such that the profile for limiting isolation structure, the profile of the isolation structure are less than sealing The profile of chamber.

In some embodiments, isolation structure 328 can have polygonal profile.For example, being shown in FIG. 13 eight Side shape profile it should be appreciated that other profiles are (for example, circle, rectangle, hexagon, limit the profile for being more than semicircle Deng) be possible.In addition, as previously mentioned, in some embodiments, isolation structure can surround multiple chambers 306, rather than single Solely surround each chamber.It therefore, is possible for the various configurations of isolation structure.

Another alternative of the manufacturing process of device 300 and Fig. 4 A to Fig. 4 T is related to the use of TSV.As previously mentioned, this Many embodiments of text description avoid the needs to TSV, can be in the easiness, low cost and reliability of such as manufacture Aspect provides significant benefit.However, in some embodiments, TSV can be used.Embodiment is described in conjunction with Figure 14.

In some embodiments, the chip with TSV can be used to form engineered substrates.Figure 14 is shown including silicon 1402 With the chip 1400 of six TSV 1404.Chip 1400 can for example be used for the SOI in the manufacturing process instead of Fig. 4 A to Fig. 4 T Chip.As embodiment, chip 1400 is substituted for the first SOI wafer 400.In this case, then, Fig. 4 F Structure can be different, the difference is that the first silicon device layer 308 will be replaced by silicon 1402 and TSV 1404 will be with chamber 306 alignments.Therefore, TSV 1404 may be used as electrode, and therefore may be used as the alternative of the doped scheme of such as Fig. 9 To form electrode.

Such as the embodiment just described in conjunction with Figure 14 that use for being related to that there is the chip of TSV, it can simplify and be used for The manufacture of the hearth electrode of the seal chamber of engineered substrates, this is because TSV may be used as electrode.Chamber can by suitably design with TSV alignment.

Describe so far for manufacturing engineering substrate and the various methods that engage engineered substrates with CMOS wafer and Chip micro Process processing technique is compatible, it is meant that they can be executed in micro Process equipment.This equipment is generally for permission Material type and the processing step that can execute there is stringent standard.Following exemplary techniques utilizes can be at least partly The technique executed in the other kinds of equipment of such as back-end wafer grade sealed in unit.It can be using the benefit of these technologies With lower cost.

According to the one side of the application, implementable wafer-class encapsulation technology is to engage the engineered substrates of type described herein To the chip (such as CMOS wafer) with IC.Wafer-class encapsulation can use redistribution technology.For example, CMOS wafer and/or Engineered substrates can have the redistributing layer of addition.In the form of welded ball array or the solder of other forms can be used for serving as a contrast engineering Bottom is bonded together with IC chip.In some embodiments, carrier wafer can be added to engineered substrates in order to handle.

According to the another aspect of the application, can be used it is so-called be fanned out to (fan out) or fan-in (fan in) technology by Engineered substrates are engaged with IC wafer.The reconstructed wafer including IC chip can be formed.It is fanned out to or fan-in technology can be used for Bonding station is established on reconstructed wafer.Then engineered substrates can be engaged with the chip of reconstruct.

In an alternative, the reconstructed wafer including engineered substrates can be formed.Then can by engineered substrates with IC chip is bonded together.The benefit of this processing is, can also be with even if engineered substrates and IC chip have different sizes Execute wafer scale engagement.

It shows in engaging the engineered substrates of type described herein with IC chip in conjunction with Figure 15 A to Figure 15 F using crystalline substance The embodiment of chip size package technology.5A referring to Fig.1 provides engineered substrates 1500.Engineered substrates 1500 can be at several aspects Similar to previously described engineered substrates 302, so that showing some identical appended drawing references.

As shown, engineered substrates 1500 include have be formed in the second silicon device layer 310 and silicon oxide layer 312 it Between sealing chamber 306 multiple ultrasonic transducers.May differ in for engineered substrates 1500 and engineered substrates 302 can be with Including substrate 1501 rather than SOI wafer 400.Substrate 1501 can be the silicon substrate with silicon wafer 1502, silicon wafer 1502 With the groove 1503 being formed by insulating materials.What groove 1503 can be positioned so that silicon wafer 1502 may be used as chamber 306 The area of isolation of electrode.

In some embodiments, as shown, groove 1503 can extend through the thickness of silicon wafer 1502.? In other embodiments, groove 1503 can extend partially through silicon wafer 1502, start from the close chamber of silicon wafer 1502 On 306 surface, but the whole thickness of silicon wafer 1502 is not extended through.In such a case, it is possible to from the back side (in silicon wafer The surface of 1502 separate chamber 306) substrate 1501 is carried out it is thinned, with during processing step later expose groove 1503.

In some embodiments, substrate 1501 sufficiently thick can be enough to allow to execute processing step to provide to form work The mechanical stability of the ultrasonic transducer structures of journey substrate.For example, substrate 1501 can be about 400 microns of thickness, at 200 microns The range of any value or value between 500 microns, or in the range.In some embodiments, as further below Description, if groove 1503 does not extend across the whole thickness of silicon wafer 1502, substrate 1501 can be thinned with Expose groove 1503.However, even if it can keep sufficiently thick in some such embodiments that substrate 1501 is thinned To provide mechanical stability for further process step.However, as another alternative, in some embodiments, After being engaged with temporary carrier chip, substrate 1501 can be carried out it is thinned, as will be in conjunction with described in Figure 15 B.

Engineered substrates 1500 may include the layer 1504 and 1506 that can respectively represent conductive layer and passivation layer.Layer 1504 It may be used as electric contact piece.It is in electrical contact later with the CMOS wafer for being bonded to engineered substrates 1500 due to expecting, so It can be formed and remove region 1508.Therefore, should be understood that according to Figure 15 A can execute top side processing on engineered substrates To provide electric contact piece, metallization, passivation part and bonding pad opening.

Next, as shown in fig. 15b, engineered substrates 1500 can be engaged with carrier wafer 1510.Carrier wafer 1510 can In order to being further processed, such as in wafer-class encapsulation manufactory.Carrier wafer can be chip glass, silicon wafer or other conjunctions Suitable material, and adhesive can be used or other suitable interim joining techniques are engaged with engineered substrates 1501, because such as What is be described further below can remove carrier wafer 1510 later.It should be understood that engineered substrates 1500 according to Figure 15 B It can be engaged with the carrier wafer 1510 of the device-side close to engineered substrates.That is, substrate 1501 can expose.

As previously mentioned, in some embodiments, groove 1503 can not extend across the entire thickness of silicon substrate 1502 Degree.In such embodiments, substrate 1501 can be thinned after engaging with carrier wafer 1510.This is thinned and can hold Row extremely is suitable for exposing the degree of groove 1503.As embodiment, this be thinned can be related to grinding or spray etching.In some realities It applies in scheme, regardless of whether groove 1503 extends through silicon substrate 1502, substrate 1501 can be thinned as engineering lining Bottom provides small size.For example, substrate 1501 can be thinned to less than 50 microns, less than 30 microns, less than 20 microns, less than 10 Micron, between 5 microns and 200 microns, or the range of any value or value in such range.Pass through engineered substrates 1500 engage with carrier wafer 1510, can contribute to substrate 1501 being thinned to such degree, this is because carrier wafer 1502 can provide structural rigidity.

Then the structure of Figure 15 B can be further processed to form redistributing layer, as shown in figure 15 c. 15C.In some realities It applies in scheme, relative to the point processing until Figure 15 B, such be further processed can occur in different equipment.For example, Until the processing of the point of Figure 15 B can occur in micromachining device, then the structure of Figure 15 B is transported to the encapsulation of wafer-scale Manufactory, and the step of the encapsulation manufactory of wafer-scale executes remaining.If the processing stage shown in Figure 15 B, lining Bottom 1501 is thinned, then this be thinned can also carry out in wafer-class encapsulation manufactory.

More specifically, may include turn on substrate 1501 from the structure that the structure of Figure 15 B reaches Figure 15 C so that clear (area) Domain 1508 extends through the whole thickness of engineered substrates 1500.This can be completed in any suitable manner.In some embodiment party In case, saw is used.Then dielectric layer 1512, redistributing layer (RDL) 1516 and dielectric layer 1514 can be formed.RDL 1516 can be with It is formed by metal, and contact silicon substrate 1502 can be manufactured to as shown in the figure.It is mixed since silicon substrate 1502 can be height Miscellaneous, so RDL 1516 can provide being electrically accessed for the control operation to ultrasonic transducer.In some embodiments, RDL 1516 may be configured to provide the single solderable electrode connect for corresponding to each ultrasound transducer element, but other configurations It is possible.Soldered ball 1518 can be optionally formed in order to then engage engineered substrates with IC chip.In alternative embodiment party In case, solder can be formed in circuit chip sheet, as below in conjunction with described and illustrated in Figure 15 D.

In fact, dielectric layer 1512 and 1514 extends to the removing region 1508 in Figure 15 C.1512 He of dielectric layer 1514 accessible carrier wafers 1510.To simplify the explanation, the pattern is not shown.When dielectric layer 1512 and 1514 extends to removing When region 1508,1512 He of dielectric layer can be removed during subsequent processing in the case where removing carrier wafer 1510 1514。

Figure 15 D shows circuit chip, such as CMOS wafer, can be with the type shown in Figure 15 A to Figure 15 C Engineered substrates engagement.Circuit chip 1520 can have the feature common with previously described CMOS wafer 304, so that occurring Some identical appended drawing references.However, circuit chip 1520 also comprises redistribution structure to promote the engagement with engineered substrates. These redistribution structures include dielectric layer 1522, RDL 1526 and dielectric layer 1524.Soldered ball 1528 is provided to allow to engage.

As previously mentioned, in some embodiments, it is possible to implement be fanned out to or fan-in technology is to promote engineered substrates and device Manufacture.Therefore, as an example, circuit chip 1520 can be a part of the reconstructed wafer including mold 1530.Mold 1530 can permit across some contact points (soldered ball 1528) of broader area positioning being provided separately by circuit chip, this can permit Wafer-class encapsulation is executed, even if it is diametrically also such that circuit chip and engineered substrates, which are formed in different,.It is brilliant when forming reconstruct When piece, any appropriate mold materials can be used.

As shown in Fig. 15 E, then engineered substrates and circuit chip can be bonded together.The engagement can be wafer scale Engagement.Although in the embodiment illustrated, show has soldered ball in both engineered substrates and circuit chip, should manage Solution, in some embodiments, they can be provided only on only one or another on.

As shown in fig. 15f, then can remove carrier wafer 1510, and remaining device can be carried out cutting and by its It is located in insert layer 1532.It can be from region removal be removed in the dielectric layer for removing any surplus in region 1508 1512 and 1514.Wire bonding 1534 can be provided to the electrical connection of insert layer.But alternative is possible.For example, institute Obtained device can be with the die-stack of other in wafer stacking structure.

In the alternative of the manufacturing process of Figure 15 A to Figure 15 F, removing region 1508 can be in different processing stage Extend through the whole thickness of engineered substrates 1500.Not make clear (area) when being moved to the structure of Figure 15 C from the structure of Figure 15 B Domain 1508 extends through engineered substrates, but can retain as shown in Figure 15 B and remove region.Dielectric layer can be formed 1512 and 1514 and RDL 1516.Engineered substrates can be with circuit chip solder joints.Carrier wafer 1510 can be removed. After removing carrier wafer 1510, the whole thickness sawed to make removing region extend through engineered substrates 1500 can be used, To allow to be electrically accessed circuit chip 1520 using wire bonding or other electric connectors.

Although the embodiment of Figure 15 A to Figure 15 F is shown in which that circuit chip is formed as a part of reconstructed wafer Situation, but other embodiment engineered substrates are formed as a part of reconstructed wafer.Figure 16 shows embodiment.

As shown in figure 16, engineered substrates 1500 can be substantially encapsulated to generate reconstruct on three faces of mold 1536 Chip.Mold 1536 can be polymer or other suitable molding materials.In some embodiments, mold 1536 can be Interim.Mold 1536 can be formed as generating the reconstructed wafer with the size substantially the same with the size of IC chip.So Afterwards, due to matched size, the reconstructed wafer including engineered substrates and IC chip can be engaged more easily.Then it can remove Mold 1536.Then removable carrier wafer 1510.

It is understood, therefore, that the use of reconstructed wafer can have different purposes.In some embodiments, may be used Allow to be fanned out to the electrical connection on IC chip using reconstructed wafer.In some embodiments, for the purpose of chip engagement, weight Structure chip can be used for generating similarly sized chip.

Another alternative of manufacture as Figure 15 A to Figure 15 F, Figure 17 is shown wherein only is arranged weldering on IC chip The embodiment of ball.That is, Figure 17 is similar to Figure 15 E, difference is that soldered ball 1518 is omitted.On the contrary, soldered ball 1528 is straight Contact RDL 1516.In unshowned another alternative, soldered ball 1518 is kept, and omits soldered ball 1528.

According to the discussion of Figure 15 A to 15F and Figure 16 it should be understood that the embodiment of the application is provided in engineered substrates It is used with the wafer scale of the RDL on one or two of circuit chip.Chip can be bonded together and be then cut out.One In a little embodiments, the device of cutting be can be set in insert layer, or a part as die-stack configuration facilitates Biggish device.

It should be understood that it is relatively small to may be used to provide electrical connection according to the use of the RDL of the embodiment of the application Feature purpose.For example, RDL 1516 can provide the electrical contact with the electrode zone of ultrasonic transducer.Ultrasonic transducer can With small size.For example, the width of the electrode zone of engineered substrates is substantially equal to or less than the chamber 306 previously listed Width W.This use of RDL with use RDL to be connected to landing pad to be contrasted.And not all embodiment is in this respect All it is restricted.

Present aspects can provide one or more benefits, and some of them have been described previously.It retouches now What is stated is some non-limiting embodiments of these benefits.It should be understood that and not all aspect and embodiment it is all necessary What offer will now be described benefits.However, it should be understood that present aspects can be that aspect those of will now be described Other benefit is provided.

Present aspects, which provide, suitably forms single-chip integration ultrasonic transducer and CMOS structure (for example, CMOS IC) Manufacturing process.Therefore, it realizes as Vltrasonic device (for example, for ultrasonic imaging and/or high intensity focused ultrasound (HIFU)) Single substrate devices of work.

In at least some embodiments, processing can be reliable (for example, reliable with rate of good quality rate and/or high device Property be characterized), can scale to high-volume and execute relatively cheap, therefore the business that facilitates CUT is practical manufactured Journey.It can be engaged to avoid complicated and expensive processing technique, such as formation TSV is used using CMP and using low temperature oxide Densification anneal.In addition, these processing can provide the manufacture of miniature ultrasonic device, convenient for creation portable ultraphonic probe.

In some respects, manufacturing process permission engages engineered substrates with circuit chip in wafer-class encapsulation equipment, with It executes engagement in micro Process equipment to compare, which provides reduced cost.Furthermore, it is possible to adapt to reallocate and be fanned out to Or the use of fan-in technology, permit even if when the two is with different sizes or when the tube core from the two has different sizes Perhaps the engagement of circuit chip and engineered substrates.It many RDL and is fanned out to and/or the use of fan-in can also allow in engineered substrates Design variation, without redesigning circuit chip or boundary layer between the two.

Several aspects and embodiment of the technology of the application have been described, it should be appreciated that the common skill in this field Art personnel will readily occur to various changes, modification and improvement.Such changes, modifications and improvement are directed at described in this application In the spirit and scope of technology.For example, those of ordinary skill in the art will readily appreciate that for executing function and/or being tied The various other devices and/or structure of fruit and/or one or more advantages described herein, and each such modification And/or modification is considered in the range of the embodiment described herein.Those skilled in the art will appreciate that or can only make The many equivalents of specific embodiment as described herein are determined with routine experiment.It is understood, therefore, that aforementioned implementation Scheme only provides by way of examples, and within the scope of the appended claims and their equivalents, the embodiment party of invention Case can be implemented in a manner of being different from specifically describing.In addition, if feature described herein, system, product, material, element And/or method is not conflicting, then two or more such features, system, product, material, element and/or method appoint Meaning combination be included in scope of the present disclosure.

As non-limiting embodiment, various embodiments are described as including CMUT.It, can be in alternative embodiment It substitutes CMUT or uses PMUT other than CMUT.

In addition, as described, some aspects may be implemented as one or more methods.A part as method The movement of execution can sort in any suitable manner.Therefore, it can be constructed in which with the sequence of sequence shown in being different from The embodiment of execution movement, may include being performed simultaneously some movements, even if being illustrated as in illustrative embodiment suitable Sequence movement.

Being defined for defining and use herein is interpreted as control dictionary definition, determines in the document being incorporated by reference into The ordinary meaning of justice and/or defined term.

Singular as used herein in the specification and claims is understood to refer to "at least one", removes It is non-to clearly indicate on the contrary.

Phrase "and/or" as used herein in the specification and claims should be understood as referring to such combination Element in " either one or two ", i.e. in some cases combine existing element and discretely exist in other cases Element.The multiple element listed with "and/or" should be explained in an identical manner, that is, " one in the element so combined Or more ".Element other than the element especially identified by "and/or" clause can there can optionally be, and specifically Those of mark element is related or uncorrelated.Therefore, as non-limiting embodiment, when combining open language (such as " packet Include ") in use, can only refer to that A (optionally includes the member in addition to B in one embodiment to the reference of " A and/or B " Part)；In another embodiment, only refer to B (optionally including the element in addition to A)；In another embodiment again, refer to Both A and B (optionally including other elements) etc..

As used in the specification and in the claims herein, the phrase of the list about one or more elements "at least one" should be understood as referring at least one element selected from any one of element list or more element, But not necessarily includes at least one of each element specifically listed in element list, and be not excluded in element list Any combination of element.This definition also permits other than the element being specifically identified in the element list of phrase "at least one" meaning Perhaps element can there can optionally be, but regardless of to those of to be specifically identified element related or uncorrelated.Therefore, as non-limiting Embodiment, " at least one of A and B " (or equally, " at least one of A or B " or equally " in A and/or B at least One ") it can refer at least one in one embodiment, more than one A is optionally included, there is no B (and optionally Including the element in addition to B)；In another embodiment, refer at least one, optionally include more than one B, and be not present A (and optionally including the element in addition to A)；In another embodiment again, refers at least one, optionally include and be more than One A and at least one, optionally include more than one B (and optionally including other elements) etc..

In addition, phraseology and terminology employed herein is for purposes of description, and to be not considered as restrictive.This "include", "comprise" used herein or " having ", " containing ", " being related to " and its modification mean to include items listed thereafter And its equivalent and addition item.

In the claims and in the above specification, all transition phrases such as "include", "comprise", " carrying ", " tool By ", " containing ", " being related to ", " holding ", " by ... form " etc. be understood as it is open, that is, mean include but not It is limited to.Only transition phrase " by ... constitute " and " substantially by ... constitute " should be closing respectively or semi-enclosed Transition phrase.

The present invention at least the following technical schemes are provided:

A kind of method of scheme 1., comprising:

The first chip by that will be formed with open cavity is bonded to the second chip, then by first wafer grinding To less than about 30 microns of thickness forms the engineered substrates with multiple seal chambers；

No more than 450 DEG C at a temperature of the engineered substrates are bonded to third wafer；And

It is after the engineered substrates are bonded to the third wafer, second wafer grinding to less than about 30 is micro- The thickness of rice.

2. the method for claim 1 of scheme, wherein first chip is silicon-on-insulator (SOI) chip, wherein Be thinned to first chip includes the operation layer for removing first chip.

3. the method for claim 2 of scheme, wherein second chip is SOI wafer, wherein brilliant to described second It includes the operation layer for removing second chip that piece, which be thinned,.

4. the method for claim 1 of scheme, wherein first chip is the body silicon wafer for including doped layer, it is described Doped layer have less than about 10 microns thickness and close to first chip the first face, wherein to first chip into It includes from the back side by first wafer grinding to the doped layer that row, which is thinned, and the back side is opposite with first face.

5. the method for claim 4 of scheme, wherein second chip is to include thickness mixing less than about 10 microns The body silicon wafer of diamicton, wherein it includes brilliant by described second from the back side of second chip for be thinned to second chip Piece is thinned to the doped layer.

The method according to scheme 1 or other any aforementioned schemes of scheme 6., wherein extremely by first wafer grinding Thickness less than about 30 microns includes by first wafer grinding to less than about 5 microns of thickness, wherein brilliant by described second It includes by second wafer grinding to less than about 5 microns of thickness that piece, which is thinned to the thickness less than about 30 microns,.

7. the method for claim 1 of scheme, wherein second chip the multiple seal chamber at least one Diaphragm is formed on chamber, wherein the third wafer is complementary metal oxide semiconductor (CMOS) chip, wherein the method It further include that the integrated circuit in CMOS wafer is connected to the diaphragm.

The method according to scheme 1 or other any aforementioned schemes of scheme 8., wherein the part of first chip is It is conductive, wherein by the engineered substrates be bonded to the third wafer include first chip the part in institute It states and forms electrical connection between the electric contact piece in third wafer.

9. the method for claim 8 of scheme, wherein to limit the pattern of electrode to the portion of first chip Divide and is doped.

10. the method for claim 9 of scheme, wherein the part includes monocrystalline silicon.

11. the method for claim 9 of scheme, wherein the part includes polysilicon.

12. the method for claim 9 of scheme, wherein the part includes amorphous silicon.

13. the method for claim 9 of scheme, wherein the doping limits first area and contact area, described the One region and contact area doping type having the same, the contact area have denseer than the doping of the first area Spend high doping concentration.

The method according to scheme 8 or other any aforementioned schemes of scheme 14., wherein the portion of first chip The width divided is less than the width for being located at least one chamber of the part of neighbouring first chip.

The method according to scheme 1 or other any aforementioned schemes of scheme 15., wherein the engineered substrates are bonded to The third wafer includes forming eutectic bonding or hot press or silicide bond.

The method according to scheme 1 or other any aforementioned schemes of scheme 16., wherein the engineered substrates are bonded to The third wafer includes forming the sealing ring for airtightly sealing the multiple seal chamber.

The method according to scheme 1 or other any aforementioned schemes of scheme 17., wherein being formed has multiple seal chambers Engineered substrates include being formed with width and depth and at least one sealing of the ratio between width and depth between 50 and 300 Chamber.

18. the method for claim 17 of scheme, wherein the depth is between about 0.1 micron and about 5 microns.

The method according to scheme 1 or other any aforementioned schemes of scheme 19., further includes by being annealed come to institute The doping stated in the first chip and/or second chip is activated, and the activation is as forming the one of the engineered substrates It carries out partially and before the engineered substrates are bonded to the third wafer.

The method according to scheme 1 or other any aforementioned schemes of scheme 20., further includes the shape in the engineered substrates At the opening of at least one chamber led in the multiple seal chamber, to open at least one described chamber.

The method according to scheme 1 or other any aforementioned schemes of scheme 21., further includes the silicon in first chip The open cavity is formed in oxide skin(coating).

The method according to scheme 1 or other any aforementioned schemes of scheme 22., further include to first chip into Row etches multiple grooves after being thinned in first chip, and the multiple groove limits the multiple electrodes of first chip Region.

The method according to scheme 22 or other any aforementioned schemes of scheme 23. further includes filling institute with insulating materials State multiple grooves.

The method according to scheme 1 or other any aforementioned schemes of scheme 24., wherein the engineered substrates are bonded to The third wafer includes by the engineered substrates and the third wafer single-chip integration.

Claims

1. a kind of method for forming Vltrasonic device on the chip including integrated CMOS (CMOS) circuit, institute The method of stating includes:

Chamber is formed in the first chip, wherein first chip includes silicon-on-insulator (SOI) chip；

By the way that the second chip and the first chip welding are formed compound substrate to be sealed to the chamber, and to institute It states compound substrate to anneal, wherein second chip includes silicon-on-insulator (SOI) chip, wherein forming the composite lining Bottom includes by the oxidation on the first face of the silicon device layer of second chip and the silicon device layer for being formed in first chip Nitride layer engagement, the chamber are formed in the oxide skin(coating)；

Conductive contact piece is formed on the electrode zone of the compound substrate；

Before the compound substrate is bonded to the third wafer for being formed with the integrated CMOS circuit, described the is removed The operation layer of one chip and bury oxygen (BOX) layer；

The compound substrate is bonded to using the conductive contact piece and is formed with described the of the integrated CMOS circuit Three chips；And

The compound substrate is thinned to be formed close to the flexible membrane of the chamber.

2. according to the method described in claim 1, wherein lower than 450 DEG C at a temperature of execute the welding in a vacuum.

3. according to the method described in claim 2, wherein the seal chamber has about 1 × 10^-3It holds in the palm to about 1 × 10^-5The pressure of support.

4. according to the method described in claim 1, described in wherein being executed at a temperature of between about 500 DEG C with about 1500 DEG C Annealing.

5. according to the method described in claim 1, it includes being lower than that the compound substrate, which is wherein bonded to the third wafer, One of hot press, eutectic bonding or silicide bond are formed at a temperature of 450 DEG C.

6. according to the method described in claim 1, further including the shape in the second face of the silicon device layer of first chip At isolated groove, the isolated groove corresponds to the position of the chamber.

7. according to the method described in claim 1, wherein the chamber includes a part of ultrasonic transducer.

8. Vltrasonic device on a kind of chip, comprising:

Composite capacitive micro-machined ultrasonic transducer (CMUT) substrate comprising there is the first chip of ultrasonic transducer chamber and connect It is bonded to the second chip of first chip, limits the oxide-that is sealed to the ultrasonic transducer chamber to-oxide Engagement, wherein the ultrasonic transducer chamber is about 1 × 10^-3It holds in the palm to about 1 × 10^-5Under the pressure of support；

Conductive contact piece on the electrode zone of the compound CMUT substrate is set；

It is formed with the third wafer of integrated circuit, the third wafer is bonded to described compound using the conductive contact piece CMUT substrate, in which:

The compound CMUT substrate has thinned surface to be formed close to the flexible membrane of the ultrasonic transducer chamber；

The ultrasonic transducer chamber is formed in the first thermal oxide layer of first chip；

Second chip has the second thermal oxide layer, so that the compound CMUT substrate includes to the ultrasonic transducer chamber The oxide-being sealed to-oxide engagement；

Second chip includes thinned body silicon layer, and the body silicon layer includes the hearth electrode of the ultrasonic transducer chamber；And

First chip includes silicon device layer, and the silicon device layer includes the flexible membrane close to the ultrasonic transducer chamber Piece；And

Isolation structure, the isolation structure is formed in the hearth electrode so that the hearth electrode corresponds to the ultrasonic transduction The part of device chamber is electrically isolated, wherein the isolation structure extends through the thinned body silicon layer including the hearth electrode.

9. Vltrasonic device on chip according to claim 8, wherein the isolation structure includes in the thinned body silicon The groove being filled with an insulating layer in layer.

10. Vltrasonic device on chip according to claim 8, wherein the hearth electrode includes the thinned body silicon layer Doped portion, the isolation structure include the undoped part of the thinned body silicon layer.