CN109275253B - Electronic ballast drive control circuit - Google Patents
Electronic ballast drive control circuit Download PDFInfo
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- CN109275253B CN109275253B CN201811417901.5A CN201811417901A CN109275253B CN 109275253 B CN109275253 B CN 109275253B CN 201811417901 A CN201811417901 A CN 201811417901A CN 109275253 B CN109275253 B CN 109275253B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
- H05B41/14—Circuit arrangements
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
- H05B41/14—Circuit arrangements
- H05B41/36—Controlling
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Abstract
The invention discloses an electronic ballast drive control circuit, which comprises a first single chip microcomputer, wherein the first single chip microcomputer comprises a configurable logic unit CLC peripheral, a reversing signal input end, a median voltage signal input end and a peak detection signal input end; the CLC peripheral is used for synthesizing a reversing signal input by the reversing signal input end and a median voltage signal input by the median voltage signal input end into a starting signal for driving PWM, and comparing a detection signal of the peak detection signal input end with a reference voltage to generate a closing signal for driving PWM; the PWM opening signal is used for driving a switching tube of the bridge circuit to be switched on, and the PWM closing signal is used for driving the switching tube of the bridge circuit to be switched off. The technical scheme provided by the embodiment of the invention can realize the soft switching function of the driving transistor of the bridge type driving circuit of the electronic ballast and can also save the cost.
Description
Technical Field
The embodiment of the invention relates to a bridge circuit driving technology, in particular to an electronic ballast driving control circuit.
Background
The electronic ballast has important application in the field of lighting, however, if the driving transistor of the electronic ballast is in a hard switching state when working, the working loss is large, the heat dissipation performance is poor, and the efficiency of the electronic ballast is affected.
In the prior art, if the driving transistor is operated in a soft-on/off state, an FPGA (Field-Programmable Gate Array) chip or a specially-customized chip is generally used to drive the transistor, which is high in cost.
Disclosure of Invention
The invention provides an electronic ballast drive control circuit, which is used for reducing the cost on the basis of realizing soft switching drive of a drive transistor.
The embodiment of the invention provides an electronic ballast drive control circuit, which comprises a first single chip microcomputer, wherein the first single chip microcomputer comprises a configurable logic unit CLC peripheral, a reversing signal input end, a median voltage signal input end and a peak detection signal input end;
the CLC peripheral is used for synthesizing a reversing signal input by the reversing signal input end and a median voltage signal input by the median voltage signal input end into a starting signal for driving PWM, and comparing a detection signal of the peak detection signal input end with a reference voltage to generate a closing signal for driving PWM;
the PWM opening signal is used for driving a switching tube of the bridge circuit to be switched on, and the PWM closing signal is used for driving the switching tube of the bridge circuit to be switched off.
Optionally, the CLC peripheral includes an exclusive or gate, a not gate, a D flip-flop, and a comparison unit;
a first input end of the exclusive-or gate is electrically connected with the reversing signal input end, and a second input end of the exclusive-or gate is electrically connected with the median voltage input end;
the input end of the NOT gate is electrically connected with the output end of the exclusive-OR gate, and the output end of the NOT gate is electrically connected with the clock signal end of the D trigger;
a first input end of the comparison unit is electrically connected with the peak detection signal input end, a second input end of the comparison unit inputs the reference voltage, and an output end of the comparison unit is electrically connected with an R end of the D trigger;
and the output end of the D trigger is electrically connected with the PWM signal output end of the first singlechip and is used for outputting the driving PWM.
Optionally, the CLC peripheral further includes an and gate; the first single chip microcomputer further comprises a first delay signal input end; the output end of the comparison unit is electrically connected with the R end of the D trigger through the AND gate;
the first input end of the AND gate is electrically connected with the first delay signal input end, the second input end of the AND gate is electrically connected with the output end of the comparison unit, and the output end of the AND gate is electrically connected with the R end of the D trigger.
Optionally, the first single chip microcomputer further comprises a second delay signal input end;
and the S end of the D trigger is electrically connected with the second delay signal input end.
Optionally, the system further comprises a second single chip microcomputer, wherein the second single chip microcomputer comprises a first delay signal output end and a second delay signal output end, the first delay signal output end is electrically connected with the first delay signal input end, the second delay signal output end is electrically connected with the second delay signal input end, and the second single chip microcomputer is used for inputting the first delay signal to the second delay signal input end and inputting the second delay signal to the second delay signal input end.
Optionally, the delay time of the first delay signal is 15 microseconds, and the delay time of the second delay signal is 70 microseconds.
Optionally, the second single chip microcomputer further comprises a reversing signal output end, and the reversing signal output end is electrically connected with the reversing signal input end;
the second singlechip is used for outputting a reversing signal to the first singlechip.
Optionally, the frequency of the commutation signal is 200 Hz.
Optionally, the ballast further comprises a peak signal detection circuit, an input end of the peak signal detection circuit is electrically connected with an output end of the resonant inductor of the electronic ballast, and an output end of the peak signal detection circuit is electrically connected with an input end of the peak detection signal.
Optionally, the ballast further comprises a median signal detection circuit, an input end of the median signal detection circuit is electrically connected to a resonant capacitor in the electronic ballast, and an output end of the median signal detection circuit is electrically connected to a median voltage signal input end.
The invention adopts the electronic ballast drive control circuit which is composed of the single chip microcomputer comprising the configurable logic unit CLC peripheral, the reversing signal input end, the median voltage signal input end and the peak detection signal input end, thereby not only realizing the soft switching function of the bridge drive transistor of the electronic ballast, but also saving the cost.
Drawings
Fig. 1 is a schematic circuit diagram of a driving control circuit of an electronic ballast according to an embodiment of the present invention;
fig. 2 is a schematic circuit diagram of a driving control circuit of another electronic ballast according to an embodiment of the present invention;
fig. 3 is a waveform diagram of a CLC peripheral according to an embodiment of the present invention;
fig. 4 is a schematic circuit diagram of a driving control circuit of another electronic ballast according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a second single chip microcomputer according to an embodiment of the present invention;
fig. 6 is a schematic circuit diagram of a peak signal detection circuit according to an embodiment of the present invention;
fig. 7 is a schematic circuit structure diagram of a median signal detection circuit according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Examples
Fig. 1 is a schematic circuit diagram of a driving control circuit of an electronic ballast according to an embodiment of the present invention; referring to fig. 1, the electronic ballast driving control circuit includes a first single chip microcomputer 11, where the first single chip microcomputer 11 includes a Configurable Logic Cell (CLC) peripheral 101, a commutation signal input terminal HZ, a median voltage signal input terminal MV, and a peak detection signal input terminal CS;
the CLC peripheral 101 is configured to synthesize a commutation signal input from the commutation signal input terminal HZ and a median voltage signal input from the median voltage input terminal MV into a start signal for driving PWM (Pulse Width Modulation), and compare a detection signal at the peak detection signal input terminal CS with a reference voltage to generate a close signal for driving PWM;
the PWM opening signal is used for driving the switching tube of the bridge circuit to be switched on, and the PWM closing signal is used for driving the switching tube of the bridge circuit to be switched off.
Continuing to refer to fig. 1, fig. 1 further includes a bridge driving circuit module 105, specifically a half-bridge driving circuit, having an electronic ballast circuit structure, the circuit structure of which is well known to those skilled in the art, where the PWM on signal is used to drive a driving transistor of the half-bridge driving circuit to be turned on, the PWM off signal is used to drive a driving transistor of the half-bridge driving circuit to be turned off, and the driving transistor includes an upper transistor and a lower transistor; fig. 1 further includes a switching circuit between the first single chip microcomputer 11 and the bridge driving circuit module 105, wherein a driving PWM signal output terminal PWM of the first single chip microcomputer is used for outputting a driving PWM signal, so that the driving PWM determines an upper transistor or a lower transistor to be input to the bridge driving circuit module according to the commutation signal, a first pole of the first resistor 110 is electrically connected to the driving PWM signal output terminal PWM of the first single chip microcomputer 11, a second pole of the first resistor 110 is electrically connected to a first pole of the second resistor 107, a second pole of the second resistor 107 is electrically connected to a first pole of the first transistor 102, a second pole of the first transistor 102 is grounded, a gate of the first transistor 102 is electrically connected to a first pole of the current limiting resistor 106, a second pole of the current limiting resistor 106 is used for inputting the commutation signal, a first pole of the third resistor 108 is electrically connected to the first power source VCC, a second pole of the third resistor 108 is electrically connected to a gate of the third transistor 104, a first pole of the third transistor 104 is electrically connected to a second pole of the first resistor 110, the second pole of the third transistor 104 is grounded, a gate of the second transistor 103 is used for inputting the commutation signal, a first pole of the second transistor 103 is electrically connected to a second pole of the third resistor 108, the second pole of the second transistor 103 is grounded, a first pole of the fourth resistor 109 is used for inputting the commutation signal, and a second pole of the fourth resistor is grounded. The first electrode of the first transistor 102 may be connected to the lower transistor of the bridge driving circuit module 105, and the first electrode of the third transistor 104 may be connected to the upper transistor of the bridge driving circuit module 105. When the commutation signal is at a high level, the gate of the first transistor 102 is connected to the commutation signal through the current limiting resistor 106, so that the first transistor 102 is turned on, and at this time, the first transistor 102 is connected to one electrode of the driving PWM and is pulled down to a low level, so that the gate of the upper transistor of the bridge driving circuit module 105 is at a low level. The commutation signal is high level, so the second transistor 103 is also turned on, the gate of the third transistor 104 is pulled low to low level, so the third transistor 104 is turned off, and the driving PWM is sent to the upper transistor of the bridge driving circuit module 105; when the commutation signal is at a low level, the gates of the first transistor 102 and the second transistor 103 are both at a low level, and the gate of the third transistor 104 is at a high level, so that the first transistor 102 and the second transistor 103 are turned off, the third transistor 104 is turned on, and the driving PWM is sent to the lower transistor of the bridge driving circuit module 105, so that the electronic ballast completes driving the load. When the current of the driving transistor of the bridge type driving circuit module 105 in the electronic ballast reaches the maximum value, the current signal is converted into a voltage signal and then sent to the peak value detection signal input end CS, and the voltage signal is compared with a reference voltage to generate a closing signal for driving PWM, so that the soft turn-off process of the driving transistor is completed; it can be understood that the driving transistors of the bridge driving circuit module 105 are all connected in parallel with a detection capacitor, the median voltage can be sampled by the detection capacitor, and the specific circuit structure thereof is known to those skilled in the art, and the judgment is performed after the logic processing of the integrated control circuit, so as to provide the turn-on signal for driving the PWM, thereby implementing the soft switching operation state of the bridge driving circuit transistors.
According to the technical scheme of the embodiment, the electronic ballast driving control circuit is formed by the single chip microcomputer comprising the configurable logic unit CLC peripheral, the reversing signal input end, the median voltage signal input end and the peak detection signal input end, so that the soft switching function of the bridge driving transistor of the electronic ballast can be realized, and the cost can be saved due to the fact that the single chip microcomputer is lower in cost compared with an FPGA and a special chip.
Optionally, referring to fig. 2, fig. 2 is a schematic circuit structure diagram of a further electronic ballast driving control circuit according to an embodiment of the present invention, where the CLC peripheral 101 includes an exclusive-or gate 201, a not gate 202, a D flip-flop 203 and a comparing unit 204;
a first input end of the exclusive-or gate 201 is electrically connected with the commutation signal input end HZ, and a second input end of the exclusive-or gate 201 is electrically connected with the median voltage input end MV;
the input end of the not gate 202 is electrically connected with the output end of the exclusive or gate 201, and the output end of the not gate is electrically connected with the clock signal end of the D flip-flop 203;
a first input end of the comparing unit 204 is electrically connected to the peak detection signal input end CS, a second input end of the comparing unit 204 inputs a reference voltage, and an output end of the comparing unit 204 is electrically connected to the end R of the D flip-flop 203;
the output end of the D flip-flop 203 is electrically connected to the PWM signal output end of the first single chip microcomputer 11, and is configured to output driving PWM.
It will be appreciated that the D of the D flip-flop is terminated high.
Specifically, fig. 3 is a waveform diagram of a CLC peripheral according to an embodiment of the present invention, and referring to fig. 2 and fig. 3, a waveform 1 is a waveform diagram of driving PWM, a waveform 2 is a waveform diagram of a commutation signal, a waveform 3 is a waveform diagram of an input signal at a peak signal input terminal CS, a waveform 4 is a waveform diagram of an input signal at a median voltage signal input terminal MV, a D flip-flop 203 is triggered by a rising edge, and when a high level is input at a commutation signal input terminal HZ, a waveform of an input signal at a clock input terminal of the D flip-flop 203 is consistent with an input waveform at a commutation signal input terminal HZ; when the commutation signal input end HZ inputs a low level, the waveform of the input signal at the clock input end of the D flip-flop 203 is opposite to the input waveform at the commutation signal input end HZ; the positive input terminal of the comparing unit 204 is used as the second input terminal, i.e. inputting the reference voltage, the negative input terminal is used as the first input terminal, i.e. inputting the peak detection signal, the value of the reference voltage can be set to the value of the peak current, when the current input from the peak detection signal input terminal is less than the reference voltage, the comparing unit outputs the high level, so that the turn-off signal for driving the PWM is not generated; when the input signal at the peak detection signal input terminal CS reaches the maximum value, the output terminal of the comparison unit 204 is at a low level, so that the R terminal of the D flip-flop 203 inputs a low level, and the driving PWM is at a low level, that is, a turn-off signal of the driving transistor of the bridge driving circuit is formed.
It should be noted that fig. 3 shows an exemplary waveform diagram of the CLC peripheral only, it is understood that waveforms of input signals of each input end of the first single chip 11 may be controlled by the integrated control logic of the first single chip 11 and an output of the electronic ballast, and the CLC peripheral 101 may set a specific connection mode according to a specific configuration of the first single chip 11, as long as a function of driving the PWM to drive the soft switching of the driving tube is satisfied, which is not limited in this embodiment of the invention.
According to the technical scheme of the embodiment, the specific structure of the CLC peripheral is arranged, so that the driving control circuit of the electronic ballast is easy to realize, and the cost is saved.
Alternatively, referring to fig. 4, fig. 4 is a schematic circuit structure diagram of a driving control circuit of another electronic ballast according to an embodiment of the present invention; the CLC peripheral 101 further includes an and gate 205, the first single chip 11 further includes a first delay signal input terminal DY1, and an output terminal of the comparing unit 204 is electrically connected to an R terminal of the D flip-flop 203 through the and gate 205;
a first input terminal of the and gate 205 is electrically connected to the first delay signal input terminal DY1, a second input terminal of the and gate 205 is electrically connected to the output terminal of the comparing unit 204, and an output terminal of the and gate 205 is electrically connected to the R terminal of the D flip-flop 203.
Specifically, the first delay signal input terminal DY1 is configured to input a first delay signal, when the current input by the peak detection signal input terminal is less than the reference voltage, the comparing unit 204 outputs a high level, that is, the second input terminal of the and gate 205 inputs a high level, and because the first delay signal is initially a high level, the output terminal of the and gate 205 outputs a high level, that is, a turn-off signal for driving the PWM is not generated; if the signal input by the peak detection signal input terminal CS reaches the maximum value, the comparison unit 204 outputs a low level, that is, no matter the first delay signal is a high level or a low level, the R terminal of the D flip-flop 203 is a low level, so as to generate a shutdown signal for driving PWM; and after the driving PWM generates the on signal, the first delay signal starts timing from the high level, and when the timing reaches the preset time and the output of the comparing unit 204 is still at the high level, the first delay signal is switched to the low level, so that the R terminal of the D flip-flop 203 is set to 0, and the off signal for driving the PWM is generated, thereby preventing the driving transistor of the bridge driving circuit from being turned on for a long time.
According to the technical scheme of the embodiment, the electronic ballast driving control circuit comprising the AND gate and the first delay signal input end is adopted, so that the driving transistor of the bridge type driving circuit can be prevented from being conducted for a long time, and the service life of the electronic ballast is prolonged.
Optionally, with continued reference to fig. 4, the first single chip microcomputer 11 further includes a second delay signal input terminal DY 2;
the S terminal of the D flip-flop 203 is electrically connected to the second delay signal input terminal DY 2.
Specifically, the second delay signal input terminal DY2 is configured to input a second delay signal, where the second delay signal is initially at a high level, and when the D flip-flop 203 outputs a turn-off signal for driving the PWM, the second delay signal starts to time, and when the preset time is reached, if the D flip-flop 203 still outputs the turn-off signal for driving the PWM, the second delay signal is switched to a low level, so as to form a turn-on signal for driving the PWM, and avoid that the electronic ballast operates abnormally due to the turn-off signal for driving the PWM for a long time, and the light source is turned off.
According to the technical scheme, the electronic ballast drive control circuit comprising the second delay signal input end is adopted, so that when the median voltage signal input end cannot normally input to form a signal for driving the PWM to be started, the electronic ballast drive control circuit can still normally output a starting signal for driving the PWM, and the phenomenon that the electronic ballast works abnormally to cause the light source to be turned off due to the fact that the PWM is driven to be a long-time closing signal is avoided.
Optionally, referring to fig. 5, fig. 5 is a schematic structural diagram of a second single chip microcomputer according to an embodiment of the present invention; the electronic ballast driving control circuit further comprises a second single chip microcomputer 301, the second single chip microcomputer 301 comprises a first delay signal output end DYO1 and a second delay signal output end DYO2, the first delay signal output end DYO1 is electrically connected with the first delay signal input end DY1, the second delay signal output end DYO2 is electrically connected with the second delay signal input end, and the second single chip microcomputer 301 is used for inputting a first delay signal to the second delay signal input end DY1 and inputting a second delay signal to the second delay signal input end DY 2.
Specifically, the first single chip microcomputer 11 can adopt a single chip microcomputer with less crystal oscillator, and at the moment, the first delay signal and the second delay signal can be output by the second single chip microcomputer 301 with a simpler structure, so that the whole cost of the electronic ballast driving control circuit can be saved.
Optionally, the delay time duration of the first delay signal is 15 microseconds, and the delay time duration of the second delay signal is 70 microseconds.
After the PWM is driven to generate the on signal, the first delay signal starts timing from the high level, and when the timing reaches 15 microseconds and the output of the comparing unit 204 is still at the high level, the first delay signal is switched to the low level, so that the R terminal of the D flip-flop 203 is set to 0, and the off signal for driving the PWM is generated; when the D flip-flop 203 outputs the off signal for driving the PWM, the second delay signal starts timing from a high level, and when the timing reaches 70 microseconds, if the D flip-flop 203 still outputs the off signal for driving the PWM, the second delay signal is switched to a low level, thereby forming an on signal for driving the PWM; it can be understood that the delay time of the first delay signal and the delay time of the second delay signal can be selected according to the operating state of the electronic ballast, and the exemplary driving transistor of the bridge driving circuit in the electronic ballast can be turned off for a time longer than the turn-on time, that is, the time of the first delay signal is shorter than the time of the second delay signal, thereby ensuring high operating efficiency of the electronic ballast.
According to the technical scheme of the embodiment, the specific time length of the first delay signal and the second delay signal is set, so that the high working efficiency of the electronic ballast is ensured when the normal driving PWM signal is formed.
Optionally, with continued reference to fig. 5, the second single chip microcomputer 301 further includes a commutation signal output end HZO, and the commutation signal output end HZO is electrically connected to the commutation signal input end HZ;
the second one-chip microcomputer 301 is used for outputting a reversing signal to the first one-chip microcomputer 11.
The commutation signal can also be generated by the second singlechip 301 and output to the first singlechip 11, thereby further reducing the configuration requirement on the first singlechip 11 and being more beneficial to saving the cost. It will be appreciated that the commutation signal may initially be generated from the first falling edge of the drive PWM and transmitted to the first monolithic processor 11, thereby avoiding the simultaneous conduction of the upper and lower transistors of the bridge drive circuit in the electronic ballast.
And because the drive PWM signal can feedback control the median voltage signal, the commutation signal and the peak detection signal through the electronic ballast and the electronic ballast drive control circuit, exemplarily, the commutation signal is generated only when the first falling edge of the drive PWM starts, and the control of the bridge drive circuit module in the electronic ballast by the drive PWM signal will affect the median voltage signal and the peak detection signal in the electronic ballast, and the commutation signal, the median voltage signal and the peak detection signal will affect the drive PWM signal, thereby realizing the closed-loop control and being beneficial to improving the working stability of the electronic ballast drive control circuit.
Optionally, the frequency of the commutation signal is 200 Hz.
It will be appreciated that the frequency of the commutation signal can be specifically adjusted depending on the operating state of the electronic ballast.
Optionally, referring to fig. 6, fig. 6 is a schematic circuit structure diagram of a peak signal detection circuit according to an embodiment of the present invention; the input end of the peak value signal detection circuit is electrically connected with the output end of the resonance inductor of the electronic ballast, and the output end CS1 of the peak value signal detection circuit is electrically connected with the input end of the peak value detection signal.
Specifically, the peak signal detection circuit includes a first input terminal ZCD0 and a second input terminal ZCD1, which are respectively and correspondingly connected to two terminals of a resonant inductor in the electronic ballast, a second power source VCC1 is connected to a collector of the fourth transistor 303 for supplying power to the fourth transistor 303, and a third power source VCC2 for supplying a turn-on signal of the sixth transistor 302 and limiting a voltage of an output terminal CS1 of the peak signal detection circuit; a first pole of the fifth resistor 309 is electrically connected to the first input terminal ZCD0 of the peak signal detecting circuit, a second pole of the fifth resistor is electrically connected to the base of the fourth transistor 303, a collector of the fourth transistor 303 is electrically connected to the second power source VCC1, an emitter of the fourth transistor 303 is electrically connected to the first pole of the sixth resistor 307, the second pole of the sixth resistor 307 is electrically connected to the first pole of the first capacitor 304, the second pole of the first capacitor 304 is grounded, the first pole of the seventh resistor 308 is electrically connected to the third power source VCC2, the second pole of the seventh resistor 308 is electrically connected to the first pole of the fifth transistor 301, the second pole of the fifth transistor 301 is grounded, a gate of the fifth transistor serves as the PWM signal input terminal PWM1 of the peak signal detecting circuit, the first pole of the eighth resistor 310 is electrically connected to the first pole of the fifth transistor 301, the second pole of the eighth resistor 310 is electrically connected to the gate of the sixth transistor 302, a first pole of the sixth transistor 302 is electrically connected to the first pole of the first capacitor 304, a second pole of the sixth transistor 302 is grounded, a first pole of the ninth resistor 306 is electrically connected to the second input ZCD1 of the peak signal detection circuit, a second pole of the ninth resistor 306 is electrically connected to the anode of the first diode 305, the cathode of the first diode 305 is grounded, and the second pole of the ninth resistor 306 serves as the output CS1 of the peak signal detection circuit; when the signal is input to the first input terminal ZCD0, the fourth transistor 303 is turned on, the first capacitor 304 starts to be charged, and the input signal of the first input terminal ZCD0 is sent to the output terminal CS1, and when the input signal reaches a maximum value, the charge stored in the first capacitor 304 also reaches the maximum value, and when the input signal decreases at the next time, the output terminal CS1 still maintains the maximum value due to the energy storage effect of the capacitor, so that it can be determined that the input signal reaches the maximum value. And because the driving PWM is a low-frequency square wave signal, when the driving PWM is at a high level, the fifth transistor 301 is turned on, so that the sixth transistor 302 is turned off, and the first capacitor 304 can be charged, and when the driving PWM is at a low level, the fifth transistor 301 is turned off and the sixth transistor 302 is turned on, so that the first capacitor 304 starts to discharge, thereby ensuring that the peak signal detection circuit can detect the peak value in each square wave period.
Alternatively, referring to fig. 7, fig. 7 is a schematic circuit structure diagram of a median signal detection circuit according to an embodiment of the present invention, in which an input end MV2 of the median signal detection circuit is electrically connected to a resonant capacitor in an electronic ballast, an output end MV1 of the median signal detection circuit is electrically connected to a median voltage signal input end, a first pole of a tenth resistor 401 is electrically connected to an input end MV2 of the median signal detection circuit, a second pole of a tenth resistor 401 is electrically connected to a first pole of a second fuse 403, a second pole of the second capacitor 403 is grounded, a first pole of an eleventh resistor 404 is electrically connected to a first pole of the second capacitor 403, a second pole of the eleventh resistor 404 is grounded, the first pole of the eleventh resistor 404 serves as an output end MV1 of the median signal detection circuit, a cathode of a second diode 402 is connected to a third power source VCC2, and an anode of the second diode 402 is electrically connected to the first pole of the eleventh resistor 404.
It will be appreciated that a resonant capacitor is included in the electronic ballast and the input MV2 of the median signal detection circuit is electrically connected to the resonant capacitor in the electronic ballast so that a turn-on signal for driving the PWM can be formed by detecting the median voltage signal.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. The electronic ballast driving control circuit is characterized by comprising a first single chip microcomputer, wherein the first single chip microcomputer comprises a configurable logic unit CLC peripheral, a reversing signal input end, a median voltage signal input end and a peak detection signal input end;
the CLC peripheral is used for synthesizing a reversing signal input by the reversing signal input end and a median voltage signal input by the median voltage signal input end into a starting signal for driving PWM, and comparing a detection signal of the peak detection signal input end with a reference voltage to generate a closing signal for driving PWM;
the PWM opening signal is used for driving a driving transistor of the bridge type driving circuit module to be turned on, and the PWM closing signal is used for driving the driving transistor of the bridge type driving circuit module to be turned off;
the medium voltage signal is obtained by sampling a resonant capacitor connected in parallel with a driving transistor of a bridge type driving circuit module in the electronic ballast;
the detection signal of the peak detection signal input end is a corresponding voltage signal when the current of a driving transistor in a bridge type driving circuit module in the electronic ballast reaches the maximum value.
2. The electronic ballast drive control circuit according to claim 1, wherein the CLC peripheral comprises an exclusive or gate, a not gate, a D flip-flop, and a comparison unit;
a first input end of the exclusive-or gate is electrically connected with the reversing signal input end, and a second input end of the exclusive-or gate is electrically connected with the median voltage input end;
the input end of the NOT gate is electrically connected with the output end of the exclusive-OR gate, and the output end of the NOT gate is electrically connected with the clock signal end of the D trigger;
a first input end of the comparison unit is electrically connected with the peak detection signal input end, a second input end of the comparison unit inputs the reference voltage, and an output end of the comparison unit is electrically connected with an R end of the D trigger;
and the output end of the D trigger is electrically connected with the PWM signal output end of the first singlechip and is used for outputting the driving PWM.
3. The electronic ballast drive control circuit according to claim 2, wherein the CLC peripheral further comprises an and gate; the first single chip microcomputer further comprises a first delay signal input end; the output end of the comparison unit is electrically connected with the R end of the D trigger through the AND gate;
the first input end of the AND gate is electrically connected with the first delay signal input end, the second input end of the AND gate is electrically connected with the output end of the comparison unit, and the output end of the AND gate is electrically connected with the R end of the D trigger.
4. The electronic ballast drive control circuit according to claim 3, wherein the first single chip further comprises a second delay signal input;
and the S end of the D trigger is electrically connected with the second delay signal input end.
5. The driving control circuit of the electronic ballast according to claim 4, further comprising a second single chip microcomputer, wherein the second single chip microcomputer comprises a first delay signal output terminal and a second delay signal output terminal, the first delay signal output terminal is electrically connected to the first delay signal input terminal, the second delay signal output terminal is electrically connected to the second delay signal input terminal, and the second single chip microcomputer is configured to input a first delay signal to the second delay signal input terminal and a second delay signal to the second delay signal input terminal.
6. The electronic ballast drive control circuit according to claim 5, wherein the delay time duration of the first delay signal is 15 microseconds, and the delay time duration of the second delay signal is 70 microseconds.
7. The electronic ballast drive control circuit according to claim 5, wherein the second single chip further comprises a commutation signal output, the commutation signal output being electrically connected to the commutation signal input;
the second singlechip is used for outputting a reversing signal to the first singlechip.
8. The electronic ballast drive control circuit of claim 7, wherein the frequency of the commutation signal is 200 Hz.
9. The electronic ballast drive control circuit according to claim 2, further comprising a peak signal detection circuit, wherein an input of the peak signal detection circuit is electrically connected to the output of the resonant inductor of the electronic ballast, and an output of the peak signal detection circuit is electrically connected to the peak detection signal input.
10. The electronic ballast drive control circuit according to claim 2, further comprising a median signal detection circuit, wherein an input of the median signal detection circuit is electrically connected to a resonant capacitor in the electronic ballast, and an output of the median signal detection circuit is electrically connected to a median voltage signal input.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811417901.5A CN109275253B (en) | 2018-11-26 | 2018-11-26 | Electronic ballast drive control circuit |
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| CN201811417901.5A CN109275253B (en) | 2018-11-26 | 2018-11-26 | Electronic ballast drive control circuit |
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| CN109275253B true CN109275253B (en) | 2020-09-15 |
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| CN101237739B (en) * | 2007-05-18 | 2011-04-20 | 张福明 | HID rectifier and its control method |
| CN102364864A (en) * | 2011-10-28 | 2012-02-29 | 西安交通大学 | Pulse width modulation (PWM) control circuit and control method for peak current mode inverter |
| CN202586751U (en) * | 2012-05-30 | 2012-12-05 | 西安航天民芯科技有限公司 | High-precision AC/DC converter current-limiting circuit |
| JP6015421B2 (en) * | 2012-12-20 | 2016-10-26 | 富士電機株式会社 | Quasi-resonant switching power supply |
| CN205389172U (en) * | 2016-02-25 | 2016-07-20 | 成都大奇鹰科技有限公司 | Soft starting switch power based on digital control |
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