CN109274367A - A kind of anti-charge pump mismatch pulls in the phase discriminator that range causes limitation to phaselocked loop - Google Patents
A kind of anti-charge pump mismatch pulls in the phase discriminator that range causes limitation to phaselocked loop Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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Abstract
The invention discloses a kind of anti-charge pump mismatch to pull the phase discriminator that range causes limitation to phaselocked loop, it include: first and second NAND gate, the first to the tenth phase inverter, wherein the first input end of the first NAND gate connects reference clock, its second input terminal connects the output end of the second NAND gate, and second the first input end of NAND gate connect the output end of the first NAND gate, and its second input terminal connects feedback clock；The output end of first NAND gate is separately connected the input terminal of first, third phase inverter, and first phase inverter is connected with the second phase inverter, and the output end of the output end of the second phase inverter, the input terminal of the 4th phase inverter and the 5th phase inverter is connected in node；The output end of third phase inverter, the output end of the 4th phase inverter, the 5th phase inverter input terminal be connected in nodeDN；The output end of second NAND gate is separately connected the input terminal of the 6th and the 8th phase inverter.Deadbanding is not present in the present invention, can eliminate charge pump mismatch and pull scope limitation to phaselocked loop.
Description
Technical field
The present invention relates to a kind of anti-charge pump mismatch to pull the phase discriminator that range causes limitation to phaselocked loop, belongs to phase discriminator
Technical field.
Background technique
Phase discriminator (Phase Detector, abbreviation PD) is most of phaselocked loop (Phase_Locked Loop, abbreviation
PLL) the indispensable module of circuit.By PD, the lead lag relationship between reference clock and feedback clock is extracted, after the filtering
Control oscillator, the final alignment for realizing reference clock and feedback clock phase, to achieve the purpose that frequency locking.
In recent years, demand of the application such as high-speed interface to wide scope PLL is more more and more intense, and PLL at work may
In face of large range of frequency fluctuation, this requires phaselocked loops to pull range with enough.Phaselocked loop based on charge pump is
A kind of common phaselocked loop classification, ideal charge pump pull-up and pull-down current be it is stringent matched, although circuit designers are not
Disconnected Optimal improvements reduce mismatch, but charge pump mismatch can not be avoided by completely.And charge pump mismatch will lead in frequency
When deviation is larger, charge pump output error, and then limit phaselocked loop pulls in range.
Summary of the invention
Technical problem to be solved by the present invention lies in overcome the deficiencies of the prior art and provide a kind of anti-charge pump mismatch pair
The range that phaselocked loop pulls in causes the phase discriminator of limitation, by optimization phase discriminator output timing and transmission characteristic, to solve charge pump
Mismatch pulls in the problem of influence of range to phaselocked loop, avoids phaselocked loop losing lock in the limiting case.
The present invention specifically uses following technical scheme to solve above-mentioned technical problem:
A kind of anti-charge pump mismatch pulls in the phase discriminator that range causes limitation to phaselocked loop, comprising: the first NAND gate, second
NAND gate, the first to the tenth phase inverter, wherein the first input end of the first NAND gate meets reference clock CLKref, the first NAND gate
The second input terminal connect the second NAND gate output end and the second NAND gate first input end connect the first NAND gate it is defeated
Outlet, and the second input terminal of the second NAND gate meets feedback clock CLKfb；The output end of first NAND gate is separately connected
The output end of the input terminal of first phase inverter, third phase inverter, first phase inverter is connected with the input terminal of the second phase inverter,
And second output end, the input terminal of the 4th phase inverter and the output end of the 5th phase inverter of phase inverter be connected in node
Output end, the output end of the 4th phase inverter and the input terminal of the 5th phase inverter of the third phase inverter are connected in node DN；
The output end of second NAND gate is separately connected the input terminal of hex inverter and the 8th phase inverter, and the hex inverter is defeated
Outlet is connected with the input terminal of the 7th phase inverter, and the input terminal and the tenth of the output end of the 7th phase inverter, the 9th phase inverter
The output end of phase inverter is connected in nodeThe output end and the tenth of the output end of 8th phase inverter, the 9th phase inverter
The input terminal of phase inverter is connected in node UP.
Further, as a preferred technical solution of the present invention, the output timing of the phase discriminator are as follows:
As feedback clock CLKfbAdvanced reference clock CLKrefAnd phase differenceWhen, the output signal pulses of node UP
Width isThe output signal pulses width of node DN is π；
As reference clock CLKrefWith feedback clock CLKfbPhase alignment and phase differenceWhen, the output letter of node UP
Number pulse width is π, and the output signal pulses width of node DN is π；
As feedback clock CLKfbLag reference clock CLKrefAnd phase differenceWhen, the output signal pulses of node UP are wide
Degree is π, and the output signal pulses width of node DN is
Further, as a preferred technical solution of the present invention, the phase discriminator input phase is poorTo charge pump
Export electric current IoutTransfer function are as follows:
Wherein, α is the ionic size mismatch of charge pump；KPDFor the gain of phase discriminator, ICPFor the standard charge and discharge electricity of charge pump
Stream.
Further, as a preferred technical solution of the present invention, phaselocked loop where the phase discriminator pulls in model
Enclose δ ωPAre as follows:
Wherein, α is the ionic size mismatch of charge pump；δωLFor the lock-in range of phaselocked loop.
The present invention by adopting the above technical scheme, can have the following technical effects:
Anti- charge pump mismatch of the invention pulls in the phase discriminator that range causes limitation to phaselocked loop, utilizes the charge optimized
Output timing and transmission characteristic are pumped, the influence of charge pump mismatch bring can be weakened and offset, so that charge pump mismatch causes to lock
Phase ring pull in range reduce the problem of be resolved.In addition, deadbanding is not present in the phase discriminator in the present invention, it is dead for eliminating
The problem of reset signal in area causes limitation to phase discriminator operating rate is solved.The present invention has compared to traditional phase discriminator to disappear
Except charge pump mismatch pulls scope limitation to phaselocked loop, and suitable for higher frequency phase demodulation environment the characteristics of.
Detailed description of the invention
Fig. 1 is that the anti-charge pump mismatch of the present invention pulls the phase discriminator structural schematic diagram that range causes limitation to phaselocked loop.
Fig. 2 is the schematic diagram for verifying existing classics charge pump used by phase discriminator effect in the present invention.
Fig. 3 is the sequential relationship schematic diagram of phase discriminator of the present invention.
Fig. 4 is the transfer curve figure after the existing classical charge pump cascade of phase discriminator of the present invention and Fig. 2.
Fig. 5 is the simulation result of phase discriminator output timing of the present invention.
Fig. 6 is that phase discriminator of the present invention cascades the output response figure after existing classical charge pump.
Fig. 7 is to pull process simulation figure after the present invention applies in phaselocked loop.
Fig. 8 is to pull response analogous diagram when initial frequency difference is larger after the present invention applies in phaselocked loop.
Specific embodiment
Embodiments of the present invention are described with reference to the accompanying drawings of the specification.
As shown in Figure 1, the present invention, which devises a kind of anti-charge pump mismatch, pulls the phase demodulation that range causes limitation to phaselocked loop
Device specifically includes: the first NAND gate NAND1, the second NAND gate NAND2, the first phase inverter INV1, the second phase inverter INV2,
Three phase inverter INV3, the 4th phase inverter INV4, the 5th phase inverter INV5, hex inverter INV6, the 7th phase inverter INV7, the 8th
Phase inverter INV8, the 9th phase inverter INV9, the tenth phase inverter INV10, wherein the NAND1 first input end of the first NAND gate connects ginseng
Examine clock CLKref, the second input terminal of the first NAND gate NAND1 connect the second NAND gate NAND2 output end and second with it is non-
The first input end of door NAND2 connects the output end of the first NAND gate NAND1, and the second input terminal of the second NAND gate NAND2
Meet feedback clock CLKfb；The output end of the first NAND gate NAND1 is separately connected the first phase inverter INV1, third phase inverter
The output end of the input terminal of INV3, the first phase inverter INV1 is connected with the input terminal of the second phase inverter INV2, and second is anti-
Output end, the input terminal of the 4th phase inverter INV4 and the output end of the 5th phase inverter INV5 of phase device INV2 is connected in nodeThe output end of the third phase inverter INV3, the output end of the 4th phase inverter INV4 and the 5th phase inverter INV5 it is defeated
Enter end and is connected in node DN；The output end of the second NAND gate NAND2 is separately connected hex inverter INV6 and the 8th reverse phase
The input terminal of device INV8, the hex inverter INV6 output end are connected with the input terminal of the 7th phase inverter INV7, and the 7th is anti-
Output end, the input terminal of the 9th phase inverter INV9 and the output end of the tenth phase inverter INV10 of phase device INV7 is connected in nodeThe output end of the 8th phase inverter INV8, the output end of the 9th phase inverter INV9 and the tenth phase inverter INV10 it is defeated
Enter end and is connected in node UP.
Fig. 2 is the schematic diagram for verifying existing classics charge pump used by phase discriminator effect in the present invention.The present invention
In phase discriminator each node UP,DN、Output signal be coupled with the switch control of the same name of existing classical charge pump
End processed, with control pull-up and pull-down current.The ionic size mismatch of charge pump indicates with α, α=Iup/Idn。
Fig. 3 is the sequential relationship schematic diagram of phase discriminator in the present invention.The phase demodulation output timing are as follows: feedback clock CLKfbIt is super
Preceding reference clock CLKrefAnd phase differenceWhen, node UP output signal pulses width isThe output of node DN is believed
Number pulse width is π；Reference clock CLKrefWith feedback clock CLKfbPhase alignment and phase differenceWhen, node UP's is defeated
Signal pulse width is π out, and the output signal pulses width of node DN is π；Feedback clock CLKfbLag reference clock CLKrefAnd
Phase differenceWhen, the output signal pulses width of node UP is π, and the output signal pulses width of node DN isFrom
In Fig. 2 it can be seen that in phase difference very little or alignment, the output signal of node UP and the pulse width of node DN output signal
About π, deadbanding are eliminated.
Fig. 4 is phase discriminator input phase difference to charge after the existing classical charge pump cascade of phase discriminator and Fig. 2 of the invention
The transfer curve of pump output electric current.The ionic size mismatch of charge pump is α, wherein α=Iup/Idn, phase discriminator is input to charge
Pump output signal IoutTransfer function such as formula (1-1) shown in:
Wherein, KPDFor the gain of phase discriminator, ICPFor the standard charging and discharging currents of charge pump,For the phase of phase discriminator input
Potential difference.
The transfer function in phase discriminator sequential relationship schematic diagram and Fig. 4 of the present invention according to Fig.3, can further push away
Export ionic size mismatch α pulls in the influence of range to phaselocked loop.Specifically:
According to Tsutomu Yoshimura et al. opinion delivered on IEEE trans.Circuits Syst.I in 2013
Text " Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-
Range model is pulled in described in Locked Loop ", the average value response of charge pump output is correct in one cycle, then
Difference on the frequency at this time is just within the scope of pulling in.If the difference between target frequency and original oscillator frequency is Δ ω, t moment
Shown in difference on the frequency such as formula (1-2):
Wherein, KFLFor loop filter gain, KVCOFor oscillator gain.In conjunction with the transfer function (1-1) in the present invention
Formula, it is assumed that α < 1, (1-2) formula it is rewritable at:
Wherein t0For phase differenceInitial time, t1It is defined asAt the time of, t2Be defined as pull-up and under
At the time of sourcing current complete equipilibrium, t3For phase differenceAt the time of.It is phase by frequency integrator, can acquires:
The average value that charge pump exports in a cycleIt may be expressed as:
The case where enabling above formula be equal to 0, phase lock loop locks range is greater than for Δ ω, the solution of above formula are as follows:
For the 0.6 < α < 1 of condition that above formula is set up, easily meet in circuit design.Actually ionic size mismatch α is general
It is considered that being greater than 0.9.Therefore, apply the phaselocked loop where phase discriminator of the invention pulls in range δ ωPAre as follows:
Wherein, δ ωLFor the lock-in range of phaselocked loop.For the 0.6 < α < 1 of condition that above formula is set up, in circuit design
Easily meet.Actually ionic size mismatch α can be generally considered as being greater than 0.9.
The phaselocked loop that following formula (1-10) show existing general tri-state (Tri-State) phase discriminator pulls in range expression
Formula, formula (1-11) are that the phaselocked loop of existing general flip type (Flip-Flop) phase discriminator pulls in range expression.
(1-9) formula of the invention is pulled in into range δ ωPIn contrast to the existing general tri-state (Tri-State) of formula (1-10)
Phase discriminator and existing general flip type (Flip-Flop) phase discriminator of formula (1-11) pull in range, it is found that in the present invention
Phase discriminator have and bigger pull in range.The case where α > 1, can also be acquired with same method.
In the present invention, since in phase alignment, the output signal of node UP and node DN all have the signal of half period
The problem of width, there is no deadbanding, therefore do not need one reset signal of introducing and come deadband eliminating, reset signal width pair
The limitation of phase discriminator operating rate is eliminated.
Fig. 5 is the simulation result of phase discriminator output timing of the invention, consistent with the timing of design.Fig. 6 is present invention mirror
Phase device cascades the output response after existing classical charge pump, discharges when feedback clock is advanced, charges when feedback clock lag,
The stable signal of output common mode when phase difference is 0, the spuious of generation can be eliminated by subsequent filtering.Fig. 7 is present invention mirror
Response analogous diagram is pulled in when initial frequency difference is larger after phase device is applied in phaselocked loop, if ionic size mismatch α=0.8, phaselocked loop
Target frequency is 5GHZ, and oscillator original frequency is set to 0 and 50GHz respectively.Fig. 8 (a) is oscillator original frequency when being 0Hz
Pull in response, it can be seen that current potential rises, and phaselocked loop pulls up by frequency；Fig. 8 (b) is that oscillator original frequency is 100GHz
When pull in response, it can be seen that current potential decline, phaselocked loop pulls down by frequency.As can be seen from Figure 8 the mirror in the present invention
Phase device, when initial frequency difference is larger, so that phaselocked loop pulls in response correctly.
To sum up, phase discriminator of the invention can be weakened and be supported using the charge pump output timing and transmission characteristic optimized
The charge pump mismatch that disappears bring influences, and is resolved so that charge pump mismatch causes phaselocked loop to pull in the problem of range reduces.And
There is no deadbanding, the reset signal for deadband eliminating causes the problem of limiting to be solved phase discriminator operating rate.This
Invention compared to traditional phase discriminator there is elimination charge pump mismatch to pull scope limitation to phaselocked loop, and suitable for higher frequency
The characteristics of phase demodulation environment.
Embodiments of the present invention are explained in detail above in conjunction with attached drawing, but the present invention is not limited to above-mentioned implementations
Mode within the knowledge of a person skilled in the art can also be without departing from the purpose of the present invention
It makes a variety of changes.
Claims (4)
1. a kind of anti-charge pump mismatch to phaselocked loop pull in range cause limitation phase discriminator characterized by comprising first with
NOT gate, the second NAND gate, the first to the tenth phase inverter, wherein the first input end of the first NAND gate meets reference clock CLKref, the
Second input terminal of one NAND gate connect the second NAND gate output end and the second NAND gate first input end connection first with
The output end of NOT gate, and the second input terminal of the second NAND gate meets feedback clock CLKfb；The output end of first NAND gate point
The input terminal of the first phase inverter, third phase inverter, the input of the output end and the second phase inverter of first phase inverter are not connected
End is connected, and the output end of the output end of the second phase inverter, the input terminal of the 4th phase inverter and the 5th phase inverter is connected in section
PointOutput end, the output end of the 4th phase inverter and the input terminal of the 5th phase inverter of the third phase inverter are connected in section
Point DN；The output end of second NAND gate is separately connected the input terminal of hex inverter and the 8th phase inverter, and the described 6th is anti-
Phase device output end is connected with the input terminal of the 7th phase inverter, and the input terminal of the output end of the 7th phase inverter, the 9th phase inverter with
And the tenth the output end of phase inverter be connected in nodeThe output end of 8th phase inverter, the 9th phase inverter output end with
And the tenth the input terminal of phase inverter be connected in node UP.
2. anti-charge pump mismatch pulls the phase discriminator that range causes limitation to phaselocked loop according to claim 1, feature exists
In the output timing of the phase discriminator are as follows:
As feedback clock CLKfbAdvanced reference clock CLKrefAnd phase differenceWhen, the output signal pulses width of node UP isThe output signal pulses width of node DN is π；
As reference clock CLKrefWith feedback clock CLKfbPhase alignment and phase differenceWhen, the output signal pulses of node UP
Width is π, and the output signal pulses width of node DN is π；
As feedback clock CLKfbLag reference clock CLKrefAnd phase differenceWhen, the output signal pulses width of node UP is
The output signal pulses width of π, node DN is
3. anti-charge pump mismatch pulls the phase discriminator that range causes limitation to phaselocked loop according to claim 1, feature exists
In the phase discriminator input phase is poorTo charge pump output current IoutTransfer function are as follows:
Wherein, α is the ionic size mismatch of charge pump；KPDFor the gain of phase discriminator, ICPFor the standard charging and discharging currents of charge pump.
4. anti-charge pump mismatch pulls the phase discriminator that range causes limitation to phaselocked loop according to claim 1, feature exists
In phaselocked loop where the phase discriminator pulls in range δ ωPAre as follows:
Wherein, α is the ionic size mismatch of charge pump；δωLFor the lock-in range of phaselocked loop.
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|---|---|---|---|---|
| JPH0879063A (en) * | 1994-08-31 | 1996-03-22 | Internatl Business Mach Corp <Ibm> | Phase lock loop circuit and pulse supply/generation |
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| US20080024230A1 (en) * | 2006-07-13 | 2008-01-31 | Itt Manufacturing Enterprises, Inc. | Low noise phase locked loop with a high precision lock detector |
| US20080129352A1 (en) * | 2006-11-30 | 2008-06-05 | Gang Zhang | Linear phase frequency detector and charge pump for phase-locked loop |
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-
2018
- 2018-09-05 CN CN201811031298.7A patent/CN109274367A/en active Pending
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|---|---|---|---|---|
| JPH0879063A (en) * | 1994-08-31 | 1996-03-22 | Internatl Business Mach Corp <Ibm> | Phase lock loop circuit and pulse supply/generation |
| US20060076991A1 (en) * | 2004-10-07 | 2006-04-13 | International Business Machines Corporation | Low power high frequency phase detector |
| US20080024230A1 (en) * | 2006-07-13 | 2008-01-31 | Itt Manufacturing Enterprises, Inc. | Low noise phase locked loop with a high precision lock detector |
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Application publication date: 20190125 |