CN109273439A - A kind of power device protection chip and preparation method thereof - Google Patents
A kind of power device protection chip and preparation method thereof Download PDFInfo
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- CN109273439A CN109273439A CN201811071382.1A CN201811071382A CN109273439A CN 109273439 A CN109273439 A CN 109273439A CN 201811071382 A CN201811071382 A CN 201811071382A CN 109273439 A CN109273439 A CN 109273439A
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- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present invention provides a kind of power device protection chip and preparation method thereof, comprising: in the epitaxial layer of one conduction type of upper surface of substrate growth regulation of the first conduction type；The the first ladder groove and the second ladder groove to successively decrease from top to bottom in width is formed in the epitaxial layer；Form through the epitaxial layer and extend to the isolated groove of the substrate；First medium layer is formed in the side wall of the first ladder groove, the second ladder groove and the isolated groove；Second dielectric layer is formed in the isolated groove；Every step in the first ladder groove and the second ladder groove is respectively formed metal layer；Surface forms third dielectric layer and front electrode on said epitaxial layer there；The front electrode also extends through the third dielectric layer and connect with the metal layer in the first ladder groove and the second ladder groove, saves chip area, and obtains higher Surge handling capability.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of power device protection chip and preparation method thereof.
Background technique
Surge protection chip is a kind of for protecting sensitive semiconductor device, keeps it special from transient voltage surge destruction
The solid-state semiconductor device not designed, it is excellent that it has that clamp coefficient is small, small in size, response is fast, leakage current is small and reliability is high etc.
Point, thus be widely used on voltage transient and carrying out surge protection.Low capacitor surge protection chip is suitable for high-frequency electrical
The protection device on road reduces the decaying of high-frequency circuit signal because it can reduce interference of the parasitic capacitance to circuit.
The transient voltage that static discharge (ESD) and some other voltage surge form occur at random is typically found in each
In kind electronic device.As semiconductor devices increasingly tends to miniaturization, high density and multi-functional, electronic device be increasingly easy by
To the influence of voltage surge, fatal harm is even resulted in.Various voltage surges can induce wink from static discharge to lightning etc.
State current spike, surge protection chip is commonly used to protect sensitive circuit not by the impact of surge.Based on different applications, wave
Circuit protection can be played the role of by changing the clamping voltag of surge discharge path and itself by gushing protection chip.Current function
Rate device protects chip in order to obtain higher Surge handling capability, and the chip area needed is increasing, and it is existing right not to be able to satisfy
The demand of chip area.
Summary of the invention
The present invention is based on the above problems, proposes a kind of power device protection chip and preparation method thereof, Neng Goujie
Chip area is saved, and obtains higher Surge handling capability.
In view of this, on the one hand the embodiment of the present invention proposes a kind of power device protection chip, power device protection
Chip includes:
The substrate of first conduction type；
The epitaxial layer of first conduction type, is grown on the upper surface of substrate, the epitaxial layer be respectively formed with from upper and
The the first ladder groove and the second ladder groove to successively decrease in width down；
Isolated groove through the epitaxial layer and extends to the substrate, and the isolated groove is located at first ladder
Between groove and the second ladder groove；
First medium layer is formed in the first ladder groove, the second ladder groove and the isolated groove
Side wall；
Second dielectric layer is formed in the isolated groove；
Metal layer, the every step being respectively formed in the first ladder groove and the second ladder groove；
Third dielectric layer is formed in the epitaxial layer upper surface；
First front electrode is formed in the upper surface of the third dielectric layer and through the third dielectric layer and described the
Metal layer connection in one ladder groove；
Second front electrode is formed in the upper surface of the third dielectric layer and through the third dielectric layer and described the
Metal layer connection in two ladder grooves.
Further, the height substantially phase of every step of the first ladder groove and the second ladder groove
Deng.
Further, the width of the isolated groove is greater than the width of the smallest ladder of width in the first ladder groove
50%, the width of the isolated groove is greater than 50% of the width of the smallest ladder of width in the second ladder groove.
Further, the metal of filling is in every step of the first ladder groove and the second ladder groove
Different metals.
Further, the first ladder groove and the second ladder groove are three-level ladder groove.
On the other hand the embodiment of the present invention provides a kind of production method of power device protection chip, this method comprises:
The substrate of first conduction type is provided；
The epitaxial layer of one conduction type of surface growth regulation over the substrate；
The the first ladder groove and the second ladder groove to successively decrease from top to bottom in width is formed in the epitaxial layer；
The isolated groove of the substrate is formed through the epitaxial layer and extends to, the isolated groove is located at described first
Between ladder groove and the second ladder groove；
First medium is formed in the side wall of the first ladder groove, the second ladder groove and the isolated groove
Layer；
Second dielectric layer is formed in the isolated groove；
Every step in the first ladder groove and the second ladder groove is respectively formed metal layer；
Surface forms third dielectric layer on said epitaxial layer there；
The first front electrode is formed in third dielectric layer upper surface, first front electrode also extends through the third
Dielectric layer is connect with the metal layer in the first ladder groove；
The second front electrode is formed in third dielectric layer upper surface, second front electrode also extends through the third
Dielectric layer is connect with the metal layer in the second ladder groove.
Further, the height substantially phase of every step of the first ladder groove and the second ladder groove
Deng.
Further, the width of the isolated groove is greater than the width of the smallest ladder of width in the first ladder groove
50%, the width of the isolated groove is greater than 50% of the width of the smallest ladder of width in the second ladder groove.
Further, the metal of filling is in every step of the first ladder groove and the second ladder groove
Different metals.
Further, the first ladder groove and the second ladder groove are three-level ladder groove.
The technical solution of the embodiment of the present invention is by providing the substrate of the first conduction type；Surface is grown over the substrate
The epitaxial layer of first conduction type；The the first ladder groove and second to successively decrease from top to bottom in width is formed in the epitaxial layer
Ladder groove；It is formed through the epitaxial layer and extends to the isolated groove of the substrate, the isolated groove is located at described the
Between one ladder groove and the second ladder groove；In the first ladder groove, the second ladder groove and described
The side wall of isolated groove forms first medium layer；Second dielectric layer is formed in the isolated groove；In the first ladder ditch
Every step in slot and the second ladder groove is respectively formed metal layer；Surface forms third and is situated between on said epitaxial layer there
Matter layer；The first front electrode is formed in third dielectric layer upper surface, first front electrode also extends through the third and is situated between
Matter layer is connect with the metal layer in the first ladder groove；The second front electrode is formed in third dielectric layer upper surface,
Second front electrode also extends through the third dielectric layer and connect with the metal layer in the second ladder groove, to save
Chip area, and obtain higher Surge handling capability.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below to needed in embodiment description
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, general for this field
For logical technical staff, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is the flow diagram of the production method for the power device protection chip that one embodiment of the present of invention provides；
Fig. 2 is the structural schematic diagram for the power device protection chip that one embodiment of the present of invention provides；
Fig. 3 to Fig. 9 is the knot of the production method step for the power device protection chip that one embodiment of the present of invention provides
Structure schematic diagram；
Figure 10 is the equivalent circuit diagram for the power device protection chip structure that one embodiment of the present of invention provides；
In figure: 1, substrate；2, epitaxial layer；3, the first ladder groove；31, the first sub-trenches；32, the second sub-trenches；33,
Three sub-trenches；4, the second ladder groove；5, isolated groove；6, first medium layer；7, second dielectric layer；81, first order metal layer；
82, second level metal layer；83, third level metal layer；9, third dielectric layer；10, the first front electrode；11, the second front electrode；
A1, first diode；A2, the second diode；A3, third diode；B1, the 4th diode；B2, the 5th diode；B3, the 6th
Diode.
Specific embodiment
It below will the present invention will be described in more detail refering to attached drawing.In various figures, identical element uses similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use that " A is directly on B herein to describe located immediately at another layer, another region above scenario
The expression method of face " or " A on B and therewith abut ".In this application, " A is in B " indicates that A is located in B, and
And A and B is abutted directly against, rather than A is located in the doped region formed in B.
In this application, term " semiconductor structure " refers to entire half formed in each step of manufacturing semiconductor devices
The general designation of conductor structure, including all layers formed or region.
Many specific details of the invention, such as structure, material, the size, processing side of device are described hereinafter
Method and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
Below in conjunction with Fig. 1 to Figure 10 to a kind of power device protection chip provided in an embodiment of the present invention and preparation method thereof
It is described in detail.
Referring next to attached drawing, a kind of production method of power device of embodiment of the present invention protection chip is explained in detail
It states.
As depicted in figs. 1 and 2, the production method of power device protection chip includes:
Step S01: the substrate 1 of the first conduction type is provided；In the outer of 1 upper surface growth regulation of substrate, one conduction type
Prolong layer 2；
Step S02: the first ladder groove 3 and second-order to successively decrease from top to bottom in width is formed in the epitaxial layer 2
Terraced groove 4；
Step S03: form through the epitaxial layer 2 and extend to the isolated groove 5 of the substrate 1, the isolated groove 5
Between the first ladder groove 3 and the second ladder groove 4；
Step S04: in the side wall of the first ladder groove 3, the second ladder groove 4 and the isolated groove 5
Form first medium layer 6；
Step S05: second dielectric layer 7 is formed in the isolated groove 5；
Step S06: every step in the first ladder groove 3 and the second ladder groove 4 is respectively formed
Metal layer；
Step S07: surface forms third dielectric layer 9 on the epitaxial layer 2；In the 9 upper surface shape of third dielectric layer
At the first front electrode 10, first front electrode 10 is also extended through in the third dielectric layer 9 and the first ladder groove 3
Metal layer connection；The second front electrode 11 is formed in 9 upper surface of third dielectric layer, second front electrode 11 also passes through
The third dielectric layer 9 is worn to connect with the metal layer in the second ladder groove 4.
The present invention improves on the basis of conventional power devices protect chip proposes a kind of low capacitor of two-way single channel
Power device protects chip.The embodiment of the present invention in the first ladder groove 3 and the second ladder groove 4 by distinguishing
Different metal layers is filled, so that different metal layers is contacted with the epitaxial layer 2, is cascaded to form two groups
Three tunnel parallel connection Schottky diodes, not only save chip area, reduce technology difficulty, thus reduce chip manufacturing at
This, it is ensured that the stability of electric current, so that the protection feature and reliability of chip are all improved.
Specifically, first conduction type is one of p-type doping and n-type doping, and second conduction type is P
Type doping and the another kind in n-type doping.
Special to illustrate herein for convenience of description: first conduction type can be n-type doping, so that described second is conductive
Type is p-type doping；First conduction type can also adulterate for p-type, so that second conduction type is n-type doping.
In next embodiment, adulterated by p-type of first conduction type, second conduction type is that n-type doping is
Example is described, but is defined not to this.
Specifically, P type substrate and p-type extension belong to P-type semiconductor, and N-type substrate and N-type extension belong to N-type and partly lead
Body.The P-type semiconductor is the silicon wafer for adulterating triad, such as any group of boron element or phosphide element or aluminium element or three
It closes.The N-type semiconductor is any combination of the silicon wafer for adulterating pentad, such as P elements or arsenic element or both.
Attached drawing 3 is please referred to, step S01 is executed, specifically: the substrate 1 of the first conduction type is provided；On the substrate 1
The epitaxial layer 2 of one conduction type of surface growth regulation.In some embodiments of the invention, the substrate 1 is, for example, monocrystalline silicon lining
Bottom 1, and doping concentration is, for example, 1e15atoms/cm3.Wherein, in 1 upper surface growth regulation one of the substrate of the first conduction type
The mode of the epitaxial layer 2 of conduction type is not limited to a kind of fixed mode, can use epitaxial growth in 1 upper surface of substrate
It is formed, the epitaxial layer 2 can also be formed in 1 upper surface of substrate by ion implanting and/or the method for diffusion.Further
Ground can be epitaxially-formed in the 1 upper surface use of substrate, can also by ion implanting and/or diffusion P elements or
The method of any combination of arsenic element or both forms the epitaxial layer 2 in 1 upper surface of substrate.Specifically, the extension
Or the method for diffusion includes depositing operation.In some embodiments of the invention, depositing operation can be used on the substrate 1
Surface forms the epitaxial layer 2, for example, depositing operation can be selected from electron beam evaporation, chemical vapor deposition, atomic layer deposition
One of product, sputtering.Preferably, epitaxial layer 2, chemical vapor deposition are formed using chemical vapor deposition on the substrate 1
Including process for vapor phase epitaxy.In production, chemical vapor deposition uses process for vapor phase epitaxy mostly, in 1 upper surface of substrate
Epitaxial layer 2 is formed using process for vapor phase epitaxy, the perfection of silicon materials can be improved in process for vapor phase epitaxy, improves the integrated of device
Degree, reaches raising minority carrier life time, reduces the leakage current of storage element.Preferably, the epitaxial layer 2 and the substrate 1 are all silicon
Material is made, so that the substrate 1 and the epitaxial layer 2 have the silicon face of same crystal structure, to keep to dopant type
With the control of concentration.Due to autodoping effect, in epitaxial process, the dopant from the substrate 1 can enter outer
Prolong in layer 2, to change the electric conductivity of epitaxial semiconductor layer.The epitaxial layer 2 covers the upper surface of the substrate 1, and sets
There is certain thickness.It should be noted that the thickness of the epitaxial layer 2 is, for example, 3~10 microns.The epitaxial layer 2 it is intrinsic
The range of doping concentration is, for example, 1e11~1e14atoms/cm.The epitaxial layer 2 and the substrate 1 are for adjusting the function
Rate device protects the breakdown reverse voltage of chip, is not involved in form PN junction.Preferably, by adjusting from the substrate 1 to described
The doping concentration of epitaxial layer 2 can control the breakdown voltage of the power device protection chip, such as positioned at 2-48V or bigger
In the range of.
Attached drawing 4 is please referred to, step S02 is executed, specifically: it is formed in the epitaxial layer 2 and is successively decreased from top to bottom in width
The first ladder groove 3 and the second ladder groove 4.Firstly, by being prepared in the upper surface of the epitaxial layer 2 and covering first layer
Mask, the mask include the opening of whole upper surfaces of exposure the first ladder groove 3.In some embodiments of the present invention
In, the first sub-trenches 31 are formed by carrying out dry etching in the epitaxial layer 2 in the opening of the exposure mask, are continued in formation
The bottom surface of first sub-trenches 31 prepares and covers second layer exposure mask, is formed by carrying out dry etching in the epitaxial layer 2
Second sub-trenches 32, secondly, bottom surface preparation and overlays third layer exposure mask in second sub-trenches 32 of formation, by institute
It states and carries out dry etching formation third sub-trenches 33 in epitaxial layer 2, finally remove exposure mask, first sub-trenches being respectively formed
31, second sub-trenches 32 and the third sub-trenches 33 are interconnected, and a ladder groove has been integrally formed.At this point, institute
The section pattern for stating the first sub-trenches 31, second sub-trenches 32 and the third sub-trenches 33 is rectangular or rectangular shape
Or rectangle or approximate rectangular shape.Since second sub-trenches 32 are by carving in the 31 bottom surface dry method of the first sub-trenches
Erosion is formed, and the third sub-trenches 33 in the 32 underrun dry etching of the second sub-trenches by forming, therefore, described the
The width of one sub-trenches 31 is greater than the width of second sub-trenches 32, and the width of second sub-trenches 32 is greater than the third
The width of sub-trenches 33, so as to form the first ladder groove 3 to successively decrease from bottom to top in width.In other realities of the invention
It applies in example, second sub-trenches 32 are formed in the center of 31 downside of the first sub-trenches, the third sub-trenches 33
It is formed in the center of 32 downside of the second sub-trenches, so that first sub-trenches 31 and 32 phase of the second sub-trenches
The third sub-trenches 33 are symmetrical arranged.It is formed by the first ladder groove 3 in this step, for convenient in subsequent step
It is filled in rapid using filler.It should be noted that the second ladder groove 4 and the first ladder groove 3 are symmetrical
And it is identical, the manufacturing process of the second ladder groove 4 is also identical as the manufacturing process of the first ladder groove 3, therefore, institute
The forming process for stating the second ladder groove 4 can refer to the forming process of the first ladder groove 3 above-mentioned, no longer superfluous herein
It states.
Further, the first ladder groove 3 and the second ladder groove 4 are three-level ladder groove.For convenience
Illustrate, the present invention is retouched so that the first ladder groove 3 and the second ladder groove 4 are three-level ladder groove as an example
It states, but it is not limited to this, and the first ladder groove 3 and the second ladder groove 4 can also be second level ladder groove or four
Grade ladder groove or other grade of ladder groove, those skilled in the art can select different ladder grooves according to the actual situation.
Attached drawing 5 is please referred to, step S03 is executed, specifically: it is formed through the epitaxial layer 2 and extends to the substrate 1
Isolated groove 5, the isolated groove 5 is between the first ladder groove 3 and the second ladder groove 4.In the present invention
Some embodiments in, the isolation of the substrate 1 is yet formed through the epitaxial layer 2 and extended in the epitaxial layer 2
Groove 5, the isolated groove 5 is deep trench, and is contacted with the substrate 1.Specifically, the ladder groove at least two,
Isolated groove 5 is prepared between every two ladder groove, for two ladder grooves are spaced-apart.In the extension
The upper surface of layer 2 prepares and covers one layer of exposure mask, which includes the opening of whole upper surfaces of the exposure isolated groove 5,
And exposure mask is finally removed, the isolated groove is formed by carrying out dry etching in the epitaxial layer 2 in the opening of the exposure mask
5。
Attached drawing 6 is please referred to, step S04 is executed, specifically: in the first ladder groove 3, the second ladder groove 4
And the side wall of the isolated groove 5 forms first medium layer 6.Specifically, the material of the first medium layer 6 be silica or
Silicon nitride or silicon oxynitride specifically can form described first by using sputtering or thermal oxidation method or chemical vapor deposition process
Dielectric layer 6.Preferably, the first medium layer 6 is the silicon oxide layer that thermal oxide is formed, described in subsequent doping step
Silicon oxide layer is as protective layer, and by the interlayer insulating film as resulting devices.In addition, the first medium layer 6 is equipped with one
Fixed thickness, so that the first medium layer 6 plays the role of that electric current and insulation is isolated.More specifically, the first medium layer 6
It is contacted with silicon, can also preferably offset the stress of the ladder groove formed in the epitaxial layer 2.Of the invention one
In a little embodiments, after forming the first ladder groove 3, the second ladder groove 4 and the isolated groove 5, respectively
One layer of dielectric layer is formed in the front of power device protection chip, at this time the upper surface of the epitaxial layer 2, first rank
On the inner sidewall and bottom surface of terraced groove 3 and the second ladder groove 4 and the inner sidewall and bottom surface of the isolated groove 5, all
Cover one layer of dielectric layer, then by etching remove the first ladder groove 3, the second ladder groove 4 and it is described every
The dielectric layer covered on bottom surface from groove 5, and the dielectric layer of removal 2 upper surface of the first epitaxial layer covering, retain institute
State Jie on 5 side wall of dielectric layer and the isolated groove on 3 side wall of the first ladder groove and 4 side wall of the second ladder groove
Matter layer ensure that the bottom surface of the first ladder groove 3 and the second ladder groove 4 to form the first medium layer 6
It is come into full contact with respectively with the epitaxial layer 2, the bottom surface of the isolated groove 5 comes into full contact with the substrate 1, is also convenient for later
The step of in the epitaxial layer 2 upper surface carry out process flow.
Attached drawing 7 is please referred to, step S05 is executed, specifically: second dielectric layer 7 is formed in the isolated groove 5.At this
In some embodiments of invention, the material of the second dielectric layer 7 is silicon nitride, specifically can be by using sputtering or thermal oxide
Method or chemical vapor deposition process form the second dielectric layer 7.Preferably, the first medium layer 6 is the nitrogen that nitridation is formed
SiClx layer, since the isolated groove 5 is deep trench, deep trench be easy to cause the increase of stress in forming process to cause silicon
Piece warpage, therefore need to increase by 5 width of isolated groove during etching forms groove to achieve the purpose that reduce stress, but
It is that will increase manufacturing cost in this way, is answered at this point, the structure of silicon nitride oxygenation SiClx can reduce in the smallest situation of groove area
Power, and silicon nitride is formed in the isolated groove 5, the silicon and silica of the power device protection chip interior can be made
Interface and silica and silicon nitride interface stress direction just on the contrary, to offset each other stress.
Further, the doping concentration of the substrate 1 is higher than the doping concentration of the epitaxial layer 2.Of the invention some
In embodiment, during growing epitaxial layer 2 on the substrate 1, since the epitaxial layer 2 is in the base of the substrate 1
It is formed on plinth, therefore the doping concentration of the substrate 1 is higher than the doping concentration of the epitaxial layer 2.The electricity of the epitaxial layer 2 at this time
Resistance rate is higher than the resistivity of the substrate 1, so as to adjust the integral device resistivity of the power device protection chip, obtains
Obtain more Surge handling capabilities.
Attached drawing 8 is please referred to, executes step S06, specifically: in the first ladder groove 3 and the second ladder groove 4
Interior every step is respectively formed metal layer.In some embodiments of the invention, in the first ladder groove 3 and described
Every step in second ladder groove 4 is all respectively formed metal layer, thus by the first ladder groove 3 and described second
Ladder groove 4 is all filled completely, and carries out short annealing, ultimately forms the first ladder groove 3 and the second ladder ditch
Metal layer in slot 4.Due in above-mentioned steps, shape on the side wall of the first ladder groove 3 and the second ladder groove 4
At there is dielectric layer, and the dielectric layer formed on the bottom surface of the first ladder groove 3 and the second ladder groove 4 is by dry method
Etching removes, shape on the bottom surface in every step in the first ladder groove 3 and the second ladder groove 4 at this time
At dielectric layer also all removed by dry etching.Specifically, in the first ladder groove 3 and the second ladder groove 4
Every step in the metal layer that is respectively formed also through in every step bottom surface and the epitaxial layer 2 sufficiently
Contact, and the side wall in every step in the first ladder groove 3 and the second ladder groove 4 is also by metal layer
It is isolated with 2 part of epitaxial layer, therefore, in every step in the first ladder groove 3 and the second ladder groove 4
The metal layer being respectively formed forms Schottky contacts in the bottom surface of every step and the epitaxial layer 2, to be formed simultaneously
The Schottky diode of connection.
Further, the height substantially phase of every step of the first ladder groove 3 and the second ladder groove 4
Deng.It should be noted that the height substantially phase of every step of the first ladder groove 3 and the second ladder groove 4
Deng thus the height for the metal layer filled in every step of the first ladder groove 3 and the second ladder groove 4
Also roughly equal, so that the metal layer filled in every step contacts two pole of Schottky formed with the epitaxial layer 2
The resistance of pipe is roughly the same, reduces the resistance difference between each Schottky diode, to promote the Schottky diode
Reliability.
Further, the width of the isolated groove 5 is greater than the width of the smallest ladder of width in the first ladder groove 3
The 50% of degree, the width of the isolated groove 5 are greater than the width of the smallest ladder of width in the second ladder groove 4
50%, it should be noted that the first ladder groove 3 and the second ladder groove 4 are symmetrical and identical, the isolated groove
5 width is greater than 50% of the width of the smallest ladder of width in the first ladder groove 3 and the second ladder groove 4,
Substantially reduce the stress generated in power device protection chip forming process.
Further, the metal filled in every step of the first ladder groove 3 and the second ladder groove 4
For different metals.In some embodiments of the invention, the first ladder groove 3 and the second ladder groove 4 are
Therefore, in the first ladder groove 3 and the second ladder groove 4 it is big to be respectively formed with three layer heights for three-level ladder groove
Cause identical metal layer.Specifically, during the metal layer formed in the first ladder groove, first in third
Third level metal layer 83 is formed in groove 33, is then formed second level metal layer 82 in second sub-trenches 32, is finally existed
First order metal layer 81 is formed in first sub-trenches 31.More specifically, it is desirable that the Schottky of the first order metal layer 81
Barrier height is greater than the schottky barrier height of the second level metal layer 82, the Schottky barrier of the second level metal layer 82
Height is greater than the schottky barrier height of the first order metal layer 81, so that the first order metal layer 81, the second level
The Schottky diode that metal layer 82 and the third level metal layer 83 are formed with the epitaxial layer 2 respectively can be in different voltages
Lower conducting, such low pressure when, quickly open, the quick aerial drainage of high-pressure situations, further improve the power device protection core
The performance of piece.It should be noted that since the second ladder groove 4 and the first ladder groove are symmetrical and identical,
The process that three-level metal layer is formed in the second ladder groove 4 is referred to form three-level in the first ladder groove 3
The process of metal layer, details are not described herein.
Attached drawing 9 is please referred to, step S07 is executed, specifically: surface forms third dielectric layer 9 on the epitaxial layer 2；?
9 upper surface of third dielectric layer forms the first front electrode 10, and first front electrode 10 also extends through the third medium
Layer 9 is connect with the metal layer in the first ladder groove 3；The second front electrode is formed in 9 upper surface of third dielectric layer
11, second front electrode 11 also extends through the third dielectric layer 9 and connect with the metal layer in the second ladder groove 4.
In some embodiments of the invention, by annealing process, third dielectric layer 9 can be formed in the upper surface of the epitaxial layer 2,
The third dielectric layer 9 is identical as the material of the first medium layer 6, the manufacturing process of the third dielectric layer 9 and described the
The manufacturing process of one dielectric layer 6 is also identical, and therefore, the forming process of the third dielectric layer 9 can refer to the first medium
The forming process of layer 6, details are not described herein.It then proceedes to be formed in the upper surface of the third dielectric layer 9 and there is certain thickness
The first metal layer and second metal layer.In other embodiments of the invention, the first metal layer and second gold medal
It is corresponding with the first ladder groove 3 and the second ladder groove 4 respectively to belong to layer, the first metal layer and second gold medal
Belong to layer to be separated from each other, without connection.The first metal layer includes first for being formed in 9 upper surface of third dielectric layer
Point, and through the third dielectric layer 9 and the second part that is connect with the metal layer in the ladder groove, likewise, institute
It is symmetrical relative to the isolated groove 5 to state the first metal layer and the second metal layer, therefore the second metal layer also includes
Be formed in 9 upper surface of third dielectric layer first part and through the third dielectric layer 9 and with the ladder groove
The second part of interior metal layer connection.Specifically, contact hole first can be etched in 9 upper surface of third dielectric layer, in institute
It states and fills metal layer in contact hole, form the second part of the first metal layer and the second metal layer.First gold medal
Belong to layer and the second metal layer is respectively formed the first front electrode 10 and the second front electricity of the power device protection chip
Pole 11.The third dielectric layer 9 for be isolated and protect the epitaxial layer 2 and other cannot be with first front electrode 10
The structure directly contacted with second front electrode 11.
In some embodiments of the invention, the first metal layer and the second metal layer upper surface can also cover
There is passivation layer, the passivation layer is for protecting the first metal layer and the second metal layer, so that protection is entire described
Power device protects chip.
The embodiment of the present invention by filling three kinds in the first ladder groove 3 and the second ladder groove 4 respectively
Different type metal, in forward voltage work, the third level metal layer 83 contacts the Schottky formed with the epitaxial layer 2
Diode is connected earliest, and after electric current increase, the conducting resistance with power device protection chip increases, the second level
Metal layer 82 and the first order metal layer 81 contact the Schottky diode formed with the epitaxial layer 2 respectively and sequentially turn on,
It ensure that the stability of electric current, so that the Surge handling capability of power device protection chip is greatly improved.
In addition, power device provided by the invention protection chip saves chip area, it is low to reduce technology difficulty, also reduces device
Manufacturing cost.
As shown in Fig. 2, the embodiment of the present invention provides a kind of power device protection chip, shown power device protects chip packet
It includes:
The substrate 1 of first conduction type；
The epitaxial layer 2 of first conduction type, is grown on 1 upper surface of substrate, and the epitaxial layer 2 is respectively formed with from upper
And lower the first ladder groove 3 and the second ladder groove 4 to successively decrease in width；
Isolated groove 5 through the epitaxial layer 2 and extends to the substrate 1, and the isolated groove 5 is located at described first
Between ladder groove 3 and the second ladder groove 4；
First medium layer 6 is formed in the first ladder groove 3, the second ladder groove 4 and the isolated groove
5 side wall；
Second dielectric layer 7 is formed in the isolated groove 5；
Metal layer, the every step being respectively formed in the first ladder groove 3 and the second ladder groove 4；
Third dielectric layer 9 is formed in 2 upper surface of epitaxial layer；
First front electrode 10 is formed in the upper surface of the third dielectric layer 9 and through the third dielectric layer 9 and institute
State the metal layer connection in the first ladder groove 3；
Second front electrode 11 is formed in the upper surface of the third dielectric layer 9 and through the third dielectric layer 9 and institute
State the metal layer connection in the second ladder groove 4.
Specifically, first conduction type is one of p-type doping and n-type doping, and second conduction type is P
Type doping and the another kind in n-type doping.
Special to illustrate herein for convenience of description: first conduction type can be n-type doping, so that described second is conductive
Type is p-type doping；First conduction type can also adulterate for p-type, so that second conduction type is n-type doping.
In next embodiment, adulterated by p-type of first conduction type, second conduction type is that n-type doping is
Example is described, but is defined not to this.
Specifically, P type substrate and p-type extension belong to P-type semiconductor, and N-type substrate and N-type extension belong to N-type and partly lead
Body.The P-type semiconductor is the silicon wafer for adulterating triad, such as any group of boron element or phosphide element or aluminium element or three
It closes.The N-type semiconductor is any combination of the silicon wafer for adulterating pentad, such as P elements or arsenic element or both.
In some embodiments of the invention, as shown in Fig. 2, power device protection chip includes the first conduction type
Substrate 1 and the first conduction type epitaxial layer 2, the epitaxial layer 2 is grown on 1 upper surface of substrate.Specifically, the lining
Bottom 1 is the carrier in integrated circuit, and the substrate 1 plays the role of support, and the substrate 1 also assists in the work of the integrated circuit
Make.The substrate 1 can be silicon substrate, or Sapphire Substrate can also be silicon Chu substrate, it is preferred that the substrate 1
For silicon substrate, this is because silicon substrate material has the characteristics that low cost, large scale, conductive, edge effect is avoided, it can
Increase substantially yield.
In some embodiments of the invention, as shown in Fig. 2, first front electrode 10 and the first ladder groove
The part or all of upper surface of first order metal layer 81 connection in 3, second front electrode 11 and the second ladder groove 4
The interior part or all of upper surface of first order metal layer 81 connection guarantees first front electrode 10 and second front electricity
Pole 11 is golden with the first order in the first order metal layer 81 and the second ladder groove 4 in the first ladder groove 3 respectively
The contact for belonging to layer 81 is good, avoids the occurrence of poor contact.
Current Transient Voltage Suppressor is largely only adapted to form the suppression of single channel transient voltage in a chip
Device processed.In order to form multichannel Transient Voltage Suppressor, then need to form a channel unit in respective chip respectively, so
By by bonding wire, each chip is electrically connected to each other to form array.Bonding wire between chip leads to packaging cost
Increase, and introduce lead resistance and parasitic capacitance, so that the reliability of semiconductor devices reduces.
In conclusion the power device protection chip overall structure is symmetrical and is the first primitive unit cell.
Please refer to the equivalent circuit diagram of power device protection chip structure shown in Fig. 10.When to first front electrode
10 and second front electrode 11 be powered when, electric current flows to second front electrode 11 from first front electrode 10,
Or first front electrode 10 is flowed to from second front electrode 11, for convenience of describing, in embodiment below
In be described so that electric current flows to second front electrode 11 from first front electrode 10 as an example, but not therefore make
At restriction.It should be noted that the forward and reverse of PN junction formed below is set as p-type with the first conduction type, described
It is one embodiment of the present of invention to be judged that two conduction types, which are set as N-type, but also not to this restriction.Electric current first flows through
The first order metal layer 81, the second level metal layer 82 and the third level metal layer in the first ladder groove 3
83, the first order metal layer 81, the second level metal layer 82 and the third level metal layer 83 respectively with the epitaxial layer 2
It includes first diode a1, the second diode a2, third diode a3 that contact, which forms three reverse-biased Schottky diodes in parallel,
Due to the buffer action of the isolated groove 5, electric current is from the first order metal layer 81, the second level metal layer 82 and described
After third level metal layer 83 flows out, the second ladder groove 4 is flowed to along the epitaxial layer 2 and the substrate 1, described second
The first order metal layer (not shown), the second level metal layer (not shown) and third level gold in ladder groove 4
Belong to layer (not shown), the first order metal layer, the second level metal layer and the third level metal layer respectively with it is described outer
Prolonging the contact of layer 2 and forming three forward-biased diodes in parallel includes: the 4th diode b1, the 5th diode b2, the 6th diode b3,
To which power device protection chip forms the equivalent circuit for the three tunnel parallel connection Schottky diodes that two groups are cascaded.
It should be noted that since power device protection chip overall structure is symmetrical and is the first primitive unit cell, described the
One ladder groove 3, first front electrode 10 are respectively relative to the isolated groove 5 and the second ladder groove 4, described
Second front electrode 11 is symmetrical arranged.For convenience of description, the embodiment of the present invention is by taking first primitive unit cell as an example, described in specific descriptions
Power device protects the structure of chip, but is not limited only to this, and those skilled in the art can the function determines according to actual conditions
Rate device protects the specific structure of the primitive unit cell of chip.
The technical solution of the embodiment of the present invention is had been described in detail above with reference to the accompanying drawings, the embodiment of the present invention is in conventional power device
It is improved on the basis of part protection chip and proposes a kind of low Capacitance Power device protection chip of two-way single channel, by described
Three kinds of different types of metal layers are filled respectively in first ladder groove 3 and the second ladder groove 4, are worked in forward voltage
Shi Suoshu third level metal layer 83 contacts the Schottky diode formed with the epitaxial layer 2 and is connected earliest, after electric current increase,
With the increase of the conducting resistance of power device protection chip, the second level metal layer 82 and first order metal layer 81 divide
The Schottky diode formed is not contacted with the epitaxial layer 2 to sequentially turn on, the stability of electric current is ensure that, greatly improves institute
State the protection feature and reliability of power device protection chip.In addition, the improved power device protection chip of the present invention saves
Device area reduces technology difficulty, also reduces device manufacturing cost.It should be noted that first front electrode 10
With second front electrode 11 all in the front of power device protection chip, package area is reduced, a variety of envelopes are applicable in
Dress form, reduces packaging cost.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
It is as described above according to the embodiment of the present invention, these embodiments details all there is no detailed descriptionthe, also not
Limiting the invention is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is principle and practical application in order to better explain the present invention, thus belonging to making
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention is only by right
The limitation of claim and its full scope and equivalent.
Claims (10)
1. a kind of power device protects chip characterized by comprising
The substrate of first conduction type；
The epitaxial layer of first conduction type is grown on the upper surface of substrate, and the epitaxial layer is respectively formed with is in from top to bottom
The the first ladder groove and the second ladder groove that width successively decreases；
Isolated groove through the epitaxial layer and extends to the substrate, and the isolated groove is located at the first ladder groove
Between the second ladder groove；
First medium layer is formed in the side wall of the first ladder groove, the second ladder groove and the isolated groove；
Second dielectric layer is formed in the isolated groove；
Metal layer, the every step being respectively formed in the first ladder groove and the second ladder groove；
Third dielectric layer is formed in the epitaxial layer upper surface；
First front electrode is formed in the upper surface of the third dielectric layer and through the third dielectric layer and first rank
Metal layer connection in terraced groove；
Second front electrode is formed in the upper surface of the third dielectric layer and through the third dielectric layer and the second-order
Metal layer connection in terraced groove.
2. power device according to claim 1 protects chip, which is characterized in that the first ladder groove and described the
The height of every step of two ladder grooves is roughly equal.
3. power device according to claim 1 protects chip, which is characterized in that the width of the isolated groove is greater than institute
50% of the width of the smallest ladder of width in the first ladder groove is stated, the width of the isolated groove is greater than second ladder
The 50% of the width of the smallest ladder of width in groove.
4. power device according to claim 1 protects chip, which is characterized in that the first ladder groove and described the
The metal filled in every step of two ladder grooves is different metal.
5. power device according to claim 1 protects chip, which is characterized in that the first ladder groove and described the
Two ladder grooves are three-level ladder groove.
6. a kind of production method of power device protection chip comprising:
The substrate of first conduction type is provided；
The epitaxial layer of one conduction type of surface growth regulation over the substrate；
The the first ladder groove and the second ladder groove to successively decrease from top to bottom in width is formed in the epitaxial layer；
The isolated groove of the substrate is formed through the epitaxial layer and extends to, the isolated groove is located at first ladder
Between groove and the second ladder groove；
First medium layer is formed in the side wall of the first ladder groove, the second ladder groove and the isolated groove；
Second dielectric layer is formed in the isolated groove；
Every step in the first ladder groove and the second ladder groove is respectively formed metal layer；
Surface forms third dielectric layer on said epitaxial layer there；
The first front electrode is formed in third dielectric layer upper surface, first front electrode also extends through the third medium
Layer is connect with the metal layer in the first ladder groove；
The second front electrode is formed in third dielectric layer upper surface, second front electrode also extends through the third medium
Layer is connect with the metal layer in the second ladder groove.
7. a kind of production method of power device protection chip according to claim 6, which is characterized in that first rank
The height of every step of terraced groove and the second ladder groove is roughly equal.
8. a kind of production method of power device protection chip according to claim 6, which is characterized in that the isolating trenches
The width of slot is greater than 50% of the width of the smallest ladder of width in the first ladder groove, and the width of the isolated groove is big
The 50% of the width of the smallest ladder of width in the second ladder groove.
9. a kind of production method of power device protection chip according to claim 6, which is characterized in that first rank
The metal filled in every step of terraced groove and the second ladder groove is different metal.
10. a kind of production method of power device protection chip according to claim 6, which is characterized in that described first
Ladder groove and the second ladder groove are three-level ladder groove.
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