CN109256339A - The packaging method of the matching process and crimp type IGBT device of chip submodule group and boss - Google Patents
The packaging method of the matching process and crimp type IGBT device of chip submodule group and boss Download PDFInfo
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- CN109256339A CN109256339A CN201811014024.7A CN201811014024A CN109256339A CN 109256339 A CN109256339 A CN 109256339A CN 201811014024 A CN201811014024 A CN 201811014024A CN 109256339 A CN109256339 A CN 109256339A
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 17
- 238000003860 storage Methods 0.000 claims description 13
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 11
- 238000012360 testing method Methods 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 238000005538 encapsulation Methods 0.000 abstract description 5
- 238000012545 processing Methods 0.000 description 6
- 238000004590 computer program Methods 0.000 description 5
- 230000002459 sustained effect Effects 0.000 description 5
- 238000005259 measurement Methods 0.000 description 4
- 238000003672 processing method Methods 0.000 description 4
- 238000004364 calculation method Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The invention discloses the packaging methods of the matching process and crimp type IGBT device of a kind of chip submodule group and boss, the wherein matching process of chip submodule group and boss, by the way that the height tolerance of chip submodule group is grouped, then the height tolerance by the height tolerance of the chip submodule group after grouping respectively with the boss to be matched generated at random is overlapped, calculate the overall quantity matching deviation of boss to be matched, then it is compared with the second preset threshold, and the difference of boss to be matched is compensated until overall quantity matching deviation is less than the second preset threshold, and then realize chip submodule group and the one-to-one purpose of boss to be matched.The Rapid matching of chip submodule group and boss to be matched to batch may be implemented in the present invention, improve matching efficiency, and whole matching error can be made smaller, be conducive to the encapsulation of crimp type IGBT device by the matching way, and then ensure that crimp type IGBT device has good electrical characteristic.
Description
Technical field
The present invention relates to power semiconductor device package technical fields, and in particular to a kind of of chip submodule group and boss
The packaging method of method of completing the square and crimp type IGBT device.
Background technique
Crimp type IGBT device is to be packaged by using crimping packing forms to IGBT device, by chip, molybdenum sheet, gold
Belong to electrode, boss etc., is crimped together by mechanical pressure, is electrically and mechanically connected to guarantee that inter-module is good.Wherein
Chip, molybdenum sheet and metal electrode constitute the chip submodule group of crimp type IGBT device, and chip submodule group is mounted on boss
Achievable overall package.Due to the multiple chip submodule groups of crimp type IGBT device internal parallel, any two chip submodule group
Between can all have differences, including add up assembly height tolerance and chip as caused by parts machining geometric dimension difference
Electrical characteristic parameter deviation etc..Therefore, in order to reduce various deviations, to guarantee that crimp type IGBT device has better mechanicalness
Energy and electrical characteristic, it is necessary to study the matching way of chip submodule group and boss.
Currently, the matching way of traditional chip submodule group and boss, general using manually to crimp type IGBT device
The height parameter or electric parameter of chip submodule group are screened, and then, random fit is packed into the shell of crimp type IGBT device
It in boss, causes between chip submodule group and boss that there are biggish matching deviations, and then crimp type IGBT device is caused to encapsulate
Its pressure is still unevenly distributed afterwards, is still influenced the electric property of crimp type IGBT device, and the mode of artificial screening, is shown
So, efficiency is lower, and the encapsulation of the crimp type IGBT device of batch can not be rapidly completed.
Summary of the invention
In view of this, the present invention provides the matching process of a kind of chip submodule group and boss, to solve in the prior art
Chip submodule group is with the matching way of boss mainly using manually being matched, and matching error is larger, and matching efficiency is lower
Problem.
For this purpose, the present invention provides the following technical scheme that
The embodiment of the present invention provides the matching process of a kind of chip submodule group and boss, includes the following steps:
S11, the height tolerance and quantity for obtaining chip submodule group；
S12, the height tolerance progress according to the height tolerance and quantity of the chip submodule group, to the chip submodule group
Grouping, the difference of the height tolerance of the chip submodule group of two adjacent groups are the first preset threshold；
S13, the height tolerance for generating multiple boss to be matched at random, and to the height tolerance of the multiple boss to be matched
It is grouped, the difference of the height tolerance of the boss to be matched of two adjacent groups is first preset threshold；
S14, count every group respectively described in chip submodule group height tolerance corresponding number and every group described in it is to be matched convex
The corresponding number of the height tolerance of platform；
S15, the height tolerance of the boss to be matched described in every group are equal with the height tolerance of chip submodule group described in every group
When, judge every group described in boss to be matched height tolerance corresponding number and the height tolerance of chip submodule group described in every group
Whether the difference of corresponding number is greater than zero；
S16, when the difference is greater than zero, the chip submodule group and the boss to be matched are calculated according to the difference
Overall quantity matches deviation, and judges whether the overall quantity matching deviation is greater than the second preset threshold；
S17, when the overall quantity matching deviation be greater than second preset threshold when, to there are the institutes of the difference
The corresponding number of the height tolerance of boss to be matched described in stating every group carries out difference compensation；
S18, the circulation step S13- step S17, until overall quantity matching deviation is less than described second in advance
Until if threshold value matches the chip submodule group with the boss to be matched.
Optionally, the matching process of the chip submodule group and boss, further includes: when the difference is not more than zero,
The difference is reset.
Optionally, the matching process of the chip submodule group and boss, to there are described in every group of the difference to
The quantity of height tolerance with boss carries out the step of difference compensation and includes:
It searches and described there are described in immediate every group of the height tolerance of boss to be matched described in every group of the difference
The height tolerance of chip submodule group；
A number of chip is distributed from the height tolerance of chip submodule group described in described immediate every group
Mould group compensate it is described there are boss to be matched described in every group of the difference, it is described a number of to be equal to the difference.
Optionally, the step of height tolerance and quantity for obtaining chip submodule group includes:
Obtain the height parameter and quantity of the chip submodule group；
Minimum value is chosen from the height parameter of the chip submodule group；
The difference of the height parameter and the minimum value that calculate each chip submodule group obtains the chip submodule group
Height tolerance.
Optionally, the step of height tolerance for generating multiple boss to be matched at random includes:
Obtain the height parameter of multiple boss to be matched；
Maximum value is chosen from the height parameter of the multiple boss to be matched；
Calculate the difference of the height parameter of the maximum value and each boss to be matched；
According to the feature of the maximum value and the difference of the height parameter of each boss to be matched, it is random generate it is described to
Match the height tolerance of boss.
Optionally, the chip submodule group includes igbt chip submodule group and FRD chip submodule group.
The embodiment of the present invention provides a kind of packaging method of crimp type IGBT device, comprising:
The chip, molybdenum sheet and metal electrode of chip submodule group are carried out pre-packaged；
Height and electrical characteristic and the height of boss to be matched to the chip submodule group are tested, and will test
Reference record is in electrical form；
According to the matching process of the chip submodule group and boss, to the chip submodule group and the boss to be matched
It is matched to obtain matching result；
According to the matching result, the chip submodule group is encapsulated in corresponding boss to be matched.
Optionally, described and test parameter is recorded in the step in electrical form includes；
Obtain the position of the electric parameter, height parameter, the chip submodule group of the chip submodule group in chip tray
Set the number of coordinate and the chip tray；
By the height parameter of the chip submodule group, the electric parameter, the position coordinates and the chip support
The number of disk is associated the deposit electrical form；
Obtain the height parameter of the boss to be matched, and according to predetermined number by the height parameter of the boss to be matched
It is stored in the electrical form.
Optionally, the matching result includes the test parameter of the electrical form record and the height of boss to be matched
Spend parameter.
A kind of computer readable storage medium of the embodiment of the present invention, is stored thereon with computer instruction, and the instruction is processed
The step of matching process of chip submodule group and boss described in when device executes；Or the encapsulation side of the crimp type IGBT device
The step of method.
The embodiment of the present invention provides a kind of matching unit, including memory, processor and storage are on a memory and can be
The computer program run on processor, the processor realize the chip submodule group and boss when executing described program
The step of matching process.
The embodiment of the present invention provides a kind of sealed in unit, including memory, processor and storage are on a memory and can be
The computer program run on processor, the processor realize the envelope of the crimp type IGBT device when executing described program
The step of dress method.
Technical solution of the present invention has the advantages that
The present invention provides the packaging method of the matching process and crimp type IGBT device of a kind of chip submodule group and boss,
The wherein matching process of chip submodule group and boss then will grouping by the way that the height tolerance of chip submodule group to be grouped
Height tolerance of the height tolerance of chip submodule group afterwards respectively with the boss to be matched generated at random is overlapped, calculate to
Overall quantity with boss matches deviation, is then compared with the second preset threshold, and to the difference of boss to be matched into
Row compensation matches deviation less than the second preset threshold until overall quantity, and then realizes chip submodule group and boss to be matched one by one
Corresponding purpose.The Rapid matching of chip submodule group and boss to be matched to batch may be implemented in the present invention, that is, improves
With efficiency, and whole matching error can be made smaller, be conducive to the encapsulation of crimp type IGBT device by the matching way, into
And ensure that crimp type IGBT device has good electrical characteristic.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is the first pass figure of the chip submodule group of the embodiment of the present invention and the matching process of boss；
Fig. 2 is the second flow chart of the chip submodule group of the embodiment of the present invention and the matching process of boss；
Fig. 3 A is the bar chart of the height tolerance of the igbt chip submodule group of the embodiment of the present invention；
Fig. 3 B is the bar chart of the height tolerance of the FRD chip submodule group of the embodiment of the present invention；
Fig. 4 is the bar chart that the chip submodule group of the embodiment of the present invention is superimposed with the height tolerance of boss to be matched；
Fig. 5 is the third flow chart of the chip submodule group of the embodiment of the present invention and the matching process of boss；
Fig. 6 is the flow chart of the packaging method of crimp type IGBT device of the embodiment of the present invention；
Fig. 7 is the hardware schematic of matching unit of the embodiment of the present invention；
Fig. 8 is the hardware schematic of sealed in unit of the embodiment of the present invention.
Specific embodiment
Technical solution of the present invention is clearly and completely described below in conjunction with attached drawing, it is clear that described implementation
Example is a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill
Personnel's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that term " first ", " second ", " third " are used for description purposes only,
It is not understood to indicate or imply relative importance.
In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can
To be mechanical connection, it is also possible to be electrically connected；It can be directly connected, can also indirectly connected through an intermediary, it can be with
It is the connection inside two elements, can be wireless connection, be also possible to wired connection.For those of ordinary skill in the art
For, the concrete meaning of above-mentioned term in the present invention can be understood with concrete condition.
As long as in addition, the non-structure each other of technical characteristic involved in invention described below different embodiments
It can be combined with each other at conflict.
Embodiment 1
The embodiment of the invention provides the matching process of a kind of chip submodule group and boss, as shown in Figure 1, including following step
It is rapid:
S11, the height tolerance and quantity for obtaining chip submodule group.Chip submodule group herein includes igbt chip submodule group
With FRD chip submodule group, igbt chip submodule group is all respectively necessary for matching with boss and then could complete with FRD chip submodule group
The encapsulation of crimp type IGBT device.Igbt chip submodule group is matched with respective boss respectively with FRD chip submodule group, and two
The matching way of person is identical.The matching way of chip submodule group and boss can represent igbt chip submodule group and FRD chip submodule
The group matching with respective boss respectively.The general multiple chip submodule groups in parallel in the inside of crimp type IGBT device, due to appointing
All there is some difference for the height for two chip submodule groups of anticipating, so, the different chip submodule group of difference is assembled on boss,
Will lead to whole height also can there is some difference, this will affect the electrical characteristic of crimp type IGBT device, so, study chip
The matching way of submodule group and boss is critically important.
Specifically, as shown in Fig. 2, the height tolerance of acquisition chip submodule group and the step S11 of quantity include:
S111, the height parameter and quantity for obtaining chip submodule group.The height parameter of chip submodule group herein passes through number
Aobvious micrometer or spiral micrometer measure, and the measurement accuracy of the digimatic micrometer and spiral micrometer reaches 1 micron.
Such as: the height parameter of acquired chip submodule group is 4.204,4.198,4.195,4.199,4.196.Chip submodule group is made
For with the matched supplier of boss to be matched, it is therefore desirable to obtain the height parameter of many chip submodule groups.
S112, minimum value is chosen from the height parameter of chip submodule group.Such as: the chip submodule in above-mentioned steps S111
The height parameter of group is 4.204,4.198,4.195,4.199,4.196, is chosen from the height parameter of these chip submodule groups
Minimum value 4.195.Certainly, the quantity of chip submodule group is not limited to 5, can also be more quantity.
The height that the difference of S113, the height parameter for calculating each chip submodule group and minimum value obtain chip submodule group is inclined
Difference.The minimum value that chip submodule group is obtained from above-mentioned steps S112 is 4.195, calculates the height parameter of each chip submodule group
Height tolerance is obtained with the difference of the minimum value.1st height tolerance are as follows: 4.204-4.195=9, the 2nd height tolerance are as follows:
4.198-4.195=3, the 3rd height tolerance are as follows: 4.195-4.195=0, the 4th height tolerance are as follows: 4.199-4.195=4,
5th height tolerance are as follows: 4.196-4.195=1, so, obtain the height tolerance of 5 chip submodule groups.If there is more
Chip submodule group, similarly, the difference of the height parameter and minimum value that also calculate separately each chip submodule group obtains each chip
The height tolerance of mould group.
S12, according to the height tolerance and quantity of chip submodule group, the height tolerance of chip submodule group is grouped, phase
The difference of the height tolerance of adjacent two groups of chip submodule group is the first preset threshold.According to the height of the chip submodule group obtained
These height tolerances are grouped according to default spacing, and count the quantity of every group of height tolerance respectively by deviation and quantity, in advance
If spacing is that the difference of the height tolerance of the chip submodule group of two adjacent groups is the first preset threshold.Such as: as shown in Figure 3A, be
The bar shaped classified statistic figure of igbt chip submodule group, the abscissa of the bar shaped classified statistic figure are the height of igbt chip submodule group
Deviation, the ordinate of the bar shaped classified statistic figure are the quantity of igbt chip submodule group, on the horizontal scale it can be seen that height is inclined
Difference is arranged according to from as low as big sequence, and the spacing of adjacent two bar chart is identical, and each bar chart represents one group of IGBT
The height tolerance of chip submodule group, the height tolerance of every group of igbt chip submodule group respectively corresponds a quantity, therefore passes through this
Shape figure can count the quantity of the height tolerance of every group of igbt chip submodule group.The spacing of adjacent two bar chart represents phase
The difference of the height tolerance of adjacent two groups of igbt chip submodule groups is the first preset threshold, and usual first preset threshold is 1 micron,
So, it can be achieved that the fine grouping of the height tolerance of greater number of igbt chip submodule group.In figure 3 a, when igbt chip
When the height tolerance of mould group is 10, the quantity of corresponding igbt chip submodule group is 15.Such as: it is FRD core as shown in Figure 3B
The bar chart classified statistic figure of piece submodule group, the ordinate of the bar shaped classified statistic figure are the height tolerance of FRD chip submodule group,
The ordinate of the bar shaped classified statistic figure is the quantity of FRD chip submodule group, on the horizontal scale it can be seen that FRD chip submodule group
Height tolerance be also to be arranged according to from as low as big sequence, the spacing of adjacent two bar chart is identical, each bar chart generation
The height tolerance of one group of FRD chip submodule group of table, the height tolerance of every group of FRD chip submodule group respectively correspond a quantity, therefore
The quantity of the height tolerance of every group of FRD chip submodule group can be counted by the bar chart.Between adjacent two bar chart
Difference away from the height tolerance for representing two adjacent groups FRD chip submodule group is the first preset threshold among the above, usually this first
Preset threshold is also 1 micron, so, it can be achieved that the fine grouping of the height tolerance of greater number of RFD chip submodule group.Scheming
In 3B, when the height tolerance of FRD chip submodule group is 20, the quantity of corresponding FRD chip submodule group is 13.By to core
The height tolerance of piece submodule group is grouped with boss to be matched to match the chip submodule group of batch simultaneously, even if
Every group of chip submodule group is matched simultaneously with every group of boss to be matched respectively under sustained height deviation.
S13, the height tolerance for generating multiple boss to be matched at random, and the height tolerance of multiple boss to be matched is carried out
Grouping, the difference of the height tolerance of the boss to be matched of two adjacent groups are the first preset threshold.It generates at random multiple to be matched convex
The purpose of the height tolerance of platform in order to verify with the matched appropriate value of chip submodule group, thus in order to quickly make random life
At numerical value reach verifying purpose.Such as: as shown in figure 4, for the height tolerance of boss to be matched and the height of chip submodule group
The bar shaped bar chart of deviation superposition, the abscissa of the bar chart are height tolerance, and the ordinate of the bar shaped classified statistic figure is number
Amount, on the horizontal scale it can be seen that height tolerance is arranged according to from as low as big sequence, the spacing of adjacent two bar chart
Identical, each bar chart represents the height tolerance of one group of boss to be matched, and the height tolerance of every group of boss to be matched respectively corresponds
One quantity, therefore the quantity of the height tolerance of every group of boss to be matched can be counted by the bar chart.Adjacent two
The spacing of shape figure represents the difference of the height tolerance of two adjacent groups boss to be matched as the first preset threshold, and usually this is first default
Threshold value is also 1 micron, so, it can be achieved that the height tolerance of greater number of boss to be matched or the height tolerance of chip submodule group
Fine grouping.It can thus be seen that the packet mode of boss to be matched is identical as the packet mode of chip submodule group.
Specifically, as shown in figure 5, the step S13 of the height tolerance for generating multiple boss to be matched at random includes:
S131, the height parameter for obtaining multiple boss to be matched.The height parameter of boss to be matched herein is also by number
Aobvious micrometer or spiral micrometer measure, and the measurement accuracy of the digimatic micrometer or spiral micrometer reaches 1 micron.
Such as；The height parameter of acquired boss to be matched is 21.946,21.947,21.948,21.944.Boss conduct to be matched
With the matched party in request of chip submodule group.
S132, maximum value is chosen from the height parameter of multiple boss to be matched.Such as: in above-mentioned steps S132 to
Height parameter with boss are as follows: 21.946,21.947,21.948,21.944,21.950, from the height of these boss to be matched
Maximum value 21.948 is chosen in parameter.
S133, the difference for calculating maximum value with the height parameter of each boss to be matched.It is obtained from above-mentioned steps to be matched
The maximum value of boss is that the 21.948, the 1st height tolerance is；21.948-21.946=2 the 2nd height tolerance are as follows: 21.948-
21.947=1, the 3rd height tolerance are as follows: 21.948-21.948=0, the 4th height tolerance are 21.948-21.944=5, the
5 height tolerances are as follows: 21.948-21.950=3.If there is N number of boss to be matched, just to this N number of boss to be matched according to
Aforesaid way calculates N number of height tolerance.
S134, according to the feature of maximum value and the difference of the height parameter of each boss to be matched, generate at random to be matched convex
The height tolerance of platform.Difference feature herein is the distribution feelings according to the numerical value of the height tolerance of above-mentioned calculating boss to be matched
Then condition generates multiple numbers for calibrating chip submodule group and the matching result of boss to be matched according to the distribution situation at random
Value, can quickly obtain suitable check results.
By the height tolerance of Fig. 3 A or Fig. 3 B observable chip submodule group, pass through the height of Fig. 4 observable boss to be matched
It spends deviation and is superimposed situation with the height tolerance of chip submodule group.The calculation of the height tolerance of chip submodule group with it is to be matched convex
The calculation of platform is different, makees difference from minimum value using the actual height parameter of chip submodule group and obtains different chip submodule groups
Height tolerance, using boss to be matched actual height parameter maximum value and boss to be matched actual height parameter make it is poor
Obtain the height tolerance of different boss to be matched, then by the height tolerance of different chip submodule groups from it is different to be matched
The height tolerance of boss is matched, in order to enable higher chip submodule group matches lower boss to be matched, it is lower
Chip submodule group matches higher boss to be matched, to guarantee that whole matching error is smaller.
S14, count respectively every group of chip submodule group height tolerance corresponding number and every group of boss to be matched height
The corresponding number of deviation.The height tolerance corresponding number to every group of igbt chip submodule group can be realized respectively according to Fig. 3 A and 3B
Statistics and every group of FRD chip submodule group height tolerance corresponding number statistics, may be implemented according to Fig. 4 to be matched to every group
The statistics of the height tolerance corresponding number of boss.
S15, when the height tolerance of every group of boss to be matched is equal with the height tolerance of every group of chip submodule group, judgement is every
The difference of the corresponding number and the corresponding number of the height tolerance of every group of chip submodule group of the height tolerance of group boss to be matched is
It is no to be greater than zero.
Specifically, since the height tolerance of chip submodule group is identical as the packet mode of the height tolerance of boss to be matched,
Therefore can be overlapped any chip submodule group in Fig. 3 A or 3B with Fig. 4, so-called superposition is i.e. high by chip submodule group
The grouping situation of the grouping situation and boss to be matched of spending deviation, which is placed in a bar chart, to be shown, i.e. Fig. 4, in same height
Corresponding one group of chip submodule group and one group of boss to be matched under deviation are spent, in Fig. 4, when the height of every group of boss to be matched is inclined
When poor equal with the height tolerance of every group of chip submodule group, the height tolerance of every group of boss to be matched under the same coordinate of observable
With the difference of the height tolerance of every group of chip submodule group.By Fig. 4, the correspondence of the height tolerance of every group of boss to be matched can determine whether
Whether the difference of the corresponding number of the height tolerance of quantity and every group of chip submodule group is greater than zero, inclined in sustained height in Fig. 4
Under difference, when the corresponding number of the height tolerance of every group of boss to be matched is less than the correspondence number of the height tolerance of every group of chip submodule group
Amount needs to carry out difference compensation to boss to be matched, and compensating quantity is the stripe portion that abscissa is close in Fig. 4.
S16, when difference be greater than zero, according to difference computing chip submodule group and the overall quantity of boss to be matched matching deviation
Value, and judge that overall quantity matching deviation is greater than the second preset threshold.Difference is greater than zero, it is meant that every group of boss to be matched
Than every group chip submodule group of quantity quantity it is more, it is clear that the boss to be matched as party in request cannot match requirement, this
When, to the chip submodule group and boss to be matched progress global analysis after grouping, realize that overall quantity matching deviation minimum reaches
It is required to matching.
Specifically, computing chip submodule group matches deviation with the overall quantity of boss to be matched, in Fig. 4, same
One group of chip submodule group and one group of boss to be matched are respectively corresponded under coordinate, i.e. the height tolerance of the chip submodule group of the group at this time
It is identical as the height tolerance of group boss to be matched, still, the corresponding ordinate of the two not phase under same coordinate
Together, i.e., corresponding chip submodule group is not identical as the quantity of boss to be matched under sustained height deviation, due to be matched convex
Platform is as party in request, and chip submodule group is as supplier, under sustained height deviation, when the quantity of every group of boss to be matched is small
When the quantity of every group of chip submodule group, it is not able to satisfy matching demand, therefore needs to calculate the difference for the demand that is unsatisfactory for.In Fig. 4,
Statistics is under sustained height deviation, the height of the corresponding number of the height tolerance of every group of boss to be matched and every group of chip submodule group
The difference of the corresponding number of deviation and, by the difference and volume deviation value as a whole.
When difference is not more than zero, difference is reset.At this point, indicating that the quantity of the boss to be matched when every group is greater than or waits
When the quantity of every group of chip submodule group, the quantity of supplier is greater than party in request, meets matching demand, therefore difference is reset.
S17, when overall quantity matching deviation be greater than the second preset threshold when, to there are every group of boss to be matched of difference
Height tolerance corresponding number carry out difference compensation.Second preset threshold as batch matching chip submodule group with it is to be matched convex
The reference value of platform, the matching result of final purpose chip submodule group and boss to be matched in order to obtain.
Above-mentioned steps S17 is to there are the steps that the quantity of the height tolerance of every group of boss to be matched of difference carries out difference compensation
Suddenly include:
Firstly, search with there are the immediate every group of chip submodule groups of the height tolerance of every group of boss to be matched of difference
Height tolerance.Such as: in Fig. 4, when height tolerance is 20, the quantity of boss to be matched is 15, the quantity of chip submodule group
(in Fig. 4, when height tolerance is 10, the quantity of chip submodule group is less than the quantity of boss to be matched, therefore chip submodule for 10
Group is covered in Fig. 4 by boss to be matched), at this time the quantity of boss to be matched than chip submodule group quantity more than 5, therefore,
It needs the quantity for the boss to be matched for being 20 to height tolerance to carry out difference compensation, compensates the chip submodule group of 5 height tolerances
To the boss to be matched under this group of height tolerance.
A number of chip submodule group compensation is distributed from the height tolerance of immediate every group of chip submodule group to exist
Every group of boss to be matched of difference, it is a number of to be equal to difference.And matched mode is by waiting for there are every group of difference
Several chip submodule groups are distributed in height tolerance with the immediate every group of chip submodule group of boss, can guarantee that matching is inclined in this way
It is poor minimum, so that every group of lower boss to be matched matches every group of higher chip submodule group.
S18, circulation step S13- step S17, until overall quantity matching deviation makes core less than the second preset threshold
Until piece submodule group is matched with boss to be matched.When there are quantity Matching differences for every group of boss to be matched, which is mended
Circulation verifies whether that meeting matching requires after repaying, so that the whole matching of the chip submodule group of batch and boss to be matched
Error is minimum.Matching be built upon by the chip submodule group of batch and boss to be matched grouping after on the basis of because grouping
Purpose is then to match deviation using overall quantity to guarantee that higher boss to be matched is matched with lower chip submodule group
Value realizes the final the smallest purpose of whole matching deviation by compensation compared with the second preset threshold.
The matching process of chip submodule group and boss in the embodiment of the present invention, first passes through the height to chip submodule group in advance
Deviation is grouped, and carries out whole matching with the boss to be matched generated at random, the chip so that after being grouped is compensated by difference
Submodule group and the overall quantity of boss to be matched matching deviation are minimum, and then guarantee the entirety of chip submodule group and boss to be matched
Height tolerance is minimum, realizes the purpose of Rapid matching bulk quantity of chips submodule group and boss to be matched, also, pass through height tolerance point
Group carries out matching chip submodule group and boss to be matched, and matching precision can be improved.
Embodiment 2
The embodiment of the present invention provides a kind of packaging method of crimp type IGBT device, as shown in Figure 6, comprising:
S61, the chip, molybdenum sheet and metal electrode of chip submodule group are carried out it is pre-packaged.Herein pre-packaged refers to core
Two metal electrodes up and down of piece are sintered with molybdenum sheet respectively, to sintered subelement, in addition to upper and lower two contact surfaces,
Remaining every other face carries out plastic packaging using high insulating materials resistant to high temperature, completes the pre-packaged of chip submodule group.Chip and molybdenum sheet
Two-sided sintering is carried out, the thermal contact resistance and contact resistance at interface on the one hand can be substantially reduced, improves radiating efficiency, reduces function
Consumption；On the other hand the mechanical performances such as chip bending strength can be improved, prevents chipping under chip pressured state.Chip sides
Plastic packaging is carried out using high insulating materials resistant to high temperature, insulation performance on the one hand can be improved, prevent submodule group from high voltage arc occurs
Breakdown, on the other hand chip and external environment can be completely cut off, prevent the impurity such as steam and ion from entering internal contamination core
Piece improves the reliability of device.
S62, the height and electrical characteristic and the height of boss to be matched of chip submodule group are tested, and will test
Reference record is in electrical form.The height of chip submodule group and the height of boss to be matched are surveyed by digimatic micrometer or spiral
Micro- instrument measures, and the measurement accuracy of the digimatic micrometer and spiral micrometer reaches 1 micron.And the electricity of chip submodule group
Gas characteristic is usually collection the emitter-base bandgap grading leakage current Ice or leakage current Ir of chip submodule group, measures the chip by transistor graphic instrument
Collection the emitter-base bandgap grading leakage current Ice or leakage current Ir of submodule group, and the measurement accuracy of the transistor graphic instrument also reaches 1 micron.It will
Measure the test parameter record of the height of the height of chip submodule group, the electrical characteristic of chip submodule group and boss to be matched
In electrical form, on the one hand it is convenient for data statistics, is on the other hand convenient for the matching of chip submodule group and boss to be matched.Specifically
Ground, above-mentioned steps S72 include:
It is sat firstly, obtaining the position of the electric parameter of chip submodule group, height parameter, chip submodule group in chip tray
It is marked with and the number of chip tray.The electric parameter of chip submodule group is the collection that chip submodule group is measured by transistor graphic instrument
Emitter-base bandgap grading leakage current Ice, leakage current Ir, the height parameter of chip submodule group are to be measured by digimatic micrometer or spiral micrometer
Parameter, chip submodule group position in chip tray are that the chip submodule group is located at the position in chip boss, and general measure is complete
One chip submodule group is sequentially placed into sequence in numbered chip tray, which has chip submodule group institute
Belong to the coordinate of position.
Then, the number of the height parameter of chip submodule group, electric parameter, position coordinates and chip tray is associated
It is stored in electrical form.Association herein is exactly by the height parameter of chip submodule group, electric parameter, position coordinates and chip picture
Number bound.Such as: in the following table 1 and table 2, which is 4 column, 10 row, certainly can also be 4 column multirows, the
1 pallet for being classified as chip submodule group is numbered, the 2nd is classified as the position that chip submodule group is located at pallet, and the 3rd is classified as chip submodule group
Highly, the 4th electric parameter for being classified as chip submodule group.The following table 1 represents the electrical form of igbt chip submodule group, and the following table 2 represents
The electrical form of FRD chip submodule group.
Table 1
Table 2
Finally, obtaining the height parameter of boss to be matched, and the height parameter of boss to be matched is deposited according to predetermined number
Enter electrical form.As shown in table 3 below,
| Number | Substructure height (μm) | Upper cover height (μm) | Boss is total high (μm) |
| 1 | 14.462 | 7.484 | 21.946 |
| 2 | 14.461 | 7.485 | 21.946 |
| 3 | 14.463 | 7.487 | 21.950 |
| 4 | 14.460 | 7.487 | 21.947 |
| 5 | 14.461 | 7.489 | 21.950 |
| 6 | 14.463 | 7.489 | 21.952 |
| 7 | 14.464 | 7.488 | 21.952 |
| 8 | 14.465 | 7.487 | 21.952 |
| 9 | 14.465 | 7.487 | 21.952 |
| 10 | 14.463 | 7.484 | 21.947 |
| 11 | 14.464 | 7.483 | 21.947 |
Table 3
The height parameter for the boss to be matched measured can also be stored in above-mentioned electrical form, but at this time without sub with chip
The test parameter of mould group is associated with, and is placed it on same electrical form of chip submodule group.
S63, according to the matching process of chip submodule group and boss, chip submodule group match with boss to be matched
To matching result.Embodiment 1 can be found in the matching process of chip submodule group and boss herein, according to the method in embodiment 1
The matching of chip submodule group Yu boss to be matched is rapidly completed.
S64, according to matching result, chip submodule group is encapsulated in corresponding boss to be matched.Utilize chip
The matching process of mould group and boss completes the chip submodule group of batch and the matching of boss to be matched, can be fast according to matching result
Chip submodule group is mounted on corresponding boss to be matched by speed.Matching result includes the test parameter of electrical form record
And the height parameter of boss to be matched, as shown in the following table 4 and table 5.
Table 4
Table 5
The following table 6 is the corresponding relationship of chip submodule the group position on pallet and boss to be matched.
Table 6
Embodiment 3
The embodiment of the present invention provides a kind of computer readable storage medium, is stored thereon with computer instruction, the instruction quilt
The step of method of the matching process of chip submodule group and boss in embodiment 1 is realized when processor executes or embodiment 2 crimp
The step of packaging method of type IGBT device.Also be stored on the storage medium height tolerance of chip submodule group, quantity, to
Height parameter, the height parameter of boss to be matched etc. of height tolerance, quantity, chip submodule group with boss.
Wherein, storage medium can be magnetic disk, CD, read-only memory (Read-Only Memory, ROM), random
Storage memory (Random Access Memory, RAM), flash memory (Flash Memory), hard disk (Hard Disk
Drive, abbreviation: HDD) or solid state hard disk (Solid-State Drive, SSD) etc.；The storage medium can also include above-mentioned
The combination of the memory of type.
It is that can lead to it will be understood by those skilled in the art that realizing all or part of the process in above-described embodiment method
Computer program is crossed to instruct relevant hardware and complete, program can be stored in a computer-readable storage medium, the journey
Sequence is when being executed, it may include such as the process of the embodiment of above-mentioned each method.Wherein, storage medium can for magnetic disk, CD, read-only deposit
Store up memory body (ROM) or random access memory (RAM) etc..
Embodiment 4
The embodiment of the present invention provides a kind of matching unit, as shown in fig. 7, comprises memory 720, processor 710 and storage
On memory 720 and the computer program that can run on the processor 710, processor 710 realize embodiment 1 when executing program
The step of matching process of middle chip submodule group and boss.
Fig. 7 is that the hardware configuration of the matching unit of the processing method of execution list items operation provided in an embodiment of the present invention shows
It is intended to, as shown in fig. 7, the matching unit includes one or more processors 710 and memory 720, is handled in Fig. 7 with one
For device 710.
The equipment for executing the processing method of list items operation can also include: acquisition device 730.
Processor 710, memory 720, acquisition device 730 can be connected by bus or other modes, with logical in Fig. 7
It crosses for bus connection.
Processor 710 can be central processing unit (Central Processing Unit, CPU).Processor 710 may be used also
Think other general processors, digital signal processor (Digital Signal Processor, DSP), specific integrated circuit
(Application Specific Integrated Circuit, ASIC), field programmable gate array (Field-
Programmable Gate Array, FPGA) either other programmable logic device, discrete gate or transistor logic,
The combination of the chips such as discrete hardware components or above-mentioned all kinds of chips.General processor can be microprocessor or the processing
Device is also possible to any conventional processor etc..
Embodiment 5
The embodiment of the present invention provides a kind of sealed in unit, as shown in figure 8, including memory 820, processor 810 and storage
On memory 820 and the computer program that can run on processor 810, processor 810 realize embodiment 2 when executing program
The step of packaging method of middle crimp type IGBT device.
Fig. 8 is a kind of hardware knot of sealed in unit of the processing method of execution list items operation provided in an embodiment of the present invention
Structure schematic diagram, as shown in figure 8, the sealed in unit includes one or more processors 810 and memory 820, with one in Fig. 8
For processor 810.
The equipment for executing the processing method of list items operation can also include: acquisition device 830.
Processor 810, memory 820, acquisition device 830 can be connected by bus or other modes, with logical in Fig. 8
It crosses for bus connection.
Processor 810 can be central processing unit (Central Processing Unit, CPU).Processor 810 may be used also
Think other general processors, digital signal processor (Digital Signal Processor, DSP), specific integrated circuit
(Application Specific Integrated Circuit, ASIC), field programmable gate array (Field-
Programmable Gate Array, FPGA) either other programmable logic device, discrete gate or transistor logic,
The combination of the chips such as discrete hardware components or above-mentioned all kinds of chips.General processor can be microprocessor or the processing
Device is also possible to any conventional processor etc..
Obviously, the above embodiments are merely examples for clarifying the description, and does not limit the embodiments.It is right
For those of ordinary skill in the art, can also make on the basis of the above description it is other it is various forms of variation or
It changes.There is no necessity and possibility to exhaust all the enbodiments.And it is extended from this it is obvious variation or
It changes still within the protection scope of the invention.
Claims (12)
1. a kind of matching process of chip submodule group and boss, which comprises the steps of:
S11, the height tolerance and quantity for obtaining chip submodule group；
S12, according to the height tolerance and quantity of the chip submodule group, the height tolerance of the chip submodule group is divided
Group, the difference of the height tolerance of the chip submodule group of two adjacent groups are the first preset threshold；
S13, the height tolerance for generating multiple boss to be matched at random, and the height tolerance of the multiple boss to be matched is carried out
Grouping, the difference of the height tolerance of the boss to be matched of two adjacent groups are first preset threshold；
S14, count every group respectively described in chip submodule group height tolerance corresponding number and every group described in boss to be matched
The corresponding number of height tolerance；
S15, the boss to be matched described in every group height tolerance it is equal with the height tolerance of chip submodule group described in every group when, sentence
Break boss to be matched described in every group height tolerance corresponding number it is corresponding with the height tolerance of chip submodule group described in every group
Whether the difference of quantity is greater than zero；
S16, when the difference be greater than zero, the entirety of the chip submodule group Yu the boss to be matched is calculated according to the difference
Quantity Matching deviation, and judge whether the overall quantity matching deviation is greater than the second preset threshold；
S17, when overall quantity matching deviation is greater than second preset threshold, to there are the described every of the difference
The corresponding number of the height tolerance of the group boss to be matched carries out difference compensation；
S18, the circulation step S13- step S17, until overall quantity matching deviation is less than the described second default threshold
Until being worth so that the chip submodule group is matched with the boss to be matched.
2. the matching process of chip submodule group and boss according to claim 1, which is characterized in that further include: when described
When difference is not more than zero, the difference is reset.
3. the matching process of chip submodule group and boss according to claim 1, which is characterized in that there are the differences
Every group described in the quantity of height tolerance of boss to be matched the step of carrying out difference compensation include:
It searches and described there are chips described in immediate every group of the height tolerance of boss to be matched described in every group of the difference
The height tolerance of submodule group；
The a number of chip submodule group is distributed from the height tolerance of chip submodule group described in described immediate every group
Compensate it is described there are boss to be matched described in every group of the difference, it is described a number of to be equal to the difference.
4. the matching process of chip submodule group and boss according to claim 1, which is characterized in that acquisition chip
The step of height tolerance and quantity of mould group includes:
Obtain the height parameter and quantity of the chip submodule group；
Minimum value is chosen from the height parameter of the chip submodule group；
The difference of the height parameter and the minimum value that calculate each chip submodule group obtains the height of the chip submodule group
Deviation.
5. the matching process of chip submodule group and boss according to claim 1, which is characterized in that the random generation is more
The step of height tolerance of a boss to be matched includes:
Obtain the height parameter of multiple boss to be matched；
Maximum value is chosen from the height parameter of the multiple boss to be matched；
Calculate the difference of the height parameter of the maximum value and each boss to be matched；
According to the feature of the maximum value and the difference of the height parameter of each boss to be matched, generate at random described to be matched
The height tolerance of boss.
6. the matching process of chip submodule group and boss according to claim 1-5, which is characterized in that the core
Piece submodule group includes igbt chip submodule group and FRD chip submodule group.
7. a kind of packaging method of crimp type IGBT device characterized by comprising
The chip, molybdenum sheet and metal electrode of chip submodule group are carried out pre-packaged；
Height and electrical characteristic and the height of boss to be matched to the chip submodule group are tested, and by test parameter
It is recorded in electrical form；
According to the matching process of chip submodule group and boss described in any one of claims 1-6, to the chip submodule group with
The boss to be matched is matched to obtain matching result；
According to the matching result, the chip submodule group is encapsulated in corresponding boss to be matched.
8. the packaging method of crimp type IGBT device according to claim 7, which is characterized in that described and by test parameter
The step being recorded in electrical form includes；
The position of the electric parameter, height parameter, the chip submodule group of the chip submodule group in chip tray is obtained to sit
It is marked with and the number of the chip tray；
By the height parameter of the chip submodule group, the electric parameter, the position coordinates and the chip tray
Number is associated the deposit electrical form；
The height parameter of the boss to be matched is obtained, and is stored in the height parameter of the boss to be matched according to predetermined number
The electrical form.
9. the packaging method of crimp type IGBT device according to claim 7, which is characterized in that the matching result includes
The test parameter of the electrical form record and the height parameter of the boss to be matched.
10. a kind of computer readable storage medium, is stored thereon with computer instruction, which is characterized in that the instruction is by processor
The step of matching process of chip submodule group described in any one of claims 1-6 and boss is realized when execution；Or claim
The step of packaging method of the described in any item crimp type IGBT devices of 7-10.
11. a kind of matching unit including memory, processor and stores the calculating that can be run on a memory and on a processor
Machine program, which is characterized in that the processor realizes chip submodule described in any one of claims 1-6 when executing described program
The step of group and the matching process of boss.
12. a kind of sealed in unit including memory, processor and stores the calculating that can be run on a memory and on a processor
Machine program, which is characterized in that the processor realizes the described in any item crimp types of claim 7-10 when executing described program
The step of packaging method of IGBT device.
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| KR20110117389A (en) * | 2010-04-21 | 2011-10-27 | 허혁재 | Chip leveling apparatus |
| CN105514095A (en) * | 2015-12-18 | 2016-04-20 | 华北电力大学 | Crimped IGBT module with variable boss height |
| CN108172519A (en) * | 2017-11-17 | 2018-06-15 | 全球能源互联网研究院有限公司 | Rigid electrode crimping encapsulation power semiconductor device package method and system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20110117389A (en) * | 2010-04-21 | 2011-10-27 | 허혁재 | Chip leveling apparatus |
| CN105514095A (en) * | 2015-12-18 | 2016-04-20 | 华北电力大学 | Crimped IGBT module with variable boss height |
| CN108172519A (en) * | 2017-11-17 | 2018-06-15 | 全球能源互联网研究院有限公司 | Rigid electrode crimping encapsulation power semiconductor device package method and system |
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| CN114378816A (en) * | 2021-12-27 | 2022-04-22 | 歌尔股份有限公司 | Equipment motion track deviation rectifying method, control device and storage medium |
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