CN109256079B - Gate driver circuit and gate driver - Google Patents
Gate driver circuit and gate driver Download PDFInfo
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- CN109256079B CN109256079B CN201811354842.1A CN201811354842A CN109256079B CN 109256079 B CN109256079 B CN 109256079B CN 201811354842 A CN201811354842 A CN 201811354842A CN 109256079 B CN109256079 B CN 109256079B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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Abstract
The invention provides a gate driving circuit and a gate driver, the gate driving circuit includes: the device comprises a first signal source, a signal control module, a processing module and an adjusting module; the processing module is respectively connected with the first signal source, the signal control module and the adjusting module, and the adjusting module is also connected with the first signal source; the first signal source is used for outputting voltage signals to the processing module and the adjusting module; the signal control module is used for outputting control signals to the processing module and the adjusting module; and the processing module and the adjusting module are used for controlling the voltage of the PU signal point of the grid driving circuit to be maintained as a preset voltage according to the control signal and the voltage signal, and the PU signal point of the grid driving circuit is a common connection point of the signal source and the processing module as well as the adjusting module. The gate driving circuit provided by the invention can maintain the voltage of the PU signal point in the gate driving circuit to be the preset voltage, and solves the problem that the voltage of the PU point is leaked when a transistor in the gate driving circuit is turned on.
Description
Technical Field
The present invention relates to the field of liquid crystal display technologies, and in particular, to a gate driving circuit and a gate driver.
Background
Gate Driver On Array, referred to as GOA for short, is a technology of implementing a driving mode of scanning Gate signal lines (Gate lines) line by a Gate driving circuit integrated On a thin film transistor Array TFT. The GOA technology has the advantages of saving gate ICs, realizing narrow borders, and the like, and is widely applied to panel design at present. As the size of the display panel is increased, the load resistance and capacitance of the gate scan line are large, the delay of the gate signal becomes serious, and the driving capability of the GOA circuit is important.
A GOA circuit in the prior art generally includes a plurality of GOA units connected in cascade, each GOA unit can drive a corresponding one-stage horizontal scan line, that is, each GOA unit is responsible for turning on and off a row of thin film transistors. At present, a metal oxide TFT in a thin film transistor array is a depletion enhancement type semiconductor device; specifically, fig. 1 is a graph of the threshold voltage Vth of the TFT varying with the negative bias voltage Vgs, and as shown in fig. 1, when Vgs is 0V, the TFT has a leakage current.
In the prior art, even if the initial threshold voltage Vth of the prepared metal oxide TFT device is greater than 0V by optimizing the TFT preparation process, the Vth of the TFT is likely to shift after the TFT operates for a long time, and particularly for an Indium Gallium Zinc Oxide (IGZO) TFT, when the Vth is less than 0V, because the electrical subthreshold swing (S factor) value of the TFT is generally small, when the Vgs of the TFT is 0, the leakage of the TFT is very serious, which causes the PU point voltage in the GOA unit and the output voltage of the scanning line corresponding to the GOA unit to leak when the PD point potential in the GOA unit is low potential, further causes the GOA unit to have slow output voltage speed and low voltage, and even causes the GOA unit to fail.
Disclosure of Invention
The invention provides a gate driving circuit and a gate driver, which can maintain the voltage of a PU signal point in the gate driving circuit to be a preset voltage, and solve the problems that a transistor in the gate driving circuit is turned on and the voltage of the PU point is leaked.
A first aspect of the present invention provides a gate driving circuit, including: the device comprises a first signal source, a signal control module, a processing module and an adjusting module;
the processing module is respectively connected with the first signal source, the signal control module and the adjusting module, and the adjusting module is also connected with the first signal source;
the first signal source is used for outputting voltage signals to the processing module and the adjusting module;
the signal control module is used for outputting control signals to the processing module and the adjusting module;
the processing module and the adjusting module are used for controlling the voltage of a PU signal point of the gate driving circuit to be maintained as a preset voltage according to the control signal and the voltage signal, and the PU signal point of the gate driving circuit is a common connection point of the signal source and the processing module and the adjusting module.
Optionally, the processing module includes: a pull-down sustain circuit, the gate driver further comprising: a first low voltage module and a second low voltage module;
the pull-down maintaining circuit is respectively connected with the first signal source, the first low-voltage module, the second low-voltage module and the signal control module, and the adjusting module is connected with the second low-voltage module;
the first low voltage module is used for outputting a first voltage;
the second low-voltage module is used for outputting a second voltage;
the pull-down maintaining circuit and the adjusting module are used for controlling the voltage of the PU signal point to be maintained as a preset voltage under the action of the voltage signal, the control signal, the first voltage and the second voltage.
Optionally, the signal control module includes: the pull-down maintaining circuit comprises a first clock signal generator, a second clock signal generator, and further comprises: a first thin film transistor and a second thin film transistor;
the grid electrode and the drain electrode of the first thin film transistor are connected and connected with the first clock signal generator, the source electrode of the first thin film transistor is connected with a PD signal point in the grid electrode driving circuit, the grid electrode of the second thin film transistor is connected with the second clock signal generator, the drain electrode of the second thin film transistor is connected with the PD signal point, and the source electrode of the second thin film transistor is connected with the second low-voltage module;
the control signal is a high potential signal, and the first thin film transistor is used for transmitting the high potential signal of the first clock signal generator; the second thin film transistor is used for transmitting a high potential signal of the second clock signal generator;
when PU signal point is first default voltage, second thin film transistor is used for right PU signal point charges, and is in first voltage with under the effect of second voltage, make the voltage of PU signal point be first default voltage.
Optionally, the pull-down maintaining circuit includes: a third thin film transistor, a fourth thin film transistor, and a fifth thin film transistor;
the grid electrode of the third thin film transistor is connected with the PU signal point, the drain electrode of the third thin film transistor is connected with the PD signal point, and the source electrode of the third thin film transistor is connected with the second low-voltage module; the grid electrode of the fourth thin film transistor is connected with a PD signal point of the grid electrode driving circuit, the drain electrode of the fourth thin film transistor is connected with the PU signal point, and the source electrode of the fourth thin film transistor is connected with the second low-voltage module; the grid electrode of the fifth thin film transistor is connected with the PD signal point, the drain electrode of the fifth thin film transistor is connected with the scanning line of the grid driving circuit, and the source electrode of the fifth thin film transistor is connected with the first low-voltage module;
and the third thin film transistor is used for charging the PD signal point when the PU signal point is at a second preset voltage, so that the voltage of the PD signal point is equal to that of the second low-voltage module, the fourth thin film transistor and the fifth thin film transistor are turned off under the action of the first voltage and the second voltage, and the voltage of the PU signal point is controlled to be at the second preset voltage.
Optionally, the adjusting module includes: a sixth thin film transistor;
the grid electrode of the sixth thin film transistor is connected with the first signal source, the drain electrode of the sixth thin film transistor is connected with a PD signal point of the grid electrode driving circuit, and the source electrode of the sixth thin film transistor is connected with the second low-voltage module;
when the voltage of the PU signal point is at an initial increasing stage, the sixth thin film transistor is specifically configured to charge the PD signal point, so that the voltage of the PD signal point is equal to the voltage of the second low-voltage module, and the fourth thin film transistor and the fifth thin film transistor are turned off under the action of the first voltage and the second voltage, and the voltage of the PU signal point is controlled to be the second preset voltage.
Optionally, the pull-down maintaining circuit further includes: a seventh thin film transistor, an eighth thin film transistor, and a ninth thin film transistor;
the grid electrode of the seventh thin film transistor is connected with a reset signal point of the grid electrode driving circuit, the drain electrode of the seventh thin film transistor is connected with the PD signal point, and the source electrode of the seventh thin film transistor is connected with the second low-voltage module;
the grid electrode of the eighth thin film transistor is connected with the reset signal point, the drain electrode of the eighth thin film transistor is connected with the PU signal point, and the source electrode of the eighth thin film transistor is connected with the first low-voltage module;
the grid electrode of the ninth thin film transistor is connected with the reset signal point, the drain electrode of the ninth thin film transistor is connected with the scanning line of the grid electrode driving circuit, and the source electrode of the ninth thin film transistor is connected with the first low-voltage module.
Optionally, the signal control module further includes: third clock signal generator, fourth clock signal generator, gate drive circuit still includes: a second signal source, a tenth thin film transistor, an eleventh thin film transistor, a twelfth thin film transistor, and a thirteenth thin film transistor;
the grid electrode and the drain electrode of the tenth thin film transistor are both connected with the first signal source, and the source electrode of the tenth thin film transistor is respectively connected with a PU signal point of the grid drive circuit;
the grid electrode of the eleventh thin film transistor is respectively connected with the PU signal point, the drain electrode of the eleventh thin film transistor is connected with the third clock signal generator, and the source electrode of the eleventh thin film transistor is connected with the scanning line of the grid electrode driving circuit;
the grid electrode of the twelfth thin film transistor is connected with the second signal source, the drain electrode of the twelfth thin film transistor is connected with the PU signal point, and the source electrode of the twelfth thin film transistor is connected with the first low-voltage module;
the gate of the thirteenth thin film transistor is connected to the fourth clock signal generator, the drain of the fourth thin film transistor is connected to the scan line of the gate driving circuit, and the source of the fourth thin film transistor is connected to the first low voltage module.
Optionally, the gate driving circuit further includes: a bootstrap capacitor;
the first end of the bootstrap capacitor is connected with the PU signal point, and the second end of the bootstrap capacitor is connected with the scanning line of the gate drive circuit.
Optionally, the first voltage is greater than the second voltage.
A second aspect of the present invention provides a gate driver, comprising: the gate driving circuit comprises a plurality of stages.
The invention provides a gate driving circuit and a gate driver, the gate driving circuit includes: the device comprises a signal control module, a processing module and an adjusting module; the signal control module is electrically connected with the processing module, and the processing module is electrically connected with the adjusting module; the signal control module is used for outputting control signals to the processing module and the adjusting module; and the processing module and the adjusting module are used for controlling the voltage of the PU signal point of the grid electrode driving circuit to be maintained as a preset voltage according to the control signal. The gate driving circuit provided by the invention can maintain the voltage of the PU signal point in the gate driving circuit to be the preset voltage, and solves the problem that the voltage of the PU point is leaked when a transistor in the gate driving circuit is turned on.
Drawings
Fig. 1 is a graph of threshold voltage Vth of a TFT as a function of negative bias voltage Vgs;
fig. 2 is a first connection diagram of the gate driving circuit according to the present invention;
fig. 3 is a second connection diagram of the gate driving circuit according to the present invention;
fig. 4 is a third connection diagram of the gate driving circuit according to the present invention;
fig. 5 is a pulse sequence diagram of the gate driving circuit provided by the present invention.
Description of reference numerals:
10-a gate drive circuit;
11-a first signal source;
12-a signal control module;
13-a processing module;
131-a pull-down sustain circuit;
14-an adjustment module;
15-a first low voltage module;
16-second low voltage module.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
And the Gate drive circuit is used for realizing the drive of the Gate progressive scanning. The GOA technology has the advantages of saving gate ICs, realizing narrow borders, and the like, and is widely applied to panel design at present. With the increasing size of the display panel, the load resistance and capacitance of the gate scan line are large, the delay of the gate signal becomes serious, and the idle driving capability of the GOA circuit is particularly important. Due to the defects of the design of the GOA circuit, the output driving signal is prone to significant attenuation under heavy load, and the rise and fall times are significantly increased. The output signal of the GOA is susceptible to gradual attenuation as the number of stages of the GOA circuit increases. Common defects of the GOA include split display of the panel, weak lines of gate driving lines visible under gray-scale pictures, etc., which are strongly related to the degradation of the GOA driving capability. Increasing the driving capability of the GOA circuit cannot be achieved simply by increasing the size of the TFT, on one hand because the size of the TFT is limited by the allowable frame size of the panel, and on the other hand, the increase in the size of the TFT also causes the increase in parasitic capacitance, so that the increase in the voltage feed-through effect will cause negative effects such as an increase in output ripple and an increase in power consumption. Therefore, how to improve the driving capability of the GOA circuit is a key issue to be solved in the GOA design applied to the television panel.
As shown in fig. 1, after a depletion enhancement type semiconductor device TFT operates for a long time, a threshold voltage Vth of the depletion enhancement type semiconductor device TFT is prone to shift, and when a Vth of the thin film transistor is smaller than 0V, since an electrical sub-threshold swing (S factor) value of the thin film transistor is generally smaller, leakage current of the thin film transistor is very serious, so that when a PD point potential in the GOA unit is a low potential, a PU point voltage in the GOA unit and an output voltage of a scan line corresponding to the GOA unit are leaked, and further, an output voltage speed of the GOA unit is slow, a voltage is low, and even the GOA unit fails.
In order to solve the above-mentioned problems of low output voltage speed and low voltage of the gate driving circuit caused by the PU signal point leakage and the PU signal point voltage change in the gate driving circuit, the present invention provides a gate driving circuit, fig. 2 is a connection schematic diagram of the gate driving circuit provided by the present invention, as shown in fig. 2, the gate driving circuit 10 provided by this embodiment includes: a first signal source 11, a signal control module 12, a processing module 13 and an adjusting module 14.
The processing module 13 is respectively connected with the first signal source 11, the signal control module 12 and the adjusting module 14, and the adjusting module 14 is further connected with the first signal source 11; the first signal source 11 is configured to output a voltage signal to the processing module 13 and the adjusting module 14; the common connection point of the first signal source, the processing module 13 and the adjusting module 14 is a PU signal point of the gate driving circuit 10. The signal control module 12 in this embodiment is configured to output a control signal to the processing module 13 and the adjusting module 14. The signal control module 12 in this embodiment may be a signal clock generator, and may output a high potential or a low potential, so that the processing module 13 and the adjusting module 14 connected thereto exhibit corresponding high potentials or low potentials.
In this embodiment, the processing module 13 may include a plurality of thin film transistors, and the processing module 13 may be connected to the PU signal point and the PD signal point of the gate driving circuit 10. And the processing module 13 and the adjusting module 14 are configured to maintain a voltage of the PU signal point of the gate driving circuit 10 at a preset voltage according to the control signal. Specifically, the PD signal point of the gate driving circuit 10 in this embodiment is a connection point of the processing module 13 and the scan line of the gate driving circuit 10.
Specifically, the processing module 13 is configured to control a voltage of a PU signal point of the gate driving circuit 10 to be maintained as a preset voltage according to the control signal voltage signal.
One possible implementation manner is as follows: the voltage signal output by the first signal source 11 is a high potential, that is, when the PU signal point is a high potential, the signal control module 12 can output the high potential, so that the thin film transistor connected to the signal control module 12 in the processing module 13 is turned on, the PD signal point of the gate driving circuit 10 is charged, and then the thin film transistor connected to the PU signal point is turned off, and then the PU signal point connected to the thin film transistor is maintained at the high potential, that is, the voltage of the PU signal point is maintained at the preset voltage.
Another possible implementation is: the voltage signal output by the first signal source 11 is at a low potential, that is, when the PU signal point is at a low potential, the signal control module 12 may output a high potential, discharge the PD signal point through the thin film transistor connected to the PD signal point of the gate driving circuit 10, and maintain the potential of the PU signal point at a low potential through the thin film transistor connected to the PU signal point, that is, maintain the voltage of the PU signal point at a preset voltage.
Specifically, the adjusting module 14 is configured to maintain a voltage of the PU signal point of the gate driving circuit 10 at a preset voltage according to the control signal.
In this embodiment, the adjusting module 14 may be a thin film transistor, and when the gate driving circuit 10 is in the initial pull-up stage, the thin film transistor may be connected to the PD signal point of the gate driving circuit 10, discharge the PD signal point, and maintain the potential of the PU signal point at the low potential through the thin film transistor connected to the PU signal point in the processing module 13.
It should be noted that, in this embodiment, the potential range may be divided in advance, and the definition of the high potential and the low potential may be the same as that of the potential in the prior art, or the potential range may be divided according to different types of thin film transistors, which is not limited herein.
The gate driving circuit 10 provided in the present embodiment includes: the device comprises a first signal source 11, a signal control module 12, a processing module 13 and an adjusting module 14; the processing module 13 is respectively connected with the first signal source 11, the signal control module 12 and the adjusting module 14, and the adjusting module 14 is also connected with the first signal source 11; the first signal source 11 is configured to output a voltage signal to the processing module 13 and the adjusting module 14; the signal control module 12 is used for outputting control signals to the processing module 13 and the adjusting module 14; the processing module 13 and the adjusting module 14 are configured to maintain a voltage of a PU signal point of the gate driving circuit 10 at a preset voltage according to the control signal and the voltage signal, where the PU signal point of the gate driving circuit 10 is a common connection point of the first signal source 11 and the processing module 13 and the adjusting module 14. The gate driving circuit 10 provided by the invention can maintain the voltage of the PU signal point in the gate driving circuit at a preset voltage in each stage, and solves the problem that the voltage of the PU point is leaked when a transistor in the gate driving circuit 10 is turned on.
On the basis of the foregoing embodiment, the following further describes the gate driving circuit 10 provided by the present invention with reference to fig. 3, where fig. 3 is a connection schematic diagram of the gate driving circuit provided by the present invention, and as shown in fig. 3, the gate driving circuit 10 provided by this embodiment further includes: a first low voltage module 15 and a second low voltage module 16, in particular, the processing module 13 comprises: the pull-down holding circuit 131.
The pull-down maintaining circuit 131 is connected to the first low voltage module 15, the second low voltage module 16, and the signal control module, and the adjusting module 14 is connected to the second low voltage module 16.
The first low voltage module 15 in this embodiment is configured to output a first voltage VSS 1; a second low voltage module 16 for outputting a second voltage VSS 2; the first voltage VSS1 and the second voltage VSS2 may be preset voltage values.
Specifically, the pull-down maintaining circuit 131 and the adjusting module 14 are configured to control the voltage of the PU signal point to be maintained at the predetermined voltage under the action of the voltage signal, the control signal, the first voltage VSS1 and the second voltage VSS 2.
One possible implementation manner is as follows: when the PU signal point is at a high potential, the signal control module 12 may output the high potential, so that the thin film transistor connected to the signal control module 12 in the processing module 13 is turned on, and the PD signal point of the gate driving circuit 10 is charged to the second voltage VSS 2. The tft connected to the PU signal point in this embodiment may also be connected to the first voltage VSS1 module and the PD signal point, so that the negative bias voltage of the tft is the voltage difference between the second voltage VSS2 and the first voltage VSS 1; in this embodiment, the first voltage VSS1 may be set to be greater than the second voltage VSS2, specifically, the first voltage VSS1 and the second voltage VSS2 satisfy 15V > VSS1-VSS2> 2V; further, the first voltage VSS1 and the second voltage VSS2 satisfy 7V > VSS1-VSS2> 3V; illustratively, the first voltage VSS1 is-6V and the second voltage VSS2 is-9V. And further, the negative bias voltage of the thin film transistor is less than 0V, so that the thin film transistor is completely turned off, and a PU signal point connected with the thin film transistor is maintained at a high potential, namely the voltage of the PU signal point is maintained at a preset voltage.
Another possible implementation is: when the PU signal point is at a low potential, the signal control module 12 may output a high potential, and discharge the PD signal point through the thin film transistor connected to the PD signal point of the gate driving circuit 10; in order to reduce the high voltage stress of the thin film transistor connected to the PD signal point for a long time, specifically, the signal control module 12 may periodically discharge the PD signal point, and the thin film transistor connected to the PU signal point maintains the potential of the PU signal point at a low voltage, that is, the voltage of the PU signal point is maintained at the predetermined voltage.
Specifically, the thin film transistor in the adjusting module 14 may be connected to the PD signal point of the gate driving circuit 10 and the second low voltage module 16, when the gate driving circuit 10 is in the initial pull-up stage, the thin film transistor in the adjusting module 14 discharges the PD signal point to pull down the potential of the PD signal point to the second voltage VSS2, and since the second voltage VSS2 is smaller than the first voltage VSS1, the negative threshold voltage of the thin film transistor connected to the PU signal point in the processing module 13 is the voltage difference between the second voltage VSS2 and the first voltage VSS1, and is smaller than 0V, so that the thin film transistor connected to the PU signal point in the processing module 13 is completely turned off, and the PU signal point connected thereto may be maintained at a high potential.
In this embodiment, the gate driving circuit 10 further includes: a first low voltage module 15 and a second low voltage module 16, in particular, the processing module 13 comprises: the pull-down holding circuit 131. The pull-down maintaining circuit 131 is connected to the first low voltage module 15, the second low voltage module 16, and the signal control module, respectively. The pull-down maintaining circuit 131 and the adjusting module 14 are used for controlling the voltage of the PU signal point to be maintained at a predetermined voltage under the action of the control signal, the first voltage VSS1 and the second voltage VSS 2. The gate driving circuit 10 provided in this embodiment maintains the voltage of the PU signal point to be the preset voltage through the combination of the dual low voltage module and the adjusting module 14, thereby further solving the problem that the voltage of the PU point is leaked when the transistor in the gate driving circuit 10 is turned on.
On the basis of the foregoing embodiment, the pull-down maintaining circuit 131 in the gate driving circuit 10 provided by the present invention is described in detail with reference to fig. 4, where fig. 4 is a connection schematic diagram of the gate driving circuit provided by the present invention, and as shown in fig. 4, the signal control module 12 in the gate driving circuit 10 provided by this embodiment includes: a first clock signal generator CK1, a second clock signal generator CK 2; specifically, the pull-down holding circuit 131 further includes: a first thin film transistor T1 and a second thin film transistor T2.
The gate and the drain of the first thin film transistor T1 are connected to each other and are connected to the first clock signal generator CK1, the source of the first thin film transistor T1 is connected to the PD signal point of the gate driving circuit 10, the gate of the second thin film transistor T2 is connected to the second clock signal generator CK2, the drain of the second thin film transistor T2 is connected to the PD signal point, and the source of the second thin film transistor T2 is connected to the second low voltage module 16.
The control signal in this embodiment is a high level signal, and the first clock signal generator CK1 and the second clock signal generator CK2 are used for outputting a high level signal; a first thin film transistor T1 for transmitting a high potential signal of the first clock signal generator CK 1; and a second thin film transistor T2 for transmitting a high potential signal of the second clock signal generator CK 2.
When the PU signal point is at the first predetermined voltage, the second thin film transistor T2 is used for charging the PU signal point, and the voltage of the PU signal point is maintained at the first predetermined voltage under the action of the first voltage VSS1 and the second voltage VSS 2. The first preset voltage may be a low voltage.
Specifically, the second thin film transistor T2 is used for discharging the PD signal point when the PU signal point is at a low voltage level, so that the voltage of the PD signal point is equal to the second voltage VSS2 of the second low voltage module 16. Specifically, when PU is at a low potential, the first clock signal generator CK1 discharges the PD signal point periodically through the first thin film transistor T1, so that the PD signal point is at a high potential. When the second clock signal generator CK2 is at a high level, the PU signal point is charged to the second voltage VSS2 through the second thin film transistor T2M9, further ensuring that the PU signal point is at a low level. The PU signal point voltage and the output voltage of the scanning line corresponding to the gate driving circuit 10 are prevented from being leaked, and the problems that the gate driving circuit 10 fails or the display picture is poor due to the low speed and low voltage of the output voltage of the gate driving circuit 10 are further avoided.
Further, the pull-down holding circuit 131 in this embodiment includes: a third thin film transistor T3, a fourth thin film transistor T4, and a fifth thin film transistor T5.
The gate of the third thin film transistor T3 is connected to the PU signal point, the drain of the third thin film transistor T3 is connected to the PD signal point, and the source of the third thin film transistor T3 is connected to the second low voltage module 16; the pull-down maintaining circuit in this embodiment is connected to the first signal source 11, specifically, the first signal source 11 is connected to a third thin film transistor in the pull-down maintaining circuit through a switch, specifically, the switch may also be a thin film transistor, for example, a tenth thin film transistor T10 in fig. 4, a gate of a fourth thin film transistor T4 is connected to the PD signal point, a drain of the fourth thin film transistor T4 is connected to the PU signal point, and a source of the fourth thin film transistor T4 is connected to the second low voltage module 16; the gate of the fifth thin film transistor T5 is connected to the PD signal point, the drain of the fifth thin film transistor T5 is connected to the scan line of the gate driving circuit 10, and the source of the fifth thin film transistor T5 is connected to the first low voltage block 15.
Specifically, the third thin film transistor T3 is configured to charge the PD signal point when the PU signal point is at the second preset voltage, so that the voltage of the PD signal point is equal to the voltage of the second low voltage module 16, and the fourth thin film transistor T4 and the fifth thin film transistor T5 are turned off under the action of the first voltage VSS1 and the second voltage VSS2, so as to control the voltage of the PU signal point to be maintained at the second preset voltage. Wherein the second predetermined voltage is a high voltage.
Specifically, fig. 5 is a pulse sequence diagram of the gate driving circuit provided by the present invention, as shown in fig. 5, when the PU signal point is at a high voltage, the third thin film transistor T3 is turned on to charge the PD signal point, so that the PD voltage is VSS2, wherein the first voltage VSS1 of the first low voltage module 15 is higher than the second voltage VSS2 of the second low voltage module 16, that is, the VSS2 is lower than VSS1, and the negative bias voltages Vgs of the fourth thin film transistor T4 and the fifth thin film transistor T5 are the difference between VSS2 and VSS1 in the charging and outputting phase, and the difference is smaller than zero; according to the characteristics of the thin film transistors, Vgs of the fourth thin film transistor T4 and Vgs of the fifth thin film transistor T5 are respectively smaller than the threshold voltage thereof, so that the fourth thin film transistor T4 and the fifth thin film transistor T5 are always in an off state in the charging and outputting stages, thereby avoiding the problems that the fourth thin film transistor T4 and the fifth thin film transistor T5 in the pull-down maintaining circuit 131 are turned on, the PU signal point voltage and the output voltage of the scan line corresponding to the gate driving circuit 10 are leaked, and further avoiding the problems that the output voltage speed of the gate driving circuit 10 is slow and the voltage is low, which further causes the gate driving circuit 10 to fail, or the display screen is poor.
Further, when PU is at a low potential, the third thin film transistor T3 is turned off, and the first clock signal generator CK1 discharges the PD signal point periodically through the first thin film transistor T1, so that the PD signal point is at a high potential. In order to reduce the voltage stress of the fourth thin film transistor T4 (if the transistor is under high voltage stress for a long time, the threshold voltage of the transistor drifts), in this embodiment, the second thin film transistor T2 is further used to introduce the second clock signal generator CK2 to periodically discharge the PD signal point, and when the second clock signal generator CK2 is at a high level, the second thin film transistor T2 is turned on to pull down the PD signal point potential to the second voltage VSS 2.
Specifically, the adjusting module 14 in this embodiment includes: and a sixth thin film transistor T6.
The gate of the sixth thin film transistor T6 is connected to the signal source, the drain of the sixth thin film transistor T6 is connected to the PD signal point of the gate driving circuit 10, and the source of the sixth thin film transistor T6 is connected to the second low voltage module 16.
When the voltage of the PU signal point is at the initial increasing stage, the sixth thin film transistor T6 is specifically configured to charge the PD signal point, so that the voltage of the PD signal point is equal to the second voltage VSS2 of the second low voltage module 16, and the fourth transistor and the fifth transistor are turned off under the action of the first voltage VSS1 and the second voltage VSS2, so as to control the voltage of the PU signal point to be the second preset voltage.
Specifically, when the gate driving circuit 10 is in the initial pull-up stage, the sixth thin film transistor T6 discharges the PD signal point, so that the potential of the PD signal point is pulled down to the second voltage VSS2, and since the second voltage VSS2 is smaller than the first voltage VSS1, Vgs of the fourth thin film transistor T4 and Vgs of the fifth thin film transistor T5 in the processing module 13 are respectively smaller than the threshold voltage thereof, so that the fourth thin film transistor T4 and the fifth thin film transistor T5 are completely turned off in the initial pull-up stage, and the PU signal point connected thereto can be maintained at a high potential. Further avoiding the problems that the fourth thin film transistor T4 and the fifth thin film transistor T5 are turned on, the PU signal point voltage and the output voltage of the scanning line corresponding to the gate driving circuit 10 are leaked, and further avoiding the problems that the gate driving circuit 10 is low in output voltage speed and low in voltage, and further the gate driving circuit 10 fails or the display picture is poor.
Further, the pull-down maintaining circuit 131 further includes: a seventh thin film transistor T7, an eighth thin film transistor T8, and a ninth thin film transistor T9.
Wherein, the gate of the seventh thin film transistor T7 is connected to the reset signal point of the gate driving circuit 10, specifically, the reset signal point may be represented as R in fig. 4; the drain of the seventh thin film transistor T7 is connected to the PD signal point, and the source of the seventh thin film transistor T7 is connected to the second low voltage module 16; the gate of the eighth tft T8 is connected to the reset signal point, the drain of the eighth tft T8 is connected to the PU signal point, and the source of the eighth tft T8 is connected to the first low voltage module 15; the gate of the ninth thin film transistor T9 is connected to the reset signal point, the drain of the ninth thin film transistor T9 is connected to the scan line of the gate driving circuit 10, and the source of the ninth thin film transistor T9 is connected to the first low voltage module 15.
Further, the gate driving circuit 10 in this embodiment may further include: the pull-up control circuit, the pull-up circuit, the pull-down circuit and the bootstrap capacitor C1.
The pull-up circuit is mainly responsible for outputting a clock signal output by the signal control module 12 as a grid signal; the pull-up control circuit is responsible for controlling the opening time of the pull-up circuit; the pull-down circuit is responsible for pulling down the Gate signal to a low potential at the first time, namely closing the Gate signal; the bootstrap capacitor C1 is responsible for the second lifting of the PU signal point, which is beneficial for the output of the signal in the scan line of the pull-up circuit.
Specifically, the gate driving circuit 10 in this embodiment further includes: a signal source, a tenth thin film transistor T10, an eleventh thin film transistor T11, a twelfth thin film transistor T12, and a thirteenth thin film transistor T13; the signal control module 12 further includes: a third clock signal generator CK3 and a fourth clock signal generator CK 4.
Specifically, the signal source includes a first signal source 11 and a second signal source, wherein the pull-up control circuit includes a tenth thin film transistor T10, a gate and a drain of the tenth thin film transistor T10 are both connected to the first signal source 11, and a source of the tenth thin film transistor T10 is respectively connected to the PU signal point of the gate driving circuit 10.
The pull-up circuit includes: an eleventh thin film transistor T11; the gates of the eleventh tft T11 are connected to the PU signal point, the drain of the eleventh tft T11 is connected to the third clock signal generator CK3, and the source of the eleventh tft T11 is connected to the scan line of the gate driving circuit 10.
The pull-down circuit includes: a twelfth thin film transistor T12 and a thirteenth thin film transistor T13. The gate of the twelfth thin film transistor T12 is connected to the signal source, the drain of the twelfth thin film transistor T12 is connected to the PU signal point, and the source of the twelfth thin film transistor T12 is connected to the first low voltage module 15; the gate of the thirteenth thin film transistor T13 is connected to the fourth clock signal generator CK4, the drain of the fourth thin film transistor T4 is connected to the scan line of the gate driving circuit 10, and the source of the fourth thin film transistor T4 is connected to the first low voltage module 15.
Further, a first terminal of the bootstrap capacitor C1 is connected to the PU signal point, and a second terminal of the bootstrap capacitor C1 is connected to the scan line of the gate driving circuit 10.
The present embodiment further provides a gate driver, specifically, the gate driver includes: the gate driving circuit 10 in the above-described embodiment is multi-staged. The pull-up control circuit of the nth gate driving circuit 10 is connected to the scan line of the nth-2 nd gate driving circuit 10, and the pull-down circuit of the nth gate driving circuit 10 is connected to the scan line of the (N + 3) th gate driving circuit 10. As shown in fig. 4, the first signal source 11 in the above embodiment is an output signal or an STV signal of the N-2 th stage gate driving circuit 10, and the second signal source is an output signal of the N +3 th stage gate driving circuit 10.
In this embodiment, by controlling the turning on or off of the thin film transistor in the pull-down maintaining circuit 131, when the PU signal point is at a high potential or a low potential, the fourth thin film transistor T4 and the fifth thin film transistor T5 are always in a turned-off state in the charging and outputting stages, thereby avoiding leakage of the PU signal point voltage and the output voltage of the scan line of the gate driving circuit 10, and further avoiding the problems of low output voltage speed and low voltage of the gate driving circuit 10, which further causes the failure of the gate driving circuit 10 or the poor display screen.
Specifically, the gate driver in this embodiment can also achieve the specific functions of the gate driving circuit 10, which is not described herein.
Further, as shown in fig. 5, the pull-down holding circuit 131 in this embodiment controls the gate driving circuit 10 to output a low level when the gate driving circuit 10 is in a non-operating state. Specifically, the thin film transistor in the pull-down maintaining circuit 131 enables the gate driving circuit 10 to keep low level output during the non-operating time without generating noise due to interference of the input signal of the signal control module 12 in the gate driving circuit 10 or other signals, and the thin film transistor in the pull-down maintaining circuit 131 only applies a high voltage to the gate of the thin film transistor in the pull-down maintaining circuit 131 when the input of the signal control module 12 is high level, so that the thin film transistor of the gate driving circuit 10 is not biased for a long time, the threshold voltage offset of the thin film transistor can be effectively reduced, and the normal operation of the gate driving circuit 10 is ensured.
In addition, for a thin film transistor in the field of liquid crystal display, a drain and a source are not clearly distinguished, so that the source of the thin film transistor in the present invention may be the drain of the thin film transistor, and the drain of the thin film transistor may also be the source of the thin film transistor.
In this embodiment, when the PU signal point is at a high potential or a low potential and when the PU signal point is at an initial pull-up stage, the PU signal point is maintained at a preset voltage, which avoids leakage of the voltage of the PU signal point and the output voltage of the scan line corresponding to the gate driving circuit 10, and further avoids the problems of low output voltage speed and low voltage of the gate driving circuit 10, which further causes failure of the gate driving circuit 10 or poor display image.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
In the foregoing embodiments of the network device or the terminal device, it should be understood that the Processor may be a Central Processing Unit (CPU), or may be other general-purpose processors, Digital Signal Processors (DSP), Application Specific Integrated Circuits (ASIC), etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present application may be embodied directly in a hardware processor, or in a combination of the hardware and software modules in the processor.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (8)
1. A gate drive circuit, comprising: the device comprises a first signal source, a signal control module, a processing module, an adjusting module, a first low-voltage module and a second low-voltage module;
the processing module is respectively connected with the first signal source, the signal control module and the adjusting module, the adjusting module is also connected with the first signal source, the pull-down maintaining circuit is respectively connected with the first signal source, the first low-voltage module, the second low-voltage module and the signal control module, and the adjusting module is connected with the second low-voltage module;
the first signal source is used for outputting voltage signals to the processing module and the adjusting module;
the first low voltage module is used for outputting a first voltage;
the second low-voltage module is used for outputting a second voltage;
the signal control module is used for outputting control signals to the processing module and the adjusting module;
the processing module and the adjusting module are used for controlling the voltage of a PU signal point of the gate driving circuit to be maintained at a preset voltage according to the control signal and the voltage signal, and the PU signal point of the gate driving circuit is a common connection point of the first signal source and the processing module and the adjusting module;
specifically, the pull-down maintaining circuit and the adjusting module are configured to control the voltage of the PU signal point to be maintained at a preset voltage under the action of the voltage signal, the control signal, the first voltage and the second voltage, wherein the first voltage is greater than the second voltage, a difference between the second voltage and the first voltage is smaller than a threshold voltage of a thin film transistor connected to the PU signal point in the pull-down maintaining circuit, and the threshold voltage is smaller than 0V.
2. The gate driving circuit of claim 1, wherein the signal control module comprises: the pull-down maintaining circuit comprises a first clock signal generator, a second clock signal generator, and further comprises: a first thin film transistor and a second thin film transistor;
the grid electrode and the drain electrode of the first thin film transistor are connected and connected with the first clock signal generator, the source electrode of the first thin film transistor is connected with a PD signal point in the grid electrode driving circuit, the grid electrode of the second thin film transistor is connected with the second clock signal generator, the drain electrode of the second thin film transistor is connected with the PD signal point, and the source electrode of the second thin film transistor is connected with the second low-voltage module;
the control signal is a high potential signal, and the first thin film transistor is used for transmitting the high potential signal of the first clock signal generator; the second thin film transistor is used for transmitting a high potential signal of the second clock signal generator;
when PU signal point is first default voltage, second thin film transistor is used for right PU signal point charges, and is in first voltage with under the effect of second voltage, make the voltage of PU signal point be first default voltage.
3. The gate driving circuit of claim 2, wherein the pull-down sustain circuit comprises: a third thin film transistor, a fourth thin film transistor, and a fifth thin film transistor;
the grid electrode of the third thin film transistor is connected with the PU signal point, the drain electrode of the third thin film transistor is connected with the PD signal point, and the source electrode of the third thin film transistor is connected with the second low-voltage module; the grid electrode of the fourth thin film transistor is connected with a PD signal point of the grid electrode driving circuit, the drain electrode of the fourth thin film transistor is connected with the PU signal point, and the source electrode of the fourth thin film transistor is connected with the first low-voltage module; the grid electrode of the fifth thin film transistor is connected with the PD signal point, the drain electrode of the fifth thin film transistor is connected with the scanning line of the grid driving circuit, and the source electrode of the fifth thin film transistor is connected with the first low-voltage module;
and the third thin film transistor is used for charging the PD signal point when the PU signal point is at a second preset voltage, so that the voltage of the PD signal point is equal to that of the second low-voltage module, the fourth thin film transistor and the fifth thin film transistor are turned off under the action of the first voltage and the second voltage, and the voltage of the PU signal point is controlled to be at the second preset voltage.
4. A gate drive circuit as claimed in claim 3, wherein the adjustment module comprises: a sixth thin film transistor;
the grid electrode of the sixth thin film transistor is connected with the first signal source, the drain electrode of the sixth thin film transistor is connected with a PD signal point of the grid electrode driving circuit, and the source electrode of the sixth thin film transistor is connected with the second low-voltage module;
when the voltage of the PU signal point is at an initial increasing stage, the sixth thin film transistor is specifically configured to charge the PD signal point, so that the voltage of the PD signal point is equal to the voltage of the second low-voltage module, and the fourth thin film transistor and the fifth thin film transistor are turned off under the action of the first voltage and the second voltage, and the voltage of the PU signal point is controlled to be the second preset voltage.
5. The gate driver circuit of claim 4, wherein the pull-down sustain circuit further comprises: a seventh thin film transistor, an eighth thin film transistor, and a ninth thin film transistor;
the grid electrode of the seventh thin film transistor is connected with a reset signal point of the grid electrode driving circuit, the drain electrode of the seventh thin film transistor is connected with the PD signal point, and the source electrode of the seventh thin film transistor is connected with the second low-voltage module;
the grid electrode of the eighth thin film transistor is connected with the reset signal point, the drain electrode of the eighth thin film transistor is connected with the PU signal point, and the source electrode of the eighth thin film transistor is connected with the first low-voltage module;
the grid electrode of the ninth thin film transistor is connected with the reset signal point, the drain electrode of the ninth thin film transistor is connected with the scanning line of the grid electrode driving circuit, and the source electrode of the ninth thin film transistor is connected with the first low-voltage module.
6. The gate driving circuit of claim 5, wherein the signal control module further comprises: third clock signal generator, fourth clock signal generator, gate drive circuit still includes: a second signal source, a tenth thin film transistor, an eleventh thin film transistor, a twelfth thin film transistor, and a thirteenth thin film transistor;
the grid electrode and the drain electrode of the tenth thin film transistor are both connected with the first signal source, and the source electrode of the tenth thin film transistor is respectively connected with a PU signal point of the grid drive circuit;
the grid electrode of the eleventh thin film transistor is respectively connected with the PU signal point, the drain electrode of the eleventh thin film transistor is connected with the third clock signal generator, and the source electrode of the eleventh thin film transistor is connected with the scanning line of the grid electrode driving circuit;
the grid electrode of the twelfth thin film transistor is connected with the second signal source, the drain electrode of the twelfth thin film transistor is connected with the PU signal point, and the source electrode of the twelfth thin film transistor is connected with the first low-voltage module;
the gate of the thirteenth thin film transistor is connected to the fourth clock signal generator, the drain of the fourth thin film transistor is connected to the scan line of the gate driving circuit, and the source of the fourth thin film transistor is connected to the first low voltage module.
7. The gate driving circuit of claim 6, further comprising: a bootstrap capacitor;
the first end of the bootstrap capacitor is connected with the PU signal point, and the second end of the bootstrap capacitor is connected with the scanning line of the gate drive circuit.
8. A gate driver, comprising: a plurality of gate drive circuits as claimed in any one of claims 1 to 7.
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Address after: No. 1778, Qinglan Road, Huangjia Street, Shuangliu District, Chengdu, Sichuan 610200 Patentee after: Chengdu BOE Display Technology Co.,Ltd. Country or region after: China Address before: No. 1778, Qinglan Road, Gongxing street, Shuangliu District, Chengdu, Sichuan 610200 Patentee before: CHENGDU ZHONGDIAN PANDA DISPLAY TECHNOLOGY Co.,Ltd. Country or region before: China |