CN109243514B

CN109243514B - Column selection circuit and EEPROM circuit comprising same

Info

Publication number: CN109243514B
Application number: CN201810980297.0A
Authority: CN
Inventors: 徐兰
Original assignee: Sichuan Zhongwei Xincheng Technology Co ltd
Current assignee: Sichuan Zhongwei Xincheng Technology Co ltd
Priority date: 2018-08-27
Filing date: 2018-08-27
Publication date: 2021-08-06
Anticipated expiration: 2038-08-27
Also published as: CN109243514A

Abstract

The invention particularly relates to a column selection circuit which comprises an RC (resistance-capacitance) filtering unit and a pre-charging unit, wherein the RC filtering unit and the pre-charging unit are both composed of MOS (metal oxide semiconductor) tubes; the RC filtering unit is arranged at the output end of the column selection circuit and used for filtering interference on a power line; the pre-charging unit receives a vpul signal, the vpul signal changes along with the switching of the column address, and the output end of the pre-charging unit is connected with the gate of the high-voltage tube M9 and used for rapidly opening the high-voltage tube M9 when the column address is switched; an EEPROM circuit including the column selection circuit is also included. Interference on a power line can be effectively filtered by arranging the RC filtering unit, meanwhile, the RC filtering unit is composed of an MOS (metal oxide semiconductor) tube, the area increased on a layout can be ignored, the RC filtering unit enables rising edge to be changed slowly, the high-voltage tube M9 cannot be opened rapidly, the problem can be well solved by the arrangement of the pre-charging unit, and the reliability of operation of a column selection circuit is guaranteed.

Description

Column selection circuit and EEPROM circuit comprising same

Technical Field

The present invention relates to the field of non-volatile memory technologies, and in particular, to a column selection circuit and an EEPROM circuit including the column selection circuit.

Background

Electrically erasable memory EEPROM circuits face two major problems: one is the speed problem, which mainly includes that a row selection circuit and a column selection circuit generate long delay time when switching addresses; the other is the problem of error rate, that is, when data is read, a situation that "0" is read as "1" or "1" is read as "0" occurs. One of the main reasons for the occurrence of the error rate is that the power supply voltage provided to the EEPROM circuit in the system is affected by pvt (process voltage temperature) and the surrounding circuits, and a glitch voltage is generated, which is as high as about 1V (i.e. the normal operating voltage of the chip is 5V, and a glitch of about 1V is found on the power supply during the chip testing process). According to the working principle of the EEPROM, when data is read, a sensor circuit compares the current flowing through the EEPROM cell, and outputs the current after the current is shaped by a multi-stage inverter. When the column address of the EEPROM circuit is switched, the glitch voltage on the power supply voltage can cause the situation of misreading after the voltage passes through the sensor circuit.

Aiming at the problem of error rate caused by power supply noise, various measures are usually taken at present, and the method starts from hardware: 1. the capacitor is added on the power line to play a role of filtering, the scheme has a relatively simple structure and mature technology, but the area of the EEPROM circuit is increased; 2. in general, an EEPROM circuit is powered by an LDO or other power management module, and the performance of the power supply rejection ratio of the LDO or the power module is appropriately improved, the scheme has a high requirement on the performance of the LDO, and the circuit structure is relatively complex; 3. the I/O port line is used for supplying power to the EEPROM, and the power is supplied to the device only when the EEPORM is read and written, so that the reliability is improved, the electricity can be saved, and a control circuit of the scheme is complex.

Disclosure of Invention

The invention mainly aims to provide a column selection circuit which can effectively avoid the influence of glitch voltage on a subsequent circuit.

In order to realize the purpose, the invention adopts the technical scheme that: a column selection circuit comprises an RC filtering unit and a pre-charging unit, wherein the RC filtering unit and the pre-charging unit are both composed of MOS (metal oxide semiconductor) tubes; the RC filtering unit is arranged at the output end of the column selection circuit and used for filtering interference on a power line; the precharge unit receives a vpul signal which changes following the switching of the column address, and the output terminal of the precharge unit is connected to the gate of the high voltage pipe M9 for rapidly opening the high voltage pipe M9 upon the switching of the column address.

Compared with the prior art, the invention has the following technical effects: interference on a power line can be effectively filtered by arranging the RC filtering unit, meanwhile, the RC filtering unit is composed of an MOS (metal oxide semiconductor) tube, the area increased on a layout can be ignored, the RC filtering unit enables rising edge to be changed slowly, the high-voltage tube M9 cannot be opened rapidly, the problem can be well solved by the arrangement of the pre-charging unit, and the reliability of operation of a column selection circuit is guaranteed.

Another object of the present invention is to provide an EEPROM circuit including the above column selection circuit, which is small in size and low in bit error rate.

In order to realize the purpose, the invention adopts the technical scheme that: the EEPROM circuit comprises the column selection circuit, a storage circuit, a level conversion circuit, a row selection circuit, a column selection circuit and an SENSER circuit, wherein the level conversion circuit is connected with a control gate of the storage circuit through a high-voltage transmission tube, the row selection circuit is connected with a gating gate of the storage circuit, the column selection circuit is connected with a gate of a high-voltage tube M9, a source electrode of a high-voltage tube M9 is connected with a bit line of the storage circuit, a drain electrode of a high-voltage tube M9 is connected with the SENSER circuit, a source line of the storage circuit is connected with an NMOS, and the control source line of the NMOS is grounded or suspended.

Compared with the prior art, the invention has the following technical effects: because the column selection circuit adopts the improved circuit, the EEPROM circuit manufactured by the improved circuit has the advantages brought by the column selection circuit, the column selection circuit can effectively avoid the influence of the burr voltage on the SENSER circuit, and the SENSER circuit can accurately read the current of the EEPROM cell, thereby reducing the error rate.

Drawings

FIG. 1 is a diagram of a conventional column select circuit;

FIG. 2 is a column select circuit diagram of the present invention;

FIG. 3 is a transient simulation diagram of a conventional column select circuit and a column select circuit of the present invention;

fig. 4 is a circuit diagram of an EEPROM of the present invention.

Detailed Description

The present invention will be described in further detail with reference to fig. 1 to 4.

First, the relationship between the following figures is explained, the circuit in the dashed line frame 1 in fig. 4 corresponds to the circuit in fig. 1 and fig. 2, the high voltage pipe M9 in the circuit diagram in fig. 1 and fig. 2 is NMOS _15P0 in the dashed line frame 1 in fig. 4, Vin in fig. 1 and fig. 2 is the input terminal of the dashed line frame 1 in fig. 4, Vout in fig. 1 and fig. 2 is the SENSER circuit connected to fig. 4, and the resistor R1 in fig. 1 and fig. 2 is the equivalent resistor from the BL line to the ground in fig. 4.

Referring to fig. 2, a column selection circuit includes an RC filtering unit and a pre-charging unit, where the RC filtering unit and the pre-charging unit are both formed by MOS transistors; the RC filtering unit is arranged at the output end of the column selection circuit and used for filtering interference on a power line; the precharge unit receives a vpul signal which changes following the switching of the column address, and the output terminal of the precharge unit is connected to the gate of the high voltage pipe M9 for rapidly opening the high voltage pipe M9 upon the switching of the column address. Interference on a power line can be effectively filtered by arranging the RC filtering unit, meanwhile, the RC filtering unit is composed of an MOS (metal oxide semiconductor) tube, the area increased on a layout can be ignored, the RC filtering unit enables rising edge to be changed slowly, the high-voltage tube M9 cannot be opened rapidly, the problem can be well solved by the arrangement of the pre-charging unit, and the reliability of operation of a column selection circuit is guaranteed.

Fig. 1 is a conventional column selection circuit, and in order to further illustrate the scheme of the present invention in detail, fig. 1 is modified to illustrate how the RC filtering unit and the pre-charging unit are arranged in detail. The invention specifically comprises the following steps: the inverter comprises a first inverter, a second inverter, a third inverter and MOS transistors M1-M8, wherein the MOS transistors M1-M8 comprise MOS transistors M1, M2, M3, M4, M5, M6, M7 and M8, the input end of the first inverter forms the input end of a column selection circuit, the output end of the first inverter is connected with the input end of the second inverter and the grid electrode of the NMOS transistor M4, the output end of the second inverter is singly connected with the grid electrode of the NMOS transistor M4, the drain electrode of the PMOS transistor M4 and the grid electrode of the PMOS transistor M4 are connected, the grid electrode of the PMOS transistor M4, the drain electrode of the NMOS transistor M4 and the drain electrode of the NMOS transistor M4 are connected with the input end of the third inverter, the output end of the third inverter is connected with the grid electrode of the PMOS transistor M4 and the grid electrode of the NMOS transistor M4, the drain electrode of the PMOS transistor M4 is connected with a high-voltage signal transistor vM 4, the sources of the PMOS tubes M1, M2, M5 and M7 are all connected with a power supply VDD, and the sources of the NMOS tubes M3, M4, M6 and M8 and the drain of the NMOS tube M8 are all grounded; the PMOS tube M5 is an inverse ratio tube to form a resistor, the NMOS tube M8 forms a capacitor, and the PMOS tube M5 and the NMOS tube M8 form the RC filter unit; the PMOS transistor M7 constitutes the precharge unit.

The PMOS tube M5 is equivalent to a large resistor, the NMOS tube M8 is a capacitor realized by adopting an MOS tube, so that the area is saved, the area increased on the layout can be ignored, the PMOS tubes M5 and M8 realize the RC filtering function, the interference or burr on a power line can be reduced, the situation that an interference signal is introduced into the input of the SENSER circuit when the high-voltage tube NMOS tube M9 is opened is avoided, and the probability of misreading is greatly reduced. However, when the column select signal arrives (the PC signal changes from "0" to "1"), RC filtering slows down the rising edge change, causing the NMOS transistor M9 to not turn on quickly, resulting in a slow read speed, and in the worst case, directly causing all errors in the read data. To solve this problem, a precharge signal is added to the gate of the NMOS transistor M9, and implemented by the PMOS transistor M7. The vpul signal follows the switching of the column address, so that each time the column select signal is turned on, the gate of the NMOS transistor M9 is high and M9 is turned on rapidly.

In the GLFEE013 process, the schematic diagrams of fig. 1 and 2 were simulated and verified using a spectre simulation tool, and the excitation of Vin was at a frequency of 12.5MHz, as seen from bottom to top in fig. 3, the first curve is the output of fig. 2, and the second curve is the output of fig. 1. Simulation results show that when a voltage interference signal of +/-1V is added to 5V of a power supply, the output of the SENSOR circuit in the prior art has a disturbance voltage of 410mV, and a 1.5V power supply is used in the SENSOR circuit, obviously, the disturbance voltage of 410mV directly influences the reading of data, and the output of the SENSOR circuit in the prior art has a disturbance voltage of only 77.37mV, which is far less than 410mV, and 77.37mV is very small compared with 1.5V, and basically does not influence the reading of data. As can be seen from fig. 3, the column selection circuit after adding the RC filtering unit and the pre-charging unit effectively reduces the power supply interference.

Referring to fig. 4, the memory circuit comprises a storage circuit, a level conversion circuit, a row selection circuit, a column selection circuit and a senter circuit, wherein the level conversion circuit is connected with a control gate of the storage circuit through a high-voltage transmission tube, the row selection circuit is connected with a gate of the storage circuit, the column selection circuit is connected with a gate of a high-voltage tube M9, a source of the high-voltage tube M9 is connected with a bit line of the storage circuit, a drain of the high-voltage tube M9 is connected with the senter circuit, a source line of the storage circuit is connected with an NMOS, and the NMOS controls the source line to be grounded or suspended. In fig. 4, the storage circuit corresponds to a dashed line box 2, the level shift circuit corresponds to a Lever shift circuit2 box, the row selection circuit corresponds to a left Lever shift circuit1, the high voltage pass transistor corresponds to an NMOS transistor BST, the column selection circuit corresponds to a Lever shift circuit1 in the dashed line box 1, and the high voltage transistor M9 corresponds to an NMOS _15P0 in the dashed line box 1. Because the column selection circuit adopts the improved circuit, the EEPROM circuit manufactured by the improved circuit has the advantages brought by the column selection circuit, the column selection circuit can effectively avoid the influence of the burr voltage on the SENSER circuit, and the SENSER circuit can accurately read the current of the EEPROM cell, thereby reducing the error rate.

Claims

1. A column selection circuit, characterized by: the circuit comprises an RC filtering unit and a pre-charging unit, wherein the RC filtering unit and the pre-charging unit are both composed of MOS (metal oxide semiconductor) tubes; the RC filtering unit is arranged at the output end of the column selection circuit and used for filtering interference on a power line; the pre-charging unit receives a vpul signal, the vpul signal changes along with the switching of the column address, and the output end of the pre-charging unit is connected with the gate of the high-voltage tube M9 and used for rapidly opening the high-voltage tube M9 when the column address is switched;

the high-voltage power supply comprises a first inverter, a second inverter, a third inverter and MOS tubes M1-M8, wherein the input end of the first inverter forms the input end of a column selection circuit, the output end of the first inverter is connected with the input end of the second inverter and the grid electrode of an NMOS tube M4, the output end of the second inverter is singly connected with the grid electrode of an NMOS tube M3, the drain electrode of an NMOS tube M3, the drain electrode of a PMOS tube M1 and the grid electrode of a PMOS tube M2 are connected, the grid electrode of the PMOS tube M1, the drain electrode of a PMOS tube M2 and the drain electrode of an NMOS tube M4 are connected with the input end of the third inverter, the output end of the third inverter is connected with the grid electrode of a PMOS tube M5 and the grid electrode of an NMOS tube M6, the drain electrode of the PMOS tube M5, the drain electrode of an NMOS tube M6, the drain electrode of the PMOS tube M7 and the grid electrode of an NMOS tube M8 are connected with the grid electrode of a high-voltage tube M9, the grid electrode of the PMOS tube M7 is connected with vpul signals, the source electrodes of the PMOS tubes M1, M2, M68656, the power supply M828653 and the NMOS tubes M828653, the NMOS tubes M3 are connected with the NMOS tubes M3, and the NMOS tubes M7, and the NMOS tubes M3, and the PMOS tubes M7, and the power supply are connected with the power supply sources of the NMOS tubes M3, The sources of M6 and M8 and the drain of the NMOS transistor M8 are grounded;

the PMOS tube M5 is an inverse ratio tube to form a resistor, the NMOS tube M8 forms a capacitor, and the PMOS tube M5 and the NMOS tube M8 form the RC filter unit; the PMOS transistor M7 constitutes the precharge unit.

2. An EEPROM circuit comprising the column select circuit of claim 1, wherein: the high-voltage power supply comprises a storage circuit, a level conversion circuit, a row selection circuit, a column selection circuit and an SENSER circuit, wherein the level conversion circuit is connected with a control gate of the storage circuit through a high-voltage transmission tube, the row selection circuit is connected with a gating gate of the storage circuit, the column selection circuit is connected with a gate of a high-voltage tube M9, a source electrode of a high-voltage tube M9 is connected with a bit line of the storage circuit, a drain electrode of a high-voltage tube M9 is connected with the SENSER circuit, a source line of the storage circuit is connected with an NMOS, and the source line of the NMOS is controlled to be grounded or suspended.