CN109240159B - Multi-channel synchronous signal triggering method, terminal, data acquisition system and storage medium - Google Patents
Multi-channel synchronous signal triggering method, terminal, data acquisition system and storage medium Download PDFInfo
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- CN109240159B CN109240159B CN201811078772.1A CN201811078772A CN109240159B CN 109240159 B CN109240159 B CN 109240159B CN 201811078772 A CN201811078772 A CN 201811078772A CN 109240159 B CN109240159 B CN 109240159B
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
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- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
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Abstract
The invention discloses a multi-channel synchronous signal triggering method, a terminal, a data acquisition system and a storage medium, wherein the multi-channel synchronous signal triggering method comprises a synchronous signal generating and outputting process, and the synchronous signal generating and outputting process specifically comprises the following steps: receiving a clock signal; when the effective edge of the clock signal arrives, simultaneously triggering a control logic program corresponding to each output channel, and respectively generating output signals corresponding to each output channel by each control logic program; and outputting each path of output signals from the corresponding output channel. The multi-channel synchronous signal triggering method, the terminal, the data acquisition system and the storage medium of the invention set the control logic programs corresponding to each output channel and trigger the logic control programs by adopting the same clock signal to realize the synchronous generation and synchronous output of the output signals corresponding to each sensor, thus each sensor can synchronously acquire data and each sensor can acquire data at the optimal data acquisition frequency.
Description
Technical Field
The invention relates to the technical field of robots, in particular to a multi-channel synchronous signal triggering method, a terminal, a data acquisition system and a storage medium.
Background
In the field of robots, various sensors are needed to be used for sensing external environments of robots to acquire various data, commonly used sensors such as laser radars, visual sensors (ordinary cameras, depth-of-field cameras, infrared cameras and the like), infrared sensors, auditory sensors (microphones and the like), inertial measurement sensors and the like have different data acquisition frequencies, the data acquisition frequency of some sensors can reach 1000Hz, the data acquisition frequency of some sensors can only reach 100Hz at most, in order to ensure the synchronism of signals acquired by various sensors, in the prior art, a controller can send the same clock signal to all the sensors, so that some sensors cannot reach the required acquisition frequency, in the prior art, another method is to output control signals to all the sensors in sequence by adopting serial signals, but the synchronism of the data acquired by all the sensors is poor, the control signals of each path have time delay caused by sentence execution, and the control method is difficult to achieve satisfactory effect on occasions with high requirement on data synchronism.
Disclosure of Invention
The purpose of the invention is as follows: in order to overcome the defects in the prior art, the invention provides a multi-channel synchronous signal triggering method, a terminal, a data acquisition system and a storage medium, aiming at ensuring that the data acquisition synchronism of each channel of sensor is better and the optimal data acquisition frequency of each sensor can be achieved.
The technical scheme is as follows: in order to achieve the above object, the multi-channel synchronization signal triggering method of the present invention includes a synchronization signal generation and output process, where the synchronization signal generation and output process specifically includes:
receiving a clock signal;
when the effective edge of the clock signal arrives, simultaneously triggering a control logic program corresponding to each output channel, and respectively generating output signals corresponding to each output channel by each control logic program; wherein the effective edge is a rising edge or a falling edge;
and outputting each path of output signals from the corresponding output channel.
Optionally, the simultaneously triggering the control logic program corresponding to each output channel, and generating the output signal corresponding to each output channel specifically includes:
each control logic program independently generates an output signal corresponding to each output channel immediately or delayed for a time period, in the latter case measured in units of microframes, a period of said clock signal being equal to an integer number of microframes.
Optionally, the method further includes a clock calibration process, the clock calibration process running independently of the synchronization signal generation and output process, and the clock calibration process includes:
receiving a clock signal;
starting from the second effective edge, judging the error condition of the actual time interval of the arrival of two adjacent effective edges of the clock signal according to a high-precision clock in the processor;
and generating and outputting a corresponding feedback signal according to the error condition.
Optionally, the generating and outputting a corresponding feedback signal according to the error condition includes;
if the actual time interval of the arrival of two adjacent effective edges of the clock signal is shorter than the expected time interval and the error magnitude exceeds a certain threshold value, an error signal is generated and output through a specific feedback signal output channel.
Optionally, the generating and outputting a corresponding feedback signal according to the error condition further includes;
if the error of the actual time interval of the arrival of two adjacent effective edges of the clock signal relative to the expected time interval exceeds a certain threshold value, a distortion signal is generated and output through a specific feedback signal output channel.
Optionally, after generating and outputting the corresponding feedback signal according to the error condition, the method further includes:
and receiving and executing a processing result.
Optionally, the receiving and executing the processing result includes:
and receiving an interrupt signal and interrupting the synchronous signal generation and output process.
A terminal comprises a processor, a memory, a clock signal input module and a synchronous signal output module, wherein the memory, the clock signal input module and the synchronous signal output module are all connected with the processor, and the synchronous signal output module comprises a plurality of output channels; the memory is internally provided with an executable program, and the processor executes the executable program to realize the multi-channel synchronous signal triggering method; and the device also comprises a feedback signal output channel connected with the processor.
The utility model provides a data acquisition system, includes above-mentioned terminal, upper processing unit and a plurality of sensor, upper processing unit connects the clock signal input module and the feedback signal output channel at terminal, each way output channel at terminal all is connected with the sensor.
A storage medium having stored therein an executable program which, when executed, implements the above-described multiple-way synchronization signal triggering method.
Has the advantages that: the multi-channel synchronous signal triggering method, the terminal, the data acquisition system and the storage medium of the invention set the control logic programs corresponding to each output channel and trigger the logic control programs by adopting the same clock signal to realize the synchronous generation and synchronous output of the output signals corresponding to each sensor, thus each sensor can synchronously acquire data and each sensor can acquire data at the optimal data acquisition frequency.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a hardware structure of a terminal according to various embodiments of the present invention;
fig. 2 is a schematic diagram of a hardware structure of a data acquisition system according to various embodiments of the present invention;
fig. 3 is a flowchart illustrating a process of generating and outputting a sync signal in a multi-channel sync signal triggering method according to an embodiment of the present invention;
fig. 4 is a flow chart of a clock calibration process.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In the following description, suffixes such as "module", "part", or "unit" used to denote elements are used only for facilitating the explanation of the present invention, and have no intended meaning by themselves. Thus, "module", "component" or "unit" may be used mixedly.
In addition, the technical features involved in the embodiments of the present invention described below may be mutually used as long as they do not conflict with each other.
Referring to fig. 1, which is a schematic structural diagram of a terminal 100 for implementing various embodiments of the present invention, the terminal 100 includes a processor 101, a memory 102, a clock signal input module 103, and a synchronization signal output module 104, where the memory 102, the clock signal input module 103, and the synchronization signal output module 104 are all connected to the processor 101, and the synchronization signal output module 104 includes a plurality of output channels; an executable program is stored in the memory 102, and the processor 101 executes the executable program to implement the above-mentioned multi-channel synchronization signal triggering method; a feedback signal output channel 105 is also included which is connected to the processor 101. Those skilled in the art will appreciate that the terminal structure shown in fig. 1 does not constitute a limitation of the terminal device, and that the terminal may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.
The following describes each component of the terminal device in detail with reference to fig. 1:
the memory 102 may be used to store software programs as well as various data. The memory 102 may mainly include a program storage area and a data storage area, wherein the program storage area may store an application program and the like required for at least one function.
The processor 101 is a control center of the terminal 100, connects various parts of the entire terminal 100 using various interfaces and lines, and performs various functions of the terminal 100 and processes data by running or executing software programs and/or modules stored in the memory 102 and calling data stored in the memory 102. In this embodiment, the processor 101 is a CPLD chip.
The clock signal input module 103 is used for receiving an external clock signal as a trigger signal for the operation of the terminal 100.
The plurality of output channels included in the synchronization signal output module 104 may respectively output control signals to control the components connected to the output channels.
The terminal 100 may be implemented in various forms, and may be a circuit board, a product with a package housing, or the like.
The multi-sensor data acquisition system based on the terminal 100 comprises the terminal 100, an upper processing unit 200 and a plurality of sensors 300, wherein the upper processing unit 200 is connected with a clock signal input module 103 and a feedback signal output channel 105 of the terminal 100, each output channel of the terminal 100 is connected with a sensor 300, and all the sensors 300 can be connected with the upper processing unit 200 or other data processing equipment.
The upper processing unit 200 may be a common data processing device such as a PC, a mobile phone, a tablet, or may be a specific circuit board with data processing capability, a dedicated device, or the like, which is designed by an engineer as required.
The plurality of sensors 300 include various sensors such as a laser radar, a vision sensor (a general camera, a depth camera, an infrared camera, etc.), an infrared sensor, an auditory sensor (a microphone, etc.), and an inertial measurement sensor.
The method for triggering multiple synchronization signals based on the terminal 100 includes a synchronization signal generation and output process, where the synchronization signal generation and output process specifically includes the following steps S401 to S403:
step S401: receiving a clock signal;
in this step, a clock signal is provided by the upper processing unit 200, the clock signal is a periodic square wave type, and triggers a type of event through a rising edge or a falling edge, and a common clock signal is a 1PPS pulse signal.
Step S402: when the effective edge of the clock signal arrives, simultaneously triggering a control logic program corresponding to each output channel, and respectively generating output signals corresponding to each output channel by each control logic program; wherein the effective edge is a rising edge or a falling edge;
step S403: and outputting each path of output signals from the corresponding output channel.
In step S402-step S403, after an effective edge of the clock signal arrives, a periodic task is issued to the terminal 100, the control logic program generates an output signal whose duration does not exceed the period of the clock signal to the sensor 300 connected to its corresponding output channel, and when the next effective edge arrives, a periodic task is issued to the terminal 100, and the control logic program continues to generate an output signal whose duration does not exceed the period of the clock signal; and executing the task in such a cycle, and when no more valid edges arrive, all output channels are restored to be in an invalid state.
Optionally, in step S402, the simultaneously triggering the control logic program corresponding to each output channel, and generating the output signal corresponding to each output channel specifically includes:
each control logic program independently generates an output signal corresponding to each output channel immediately or delayed for a time period, in the latter case measured in units of microframes, a period of said clock signal being equal to an integer number of microframes.
In actual operation, the duration of the 1-micro frame is generally smaller than the duration of one period of the clock signal by several orders of magnitude, and if the clock signal is a 1PPS pulse signal, the 1-micro frame may represent 1ms, and of course, the 1-micro frame may be adjusted to other durations as needed. By adopting a micro-frame triggering offset mode, the time for starting to be effective (outputting output signals) of each output channel can be more accurately adjusted, asynchronous errors accurate to millisecond level are made up, and the synchronism of each output signal is further ensured.
Optionally, a clock calibration procedure is further included, the clock calibration procedure runs independently of the synchronization signal generation and output procedure, and the clock calibration procedure includes the following steps S501 to S503:
step S501: receiving a clock signal;
step S502: starting from the second effective edge, judging the error condition of the actual time interval of the arrival of two adjacent effective edges of the clock signal according to a high-precision clock in the processor 101;
step S503: and generating and outputting a corresponding feedback signal according to the error condition.
Optionally, the generating and outputting a corresponding feedback signal according to the error condition includes;
if the actual time interval between the arrival of two adjacent valid edges of the clock signal is shorter than the expected time interval and the error magnitude exceeds a certain threshold, an error signal is generated and output through a specific feedback signal output channel 105. For example, in a normal state, the signal output by the feedback signal output channel 105 is low, and the error signal may be a 5ms high pulse.
Optionally, the generating and outputting a corresponding feedback signal according to the error condition further includes;
if the actual time interval of the arrival of two adjacent valid edges of the clock signal has an error exceeding a certain threshold (e.g., 1us) with respect to the expected time interval, a distortion signal is generated and output through a specific feedback signal output channel 105. For example, in a normal state, the signal output by the feedback signal output channel 105 is low, and the error signal may be a 5ms high pulse. The feedback signal output channel 105 that outputs the distortion signal is not the same output channel as the feedback signal output channel 105 that outputs the error signal.
Optionally, after generating and outputting the corresponding feedback signal according to the error condition, the method further includes:
step S504: and receiving and executing the processing result of the upper processing unit.
That is, in step S503, the feedback signal is fed back to the upper processing unit 200 through the feedback signal output channel 105, the upper processing unit 200 determines the error information according to the source of the feedback signal (from which feedback signal output channel 105), and sends the processing result to the processor 101, and the processor 101 executes the corresponding operation according to the processing result.
Optionally, the receiving and executing the processing result includes:
and receiving an interrupt signal and interrupting the synchronous signal generation and output process.
Of course, the upper processing unit 200 may directly push error information or an alarm to the manager for solution without transmitting the processing result to the processor 101.
The embodiment of the invention also provides a storage medium, wherein an executable program is stored in the storage medium, and when the executable program is executed, the multipath synchronous signal triggering method is realized.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (such as a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (9)
1. A multi-channel synchronization signal triggering method is characterized in that the method comprises a synchronization signal generation and output process, and the synchronization signal generation and output process specifically comprises the following steps:
receiving a clock signal;
when the effective edge of the clock signal arrives, simultaneously triggering a control logic program corresponding to each output channel, and respectively generating output signals corresponding to each output channel by each control logic program; wherein the effective edge is a rising edge or a falling edge;
outputting each path of output signals from the corresponding output channel; the output signals of each path are output to the sensors connected with the output channels from the corresponding output channels, the types of the sensors in the sensors connected with the output channels are various, and the frequency of data acquisition of various sensors is different;
the simultaneously triggering the control logic program corresponding to each output channel to generate the output signals corresponding to each output channel specifically includes:
each control logic program independently generates output signals corresponding to each output channel immediately or after a certain time, in the latter case, the delayed time takes a micro-frame as a time measurement unit, and one period of the clock signal is equal to an integer number of micro-frames;
each control logic program generates an output signal with the duration not exceeding the period of the clock signal to a sensor connected with a corresponding output channel after an effective edge of the clock signal arrives; and executing the task in such a cycle, and when no more valid edges arrive, all output channels are restored to be in an invalid state.
2. The method as claimed in claim 1, further comprising a clock calibration procedure, said clock calibration procedure running independently of said synchronization signal generation and output procedure, said clock calibration procedure comprising:
receiving a clock signal;
starting from the second effective edge, judging the error condition of the actual time interval of the arrival of two adjacent effective edges of the clock signal according to a high-precision clock in the processor;
and generating and outputting a corresponding feedback signal according to the error condition.
3. The method for triggering multiple synchronous signals according to claim 2, wherein said generating and outputting corresponding feedback signals according to said error condition comprises;
if the actual time interval of the arrival of two adjacent effective edges of the clock signal is shorter than the expected time interval and the error magnitude exceeds a certain threshold value, an error signal is generated and output through a specific feedback signal output channel.
4. The method for triggering multiple synchronous signals according to claim 3, wherein said generating and outputting corresponding feedback signals according to said error condition further comprises;
if the error of the actual time interval of the arrival of two adjacent effective edges of the clock signal relative to the expected time interval exceeds a certain threshold value, a distortion signal is generated and output through a specific feedback signal output channel.
5. The method as claimed in claim 2, wherein the step of generating and outputting the corresponding feedback signal according to the error condition further comprises:
and receiving and executing a processing result.
6. The multiple-synchronization signal triggering method according to claim 5, wherein the receiving and executing the processing result comprises:
and receiving an interrupt signal and interrupting the synchronous signal generation and output process.
7. A terminal is characterized by comprising a processor, a memory, a clock signal input module and a synchronous signal output module, wherein the memory, the clock signal input module and the synchronous signal output module are all connected with the processor, and the synchronous signal output module comprises a plurality of output channels; an executable program is stored in the memory, and the processor executes the executable program to realize the multipath synchronous signal triggering method of any one of claims 1-6; and the device also comprises a feedback signal output channel connected with the processor.
8. A data acquisition system, comprising the terminal as claimed in claim 7, an upper processing unit, and a plurality of sensors, wherein the upper processing unit is connected to the clock signal input module and the feedback signal output channel of the terminal, and each output channel of the terminal is connected to a sensor.
9. A storage medium having stored therein an executable program which, when executed, implements the multiple sync signal triggering method of any one of claims 1-6.
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| CN111601133B (en) * | 2019-02-21 | 2022-07-01 | 杭州海康威视数字技术股份有限公司 | Multimedia data synchronous output system and method |
| CN111880603B (en) * | 2020-07-27 | 2022-06-17 | 浪潮集团有限公司 | Multi-chassis feedback result control trigger synchronization method, device, equipment and medium |
| CN112558514B (en) * | 2020-11-17 | 2022-03-29 | 中山大学 | Multi-device hardware synchronization method |
| CN113721703B (en) * | 2021-08-19 | 2024-02-13 | 飞腾信息技术有限公司 | Clock synchronization control device, system and control method in multi-path CPU system |
| CN114449129B (en) * | 2022-01-21 | 2024-04-09 | 地平线(上海)人工智能技术有限公司 | Multi-sensor time synchronization method and device, electronic equipment and storage medium |
| CN117156300B (en) * | 2023-10-30 | 2024-02-02 | 北原科技(深圳)有限公司 | Video stream synthesis method and device based on image sensor, equipment and medium |
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| CN102495912B (en) * | 2011-10-26 | 2013-11-20 | 电子科技大学 | Multi-channel high-speed data acquisition system with synchronous correction function |
| CN103326802A (en) * | 2013-05-31 | 2013-09-25 | 燕山大学 | Wireless network system for achieving synchronous acquisition, synchronous acquisition device and method |
| CN104570838A (en) * | 2014-12-02 | 2015-04-29 | 中国科学院西安光学精密机械研究所 | Asynchronous external trigger device and method for multipath trigger delay |
| CN105892560A (en) * | 2016-03-29 | 2016-08-24 | 杭州和利时自动化有限公司 | Clock detection method and system used for embedded system |
| CN108303621A (en) * | 2017-12-15 | 2018-07-20 | 山东康威通信技术股份有限公司 | The front end data acquisition and buffer circuit, system and method for partial discharge are synchronized based on clock |
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