CN109217108B - Method for manufacturing semiconductor laser by impurity induced hybrid technology - Google Patents
Method for manufacturing semiconductor laser by impurity induced hybrid technology Download PDFInfo
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- CN109217108B CN109217108B CN201710530774.9A CN201710530774A CN109217108B CN 109217108 B CN109217108 B CN 109217108B CN 201710530774 A CN201710530774 A CN 201710530774A CN 109217108 B CN109217108 B CN 109217108B
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Abstract
The invention discloses a method for manufacturing a semiconductor laser by utilizing an impurity induction hybrid technology, which comprises the following steps: preparing an epitaxial wafer; etching a current injection region and a non-current injection region on the epitaxial wafer; photoetching a window area at the front cavity surface in the current injection area; depositing a layer of copper on the window area at the front cavity surface as a metal film for promoting blue shift; growing a first mask layer in the current injection region, covering the first mask layer above the copper, growing a second mask layer in the non-current injection region, annealing, and realizing quantum well mixing in a window region at the front cavity surface; etching the first mask layer by photoetching, and reserving the second mask layer to provide a current limiting effect; and sequentially manufacturing a P-surface electrode and an N-surface electrode to finish the manufacture of the semiconductor laser. The method has the advantages of low annealing temperature, effective prevention of overflow of V-group elements such as arsenic and the like due to the adoption of the mask, guarantee of higher crystal quality of the annealed epitaxial wafer, simple process, high repeatability, short time consumption, low cost and contribution to mass production.
Description
Technical Field
The present disclosure belongs to the field of semiconductor photoelectronic devices, and relates to a method for manufacturing a semiconductor laser by utilizing an impurity induced hybrid technology.
Background
The semiconductor laser has the characteristics of high conversion efficiency, small volume, light weight, long service life, high reliability, direct modulation, easy integration with other semiconductor devices and the like, and is widely and deeply applied to the fields of military affairs, industrial processing, precision measurement, laser medical treatment, optical communication, optical storage, laser printing and the like.
During the performance test and practical use of semiconductor lasers, it is found that the main factors limiting the further increase of power are thermal saturation and Optical Catastrophic damage (COD) at the cavity surface. With the improvement of novel materials such as high-thermal-conductivity solder, high-heat-dissipation-efficiency heat sink structure design, more efficient water cooling system and the like and the improvement of semiconductor laser packaging technology, the thermal saturation phenomenon is improved to a great extent, so that COD becomes a main factor for limiting the further improvement of the power of the semiconductor laser and limiting the service life of the semiconductor laser under high power.
At present, in the aspect of improving the COD threshold power of a semiconductor laser, the adopted methods are mainly divided into three categories: reducing optical power density at the facets, reducing non-radiative recombination rates, and reducing optical absorption at the facets. The method comprises the steps of epitaxial structure of a large optical cavity and an ultra-large optical cavity, surface treatment technologies such as vacuum cleavage and film coating cavity surface passivation technology, vulcanization treatment and plasma treatment, passivation layer plating, aluminum-free active region adoption, epitaxial regrowth, ultra-short laser pulse irradiation, quantum well mixing and the like.
Therefore, in many schemes for manufacturing semiconductor lasers, the following technical problems still remain to be solved: complex process, low repeatability, long time consumption, high manufacturing cost, being not beneficial to mass production and the like.
Disclosure of Invention
Technical problem to be solved
The present disclosure provides a method of fabricating a semiconductor laser using impurity induced intermixing techniques to at least partially address the technical problems set forth above.
(II) technical scheme
According to one aspect of the present disclosure, there is provided a method of fabricating a semiconductor laser using impurity induced intermixing techniques, comprising: preparing an epitaxial wafer; etching a current injection region and a non-current injection region on the epitaxial wafer; photoetching a window area at the front cavity surface in the current injection area; depositing a layer of copper 300 on the window area at the front cavity surface as a metal film for promoting blue shift; growing a first mask layer 410 in the current injection region to cover the copper 300, growing a second mask layer 420 in the non-current injection region, and performing annealing treatment to realize quantum well mixing in the window region at the front cavity surface; the first mask layer 410 is etched away by photolithography, and the second mask layer 420 is left to provide a current limiting effect; and sequentially manufacturing a P-surface electrode 510 and an N-surface electrode 520, thereby completing the manufacture of the semiconductor laser.
In some embodiments of the present disclosure, the first mask layer 410 and the second mask layer 420 are both dielectric films that suppress quantum well intermixing.
In some embodiments of the present disclosure, the first mask layer 410 and the second mask layer 420 are grown by PECVD;
in some embodiments of the present disclosure, the material of the first mask layer 410 is silicon dioxide; the material of the second mask layer 420 is one of the following materials: silicon dioxide and silicon nitride; the first mask layer 410 and the second mask layer 420 both have a thickness between 50nm and 500 nm.
In some embodiments of the present disclosure, the preparation of the epitaxial wafer comprises: a buffer layer 102, a lower confinement layer 103, a lower waveguide layer 104, a quantum well active region 105, an upper waveguide layer 106, an upper confinement layer 107, and an ohmic contact layer 108 are epitaxially grown in this order on a substrate 101 to form an epitaxial wafer.
In some embodiments of the present disclosure, etching the current injection region and the non-current injection region on the epitaxial wafer includes: etching is carried out from the left side and the right side of the uppermost layer of the epitaxial wafer, the ohmic contact layer 108 and part of the upper limiting layer 107 are etched, the remaining upper limiting layer 107 in the middle and the ohmic contact layer 108 positioned on the upper limiting layer are current injection regions, and the exposed upper limiting layers 107 on the two sides are non-current injection regions.
In some embodiments of the present disclosure, the depth of the etched-away ohmic contact layer 108 and the partially upper limiting layer 107 is between 200nm and 1500nm, and the width is between 5 μm and 200 μm, depending on the desired beam quality and the magnitude of the output power.
In some embodiments of the present disclosure, depositing a layer of copper 300 on the window region at the front facet includes: depositing a layer of copper 300 on the whole epitaxial wafer, and in the process of photoetching a window area at the front cavity surface in the current injection area, exposing the ohmic contact layer 108 except the window area at the front cavity surface, wherein the window area does not contain the photoresist 200, and the rest areas are covered by the photoresist 200; the thin layer of copper in the region outside the window area at the front facet and the photoresist 200 thereunder are then removed after the copper 300 has been deposited.
In some embodiments of the present disclosure, the manner of depositing the copper 300 on the epitaxial wafer is magnetron sputtering; the width of the window area at the front cavity surface in the cavity length direction is between 5nm and 50 nm; the copper 300 deposited on the epitaxial wafer is high-purity thin copper, and the thickness of the copper is between 2nm and 20 nm; the photoresist 200 is a negative resist.
In some embodiments of the present disclosure, the material of the quantum well active region 105 is one of the following materials: indium gallium arsenide/gallium arsenide, aluminum gallium indium arsenide/aluminum gallium arsenic, aluminum gallium indium arsenide/gallium arsenic phosphide, gallium indium phosphide/aluminum gallium indium phosphide or aluminum gallium indium arsenide/aluminum gallium indium arsenide.
In some embodiments of the present disclosure, the annealing treatment is implemented by RTA rapid thermal annealing equipment, and the annealing temperature T satisfies: t is more than or equal to 750 ℃ and less than or equal to 850 ℃, and the annealing time T satisfies the following condition: t is more than or equal to 60s and less than or equal to 180s, and the annealing time and the annealing temperature depend on the difference of materials of the epitaxial wafer and the blue shift amount of the required quantum well active region.
(III) advantageous effects
According to the technical scheme, the method for manufacturing the semiconductor laser by using the impurity induced hybrid technology has at least one of the following beneficial effects:
1. the method has the advantages that Cu is used as a metal film for promoting blue shift, silicon dioxide, silicon nitride and the like are used as masks for inhibiting blue shift, the gain region can be masked at a lower temperature without an additional mask, so that the forbidden bandwidth of a quantum well in the region after epitaxial growth can be kept, a certain amount of blue shift of the wavelength of the quantum well is generated in the region covered with the copper, a blue shift effect is obtained, the blue shift effect with considerable blue shift can be obtained without the technologies of secondary epitaxy, passivation of the cavity surface of a vacuum cleavage coating film, vulcanization and the like, and the method is simple in process, high in repeatability, short in time consumption, low in cost and beneficial to mass production;
2. compared with other thermal annealing technologies with obvious blue shift amount only at the temperature of 900 ℃, the scheme disclosed by the invention can realize blue shift at the temperature of 750 ℃, and the adoption of the mask can effectively prevent the overflow of V-group elements such as arsenic and the like, thereby ensuring that the epitaxial chip still keeps high crystal quality after annealing;
3. the method can also be applied to scenes needing different forbidden band widths, such as a multi-wavelength laser, a multi-wavelength photon integrated transmitting chip and the like, and has a wide application range.
Drawings
Fig. 1 is a flow chart of a method of fabricating a semiconductor laser using impurity induced intermixing techniques according to an embodiment of the present disclosure.
Fig. 2A is a schematic view of an epitaxial structure and a three-dimensional structure after one-time photolithography for fabricating a semiconductor laser chip according to an embodiment of the present disclosure.
Fig. 2B is a schematic three-dimensional structure diagram of a window region formed at the front cavity surface by photolithography of a stripe region with a certain width in the current injection region according to an embodiment of the present disclosure.
Fig. 2C is a schematic three-dimensional structure of depositing a thin copper layer over an epitaxial wafer according to an embodiment of the disclosure.
Fig. 2D is a schematic three-dimensional structure diagram of a thin copper layer outside a window region at a front facet and photoresist thereunder removed by a lift-off method with glue according to an embodiment of the present disclosure.
Fig. 2E is a schematic three-dimensional structure diagram of growing a first mask layer in the current injection region and a second mask layer in the non-current injection region according to the embodiment of the disclosure.
Fig. 2F is a schematic three-dimensional structure diagram of the N, P face electrodes after the first mask layer is etched away according to the embodiment of the disclosure.
Fig. 3 is a test plot of a spectrum of a quantum well active region P L before and after annealing for making a window region of a 915nm semiconductor laser chip according to an embodiment of the disclosure.
Fig. 4 is a test plot of the spectrum of a quantum well active region P L before and after annealing for making a 975nm semiconductor laser chip window region in accordance with an embodiment of the present disclosure.
[ notation ] to show
101-a substrate; 102-a buffer layer;
103-a lower confinement layer; 104-a lower waveguide layer;
105-quantum well active region; 106 — an upper waveguide layer;
107-upper confinement layer; 108-ohmic contact layer;
200-photoresist;
300-copper;
410-a first mask layer; 420-a second mask layer;
510-a P-side electrode; 520-N-face electrode.
Detailed Description
The method for manufacturing the semiconductor laser by utilizing the impurity induction hybrid technology adds the growth of copper and a dielectric film, and carries out rapid thermal annealing at high temperature without the technologies of secondary epitaxy, vacuum cleavage coating cavity surface passivation, vulcanization treatment and the like, so that the blue shift effect with considerable blue shift can be obtained, and the method has the advantages of simple process, high repeatability, short time consumption, low cost and contribution to mass production.
For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
The quantum well intermixing means that after epitaxial growth, dielectric films (different dielectric films have different functions, some can promote blue shift and some can inhibit blue shift) and masks (as protective films, blue shift can be inhibited) with blue shift promotion and inhibition functions are selectively grown on an epitaxial wafer, and then a rapid annealing process is carried out for a specific time at a certain temperature, so that the band gap of the quantum well material in a selected area of the epitaxial wafer is blue shifted to a certain degree, and the original band gap of the non-selected area is still kept unchanged. Its essence is the interdiffusion of the heterojunction component atoms caused by point defects inside the semiconductor.
Specifically, in the semiconductor laser, dielectric films (SiO with a certain thickness) for promoting blue shift can be respectively grown in a Window Region (Window Region) and a gain Region (Active Region) at the cavity surface by photolithography process2、SiO2-Cu、Cu、HfO2Etc.) and a mask (Si) for suppressing blue shift3N4、TiO2、SrF2、P-SiO2) And then through a rapid annealing process of quantum well intermixing, the quantum well material in the window region can be subjected to blue shift, and the band gap of the quantum well material in the gain region is kept unchanged.
The present disclosure employs Cu as the metal film that promotes blue shift, based on the following considerations: cu is a 3d transition metal with extremely high values in the AlGaAs material systemThe diffusion coefficient. After a rapid annealing process at a lower temperature, Cu atoms can diffuse into the quantum well and generate traction or resonance collision with In/Ga or In/Ga/Al In the well and barrier materials, so that the activation energy required by mutual diffusion is greatly reduced, and the mutual diffusion degree of the well and barrier material components is greatly enhanced. Thus, relative to SiO2、HfO2And the like, the sputtered Cu can play a considerable blue shift effect at lower temperature. On one hand, the reduction of annealing temperature and the reduction of annealing time are more beneficial to protecting the surface appearance and the crystal quality of the epitaxial wafer while ensuring the blue shift effect, so that the electro-optic characteristic of the epitaxial wafer is less damaged; on the other hand, because the epitaxial material has certain stability below 800 ℃, silicon dioxide, silicon nitride and the like are used as masks for inhibiting blue shift, and extra masks are not needed to protect regions which do not need blue shift at a lower annealing temperature, so that the manufacturing process of the laser chip is simplified, and the yield is improved.
In a first exemplary embodiment of the present disclosure, a method of fabricating a 915nm separation-limited asymmetric large optical cavity semiconductor laser using impurity-induced intermixing techniques is provided. Fig. 1 is a flow chart of a method of fabricating a semiconductor laser using impurity induced intermixing techniques in accordance with an embodiment of the present disclosure; fig. 2A to 2F are schematic views of three-dimensional structures corresponding to the semiconductor laser chip manufactured according to the embodiment of the present disclosure after the steps are performed. Referring to fig. 1 and 2A to 2F, a method of fabricating a semiconductor laser using impurity induced intermixing techniques, comprising:
step S102: epitaxially growing a buffer layer 102, a lower limiting layer 103, a lower waveguide layer 104, a quantum well active region 105, an upper waveguide layer 106, an upper limiting layer 107 and an ohmic contact layer 108 on a substrate 101 in sequence to form an epitaxial wafer;
in this embodiment, the substrate 101 is made of N-type gaas, and the doping concentration thereof is: 1*1018cm-3；
In this embodiment, the buffer layer 102 is made of N-type gaas with a doping concentration of 2 × 1018cm-3The thickness is 200 nm;
in this example, the followingThe confinement layer 103 is made of N-type AlGaAs with a doping concentration of 1 × 1018cm-3The thickness is 1.5 mu m;
in this embodiment, the lower waveguide layer 104 is made of aluminum gallium arsenide (AlGaAs) doped unintentionally and has a thickness of 700 nm;
the material of quantum well active region 105 may be one of the following materials: indium gallium arsenide/gallium arsenide, aluminum gallium indium arsenide/aluminum gallium arsenic, aluminum gallium indium arsenide/gallium arsenic phosphide, gallium indium phosphide/aluminum gallium indium phosphide, aluminum gallium indium arsenide/aluminum gallium indium arsenide; in this embodiment, the quantum well active region 105 is made of AlGaInAs/AlGaAs, and has a thickness of 7 nm;
in this embodiment, the upper waveguide layer 106 is made of aluminum gallium arsenide (AlGaAs) doped unintentionally and has a thickness of 400 nm;
the doping concentration of the unintentionally doped AlGaAs in the embodiment is less than 1 × 1016cm-3Generally 1 × 1015cm-3The order of (a) is not intentionally doped, which means that the doping concentration is generated autonomously in the material growth process, and is not achieved by means of ion implantation or other doping means, but the invention is not limited thereto, and other approaches are also satisfactory as long as the relevant doping concentration is satisfied;
in this embodiment, the upper confinement layer 107 is made of P-type AlGaAs with a doping concentration of 2 × 1018cm-3The thickness is 1.3 mu m;
in this embodiment, the material of the ohmic contact layer 108 is P-type gaas with a doping concentration of 1 × 1020cm-3The thickness is 200 nm;
note that the doping concentrations of the materials of the substrate 101, the buffer layer 102, the lower confinement layer 103, the lower waveguide layer 104, the upper waveguide layer 106, the upper confinement layer 107, and the ohmic contact layer 108, which are listed above, are used as an example for illustration, and are not limited to the above doping concentrations, and the materials and thicknesses to be selected are not limited thereto, and may be flexibly changed according to the experimental needs in an actual experiment.
Step S104: etching is carried out from the left side and the right side of the uppermost layer of the epitaxial wafer, the ohmic contact layer 108 and part of the upper limiting layer 107 are etched, the remaining upper limiting layer 107 in the middle and the ohmic contact layer 108 positioned on the upper limiting layer are current injection regions, and the exposed upper limiting layers 107 on the two sides are non-current injection regions;
the current injection area is determined according to the different quality of the needed light beam and the output power, and is etched by photoetching, the depth of the non-current injection area is between 200nm and 1500nm, and the width of the non-current injection area is between 5 mu m and 200 mu m; in this embodiment, the etching depth of the upper limiting layer 107 is 300nm, fig. 2A is a schematic diagram of an epitaxial structure for manufacturing a semiconductor laser chip according to an embodiment of the present disclosure and a three-dimensional structure after one-time photolithography, as shown in fig. 2A, the upper limiting layer 107 and the ohmic contact layer 108 thereon in the middle part left after etching are current injection regions; the exposed upper limiting layer 107 on both sides is a non-current injection region;
step S106: photoetching a window area at the front cavity surface in the strip-shaped current injection area, and depositing a layer of copper 300 on the window area at the front cavity surface;
this step can be divided into the following substeps:
sub-step S106A: photoetching a strip-shaped area with a certain width in the current injection area to form a window area at the front cavity surface, wherein the ohmic contact layer 108 is exposed out of the window area at the front cavity surface, and the rest areas are covered by the photoresist 200;
the strip-shaped area formed by photoetching is a window area at the front cavity surface, and the width of the strip-shaped area in the cavity length direction (namely the front and back direction) is between 5nm and 50 nm; in this embodiment, a 100 μm stripe region is photo-etched in the window region at the front facet, which has a width of 20nm in the cavity length direction; fig. 2B is a schematic diagram of a three-dimensional structure in which a strip-shaped region with a certain width is formed in a current injection region by photolithography to form a window region at a front cavity surface according to the embodiment of the present disclosure, as shown in fig. 2B, the photoresist 200 in the strip-shaped region with a certain width is removed by processes of spin coating, exposure, development and the like of photolithography to expose the ohmic contact layer 108, so that the window region at the front cavity surface is formed, and the rest regions are covered by the photoresist 200;
step S106B: depositing a layer of copper 300 on the whole epitaxial wafer, and removing a copper thin layer in the region outside a window region on the front cavity surface and the photoresist 200 below the copper thin layer;
the copper 300 deposited on the whole epitaxial wafer is high-purity thin copper with the thickness between 2nm and 20nm, and in the embodiment, the thickness of the copper 300 is 5 nm; the photoresist 200 is a negative photoresist; the mode of removing the copper thin layer in the area outside the window area at the front cavity surface and the photoresist 200 below the copper thin layer is a stripping method with photoresist; fig. 2C is a schematic three-dimensional structure of a thin copper layer deposited on the entire epitaxial wafer according to an embodiment of the disclosure, and as shown in fig. 2C, a layer of copper 300 is further deposited on the epitaxial wafer, and the deposition method may be a magnetron sputtering method, but is not limited thereto, and other conventional preparation techniques in the art may also be adopted; fig. 2D is a schematic three-dimensional structure diagram of the thin copper layer and the photoresist under the thin copper layer except the window region at the front cavity surface removed by the lift-off with glue method according to the embodiment of the present disclosure, where the meaning of the lift-off with glue is: the stripping of Cu and the photoresist are stripped together, and in the practical application process, the thin copper layer outside the window area at the front cavity surface and the photoresist below the thin copper layer can be removed in other modes, so that the method is not limited to the stripping method with the photoresist provided by the disclosure; as shown in fig. 2D, after the copper layer 300 and the photoresist 200 are stripped, the current injection region is composed of the copper layer located in the window region at the front cavity surface, the ohmic contact layer 108 located under the copper layer, and the upper limiting layer 107 located in the middle portion under the ohmic contact layer 108, and the non-current injection region is exposed;
step S108: growing a first mask layer 410 in the current injection region, growing a second mask layer 420 in the non-current injection region, annealing, and realizing quantum well mixing in the window region at the front cavity surface;
the first mask layer 410 and the second mask layer 420 are used as protective layers to inhibit quantum well intermixing, thereby inhibiting blue shift; the growth mode of the first mask layer 410 and the second mask layer 420 is Plasma Enhanced Chemical Vapor Deposition (PECVD), the material of the first mask layer 410 is silicon dioxide, the material of the second mask layer 420 is one selected from silicon dioxide and silicon nitride, and the thickness of the second mask layer is between 50nm and 500 nm; in this embodiment, the first mask layer 410 and the second mask layer 420 are made of silicon dioxide, and the thicknesses thereof are both 300 nm; fig. 2E shows a schematic three-dimensional structure of growing the first mask layer 410 in the current injection region and growing the second mask layer 420 in the non-current injection region;
it is to be noted that the dielectric film for suppressing quantum well intermixing includes, in addition to silicon dioxide and silicon nitride: titanium oxide TiO2And strontium fluoride SrF2And the like, are not limited to the materials exemplified in the present embodiment.
The annealing is realized by RTA rapid thermal annealing equipment, the annealing temperature is between 750 and 850 ℃, the annealing time is between 60 and 180 seconds, and the annealing time and the annealing temperature are determined according to the difference of epitaxial materials and the blue shift amount of the required quantum well active region; in this embodiment, according to the required amount of blue shift, the annealing parameters are determined as follows: the annealing temperature is 810 ℃, the annealing time is 60s, the annealing protective atmosphere is high-purity nitrogen, a clean gallium arsenide substrate is covered on the surface of the epitaxial wafer to serve as a cover plate, the polishing surface of the cover plate faces downwards and is completely attached to the epitaxial wafer, and therefore possible V-group elements are prevented from being separated out in the rapid thermal annealing process; in the annealing process, Cu atoms can diffuse into the quantum well and generate traction or resonance collision with In/Ga or In/Ga/Al In the well and barrier materials, so that the activation energy required by mutual diffusion is greatly reduced, and the mutual diffusion degree of the well and barrier material components is greatly enhanced.
Step S110: the first mask layer 410 is etched away by photolithography, and the second mask layer 420 is left to provide a current limiting effect;
step S112: sequentially manufacturing a P-surface electrode 510 and an N-surface electrode 520 to finish the manufacture of the semiconductor laser chip;
in this embodiment, the P-side electrode 510 is made of titanium/platinum/gold stacked in sequence; the N-face electrode 520 adopts gold/germanium/nickel which are sequentially laminated; the P-surface electrode 510 is manufactured in a magnetron sputtering mode, and the N-surface electrode 520 is manufactured in a vacuum evaporation mode; fig. 2F illustrates a schematic three-dimensional structure diagram of the first mask layer after the P-side electrode 510 and the N-side electrode 520 are etched away;
the method also comprises a common process, which comprises the following steps: the processes of polishing, thinning and polishing the N-side substrate 101, annealing the alloy, electroplating thick gold on the N-side, coating the cavity surface, and testing the chip cleavage and packaging are not repeated herein because the processes do not belong to the innovation point of the invention.
The 915nm separation limit asymmetric large optical cavity semiconductor laser prepared by the method is subjected to performance test, fig. 3 is a spectrum test graph of a quantum well active region P L spectrum before and after annealing of a chip window region of the 915nm semiconductor laser manufactured according to the embodiment of the disclosure, as shown in fig. 3, a spectrum peak of a window region quantum well active region P L spectrum before annealing is 894.3nm, a spectrum peak after annealing is 834.3nm, a blue shift amount after annealing is 99.72meV, and a blue shift effect is obvious.
In a second exemplary embodiment of the present disclosure, a method of fabricating a 975nm split-confined asymmetric large optical cavity semiconductor laser using impurity induced intermixing techniques of the present disclosure is provided.
Compared with the first embodiment, the present embodiment is different in the material and thickness of the lower waveguide layer 104, the quantum well active region 105 and the upper waveguide layer 106, the size of the window region etched at the front cavity surface in the subsequent preparation process is different, and the annealing process for performing high-temperature rapid thermal annealing is different; the following describes different parameters of this embodiment from those of the first embodiment, and other similar preparation methods and process parameters are not described herein again;
in this embodiment, the lower waveguide layer 104 is also made of aluminum gallium arsenide (AlGaAs) doped unintentionally and has a thickness of 900 nm;
in this embodiment, the material of the quantum well active region 105 is: indium gallium arsenide/aluminum gallium arsenide, the thickness of which is 9 nm;
in this embodiment, the upper waveguide layer 106 is also made of aluminum gallium arsenide (AlGaAs) doped unintentionally and has a thickness of 500 nm;
in the embodiment, a 100 μm strip-shaped region is photoetched in the window region at the front cavity surface, and the width of the strip-shaped region in the cavity length direction is also 20 nm;
in this embodiment, the annealing parameters are determined according to the required amount of blue shift as follows: the annealing temperature was 810 ℃ and the annealing time was 90 s.
The 975nm separation-limited asymmetric large optical cavity semiconductor laser prepared by the method is subjected to performance test, fig. 3 is a spectrum test chart of a P L spectrum of a quantum well active region before and after annealing of a chip window region of the 975nm semiconductor laser manufactured according to the embodiment of the disclosure, as shown in fig. 4, a spectrum peak of a P L spectrum of the quantum well active region of the window region before annealing is 955.9nm, a spectrum peak after annealing is 891.3nm, a blue shift amount after annealing is 94meV, and a blue shift effect is obvious.
It should be noted that the method for manufacturing the semiconductor laser by using the impurity-induced hybrid technology is not only suitable for manufacturing the semiconductor laser, but also applicable to scenes requiring different forbidden bandwidths, such as a multi-wavelength laser, a multi-wavelength photonic integrated emission chip, and the like, and has a wide application range.
In summary, the embodiments of the present disclosure provide a method for manufacturing a semiconductor laser by using an impurity-induced hybrid technology, in which Cu is used as a metal film for promoting blue shift, and silicon dioxide, silicon nitride, and the like are used as masks for suppressing blue shift, and a gain region can be masked at a lower temperature without an additional mask, so that a quantum well in the region can maintain a forbidden bandwidth after epitaxial growth, and a region covered with copper undergoes a certain amount of blue shift of a quantum well wavelength, so as to obtain a blue shift effect, and a blue shift effect with appreciable blue shift can be obtained without technologies such as secondary epitaxy, passivation of a vacuum cleavage coating film, and vulcanization processing, and the method is simple in process, high in repeatability, short in time consumption, low in cost, and beneficial for mass production; compared with other thermal annealing technologies with obvious blue shift amount only at the temperature of 900 ℃, the scheme disclosed by the invention can realize blue shift at the temperature of 750 ℃, and the adoption of the mask can effectively prevent the overflow of V-group elements such as arsenic and the like, thereby ensuring that the epitaxial chip still keeps high crystal quality after annealing.
It is also noted that the illustrations herein may provide examples of parameters that include particular values, but that these parameters need not be exactly equal to the corresponding values, but may be approximated to the corresponding values within acceptable error tolerances or design constraints. Directional phrases used in the embodiments, such as "upper", "lower", "front", "rear", "left", "right", etc., refer only to the direction of the attached drawings and are not intended to limit the scope of the present disclosure. In addition, unless steps are specifically described or must occur in sequence, the order of the steps is not limited to that listed above and may be changed or rearranged as desired by the desired design. The embodiments described above may be mixed and matched with each other or with other embodiments based on design and reliability considerations, i.e., technical features in different embodiments may be freely combined to form further embodiments.
Unless otherwise indicated, all numbers expressing quantities of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term "about". Accordingly, unless indicated to the contrary, the numerical parameters set forth in this specification and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by the present disclosure.
It should be noted that the above-mentioned embodiments illustrate rather than limit the disclosure, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
It should be noted that throughout the drawings, like elements are represented by like or similar reference numerals. In the foregoing description, some specific embodiments have been described for illustrative purposes only, and should not be construed as limiting the disclosure in any way, but merely as exemplifications of embodiments of the disclosure. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure. It should be noted that the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure.
The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.
Claims (7)
1. A method of fabricating a semiconductor laser using impurity induced intermixing, comprising:
preparing an epitaxial wafer; the preparation of the epitaxial wafer comprises the following steps: epitaxially growing a buffer layer (102), a lower limiting layer (103), a lower waveguide layer (104), a quantum well active region (105), an upper waveguide layer (106), an upper limiting layer (107) and an ohmic contact layer (108) on a substrate (101) in sequence to form an epitaxial wafer;
etching a current injection region and a non-current injection region on the epitaxial wafer, wherein the steps of: etching is carried out from the left side and the right side of the uppermost layer of the epitaxial wafer, the ohmic contact layer (108) and part of the upper limiting layer (107) are etched, the remaining upper limiting layer (107) in the middle and the ohmic contact layer (108) positioned on the upper limiting layer are current injection regions, and the exposed upper limiting layers (107) on the two sides are non-current injection regions;
photoetching a window area at the front cavity surface in the current injection area;
depositing a layer of copper (300) on the window region at the front facet as a metal film to promote blue-shifting; said depositing a layer of copper (300) over the window region at the front facet comprises: depositing a layer of copper (300) on the whole epitaxial wafer, and in the process of photoetching the window area at the front cavity surface in the current injection area, exposing the ohmic contact layer (108) except the window area at the front cavity surface, wherein the ohmic contact layer does not contain the photoresist (200), and the rest areas are covered by the photoresist (200); then after depositing copper (300), removing the copper thin layer and the photoresist (200) below the copper thin layer outside the window area at the front cavity surface;
growing a first mask layer (410) in the current injection region, covering the first mask layer on the copper (300), growing a second mask layer (420) in the non-current injection region, annealing, and realizing quantum well mixing in the window region at the front cavity surface;
etching away the first mask layer (410) by photolithography, leaving the second mask layer (420) to provide a current limiting effect; and
a P-face electrode (510) and an N-face electrode (520) are sequentially formed, and the semiconductor laser is completed.
2. The method of claim 1, wherein the first mask layer (410) and the second mask layer (420) are both dielectric films that inhibit quantum well intermixing.
3. The method of claim 2, wherein,
the growth mode of the first mask layer (410) and the second mask layer (420) is PECVD;
the first mask layer (410) is made of silicon dioxide;
the material of the second mask layer (420) is one of the following materials: silicon dioxide and silicon nitride;
the thickness of the first mask layer (410) and the thickness of the second mask layer (420) are both between 50nm and 500 nm.
4. The method according to claim 1, wherein the etching away of the ohmic contact layer (108) and the portion of the upper confinement layer (107) has a depth of between 200nm and 1500nm and a width of between 5 μm and 200 μm, depending on the desired beam quality and the magnitude of the output power.
5. The method of claim 1, wherein,
the mode of depositing the copper (300) on the epitaxial wafer is a magnetron sputtering method;
the width of the window area at the front cavity surface in the cavity length direction is between 5nm and 50 nm;
the copper (300) deposited on the epitaxial wafer is high-purity thin copper, and the thickness of the copper is between 2nm and 20 nm;
the photoresist (200) is a negative photoresist.
6. The method of any of claims 1 to 5, wherein the material of the quantum well active region (105) is one of the following materials: indium gallium arsenide/gallium arsenide, aluminum gallium indium arsenide/aluminum gallium arsenic, aluminum gallium indium arsenide/gallium arsenic phosphide, gallium indium phosphide/aluminum gallium indium phosphide or aluminum gallium indium arsenide/aluminum gallium indium arsenide.
7. The method of claim 6, wherein the annealing treatment is carried out using RTA rapid thermal annealing equipment, and the annealing temperature T satisfies: t is more than or equal to 750 ℃ and less than or equal to 850 ℃, and the annealing time T satisfies the following condition: t is more than or equal to 60s and less than or equal to 180s, and the annealing time and the annealing temperature depend on different materials of the epitaxial wafer and the blue shift amount of the required quantum well active region.
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| CN111971861B (en) * | 2018-08-31 | 2024-01-30 | 华为技术有限公司 | Optical integrated chip |
| CN112072469A (en) * | 2020-08-07 | 2020-12-11 | 西安理工大学 | Semiconductor laser based on quantum well mixed active region and preparation method |
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| CN112993063B (en) * | 2021-01-28 | 2022-08-19 | 湖北光安伦芯片有限公司 | Method for manufacturing ohmic contact electrode of optical communication chip |
| CN114122914A (en) * | 2021-11-11 | 2022-03-01 | 中国科学院半导体研究所 | Laser and preparation method thereof |
| CN115207776B (en) * | 2022-09-15 | 2022-12-13 | 苏州长光华芯光电技术股份有限公司 | Semiconductor epitaxial structure and growth method thereof |
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