CN109216538B - MRAM and manufacturing method thereof - Google Patents
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- CN109216538B CN109216538B CN201710526108.8A CN201710526108A CN109216538B CN 109216538 B CN109216538 B CN 109216538B CN 201710526108 A CN201710526108 A CN 201710526108A CN 109216538 B CN109216538 B CN 109216538B
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Abstract
The application provides an MRAM and a manufacturing method thereof. The manufacturing method comprises the following steps: step S1, a metal wire layer is arranged on the surface of the substrate; step S3, a dielectric layer is arranged on the surface of the metal wire layer far away from the substrate; step S4, forming a plurality of spaced through holes by adopting a dual damascene process, wherein the through holes comprise a first part and a second part, the depth of the second part is less than that of the first part, and the width of the second part is greater than that of the first part; step S5, filling a bottom electrode material in each through hole to form a bottom electrode, where a surface of the bottom electrode away from the substrate and a surface of the dielectric layer away from the substrate are on the same plane, and the bottom electrode material is a non-copper conductive material. The method avoids the two-step process of filling copper in the through hole and then arranging the bottom electrode on the copper, and avoids the problem that a smoother surface cannot be formed due to the lower hardness of the Cu because the Cu is not arranged.
Description
Technical Field
The present disclosure relates to the field of semiconductor memory, and more particularly, to an MRAM and a method for fabricating the same.
Background
Magnetic Random Access Memory (MRAM) is a novel nonvolatile Memory, and compared with other types of Memory at present, the MRAM has the advantages of high read/write speed, unlimited erasing/writing, easy compatibility with the semiconductor process at present, and the like. These advantages make MRAM the main development of new types of memories in the future.
The main functional unit in MRAM is MTJ cell, whose structure mainly includes a magnetic free layer/nonmagnetic oxide layer (MgO)/magnetic pinned layer. Under the drive of an external magnetic field or current and the like, the direction of the magnetic moment of the magnetic free layer is overturned, and the direction of the magnetic moment of the magnetic pinning layer are in a parallel state or an antiparallel state, so that the MRAM has high and low resistance states which can be respectively defined as a storage state '0' and '1', and the storage of information is realized.
In the preparation process of MRAM, the main functional unit MTJ cell has a total of dozens to twenty layers of different magnetic or non-magnetic thin films, wherein the thickness of the multilayer thin film is required to be less than 1nm or even a few angstroms. In order to ensure the continuity of the ultra-thin film growth in the MTJ, the planarization process of the bottom electrode becomes very important. In the current semiconductor process, because copper is difficult to etch and easy to oxidize during oxidation treatment, a damascene process is often used to form interconnects of copper material, according to which interconnect grooves and vias are formed in an insulating layer, copper is filled in the grooves and vias of the interconnects, so that the grooves form upper interconnects and the vias are connected to a lower interconnect or a substrate, and the above structure is planarized by a chemical mechanical polishing process. As shown in fig. 1, the bottom electrode 6' and the metal wiring layer 2' are electrically connected through a via hole 5' filled with metal Cu. In order to prevent Cu diffusion, a barrier layer 3 'is also provided on the bottom metal conductor layer 2', and the surface roughness of Cu is very important for obtaining good conductivity of MRAM. The surface roughness of Cu is usually selected to be reduced by Chemical Mechanical Polishing (CMP), but due to the low hardness of Cu metal, a sufficiently flat Cu surface cannot be obtained by CMP, which directly affects the surface flatness of the bottom electrode grown on Cu, and the arrangement of other structural layers in the subsequent MTJ device, and even the performance of the whole MRAM device.
In addition, in order to obtain the bottom electrode 6 'of the MTJ device with a sufficiently flat surface, the dielectric layer 4' needs to be removed by a CMP process so that a polishing end point stops on the bottom electrode (e.g., TaN). The selection ratio of the existing grinding liquid in the market is generally lower, and great challenges are brought to accurately stopping on the bottom electrode TaN in the polishing process.
Disclosure of Invention
The present application is directed to an MRAM and a method for fabricating the same, so as to solve the problem that a sufficiently flat bottom electrode cannot be obtained in the prior art.
In order to achieve the above object, according to an aspect of the present application, there is provided a method of fabricating an MRAM, the method including: step S1, providing a metal wire layer on the surface of the substrate, wherein the metal wire layer comprises a plurality of spaced metal wire portions; step S3, disposing a dielectric layer on the surface of the metal wire layer away from the substrate; step S4, forming a plurality of spaced vias by using a dual damascene process, the vias being formed in the dielectric layer and connected to the metal wire portions in a one-to-one correspondence, the vias including a first portion and a second portion, the first portion being close to the substrate, the second portion being in communication with the first portion, the second portion having a depth smaller than that of the first portion and a width greater than that of the first portion; step S5 is to fill each through hole with a bottom electrode material to form a bottom electrode, wherein a surface of the bottom electrode away from the substrate and a surface of the dielectric layer away from the substrate are on the same plane, and the bottom electrode material is a non-copper conductive material.
Further, the depth of the first portion is H, the width of the first portion is W, H: w < 1.
Further, between the step S1 and the step S3, the manufacturing method further includes: in step S2, a barrier layer is formed on a surface of the metal wiring layer away from the substrate, and the via hole is opened in the dielectric layer and the barrier layer.
Further, the step S5 includes: a step S51 of providing the bottom electrode material in each of the through holes; in step S52, the bottom electrode material outside the through hole is removed by chemical mechanical polishing, and the bottom electrode material in the through hole forms the bottom electrode.
Further, the step S52 is performed by using a polishing liquid, the polishing speed of the polishing liquid to the bottom electrode material is V1, the polishing speed of the polishing liquid to the dielectric layer is V2, the polishing speed of the polishing liquid to the dielectric layer is V1: v2> 50.
Further, the bottom electrode material is TaN.
Further, the material of the dielectric layer is selected from a low-K material and/or an ultra-low-K material.
Further, the material of the metal wire layer is Cu.
According to another aspect of the present application, there is provided an MRAM including: a substrate; a metal wire layer disposed on a surface of the substrate, the metal wire layer including a plurality of spaced metal wire portions; a dielectric layer disposed on a surface of the metal wire layer away from the substrate, the dielectric layer having a plurality of spaced through holes therein, the through holes being connected to the metal wire portions in a one-to-one correspondence, the through holes including a first portion and a second portion, the first portion being adjacent to the substrate, the second portion being in communication with the first portion, the second portion having a depth smaller than a depth of the first portion, and a width larger than a width of the first portion; and the bottom electrode comprises a bottom electrode material and is arranged in each through hole, the surface of the bottom electrode, which is far away from the substrate, is on the same plane with the surface of the dielectric layer, which is far away from the substrate, and the bottom electrode material is a non-copper conductive material.
Further, the depth of the first portion is H, the width of the first portion is W, H: w < 1.
Further, the MRAM may further include: and a barrier layer disposed between the metal wiring layer and the dielectric layer, wherein the via hole is opened in the barrier layer and the dielectric layer.
Further, the bottom electrode material is TaN.
By applying the technical scheme of the application, a plurality of spaced through holes are directly formed in the dielectric layer by adopting a dual damascene process, then bottom electrode materials are filled in the through holes, and a plurality of spaced bottom electrodes are further formed, so that the two-step process that copper is filled in the through holes firstly and then the bottom electrodes are arranged on the copper in the prior art is avoided, and the problem that a relatively flat surface cannot be formed due to the fact that the hardness of the Cu is lower is avoided because the Cu is not arranged.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 is a schematic diagram of a prior art MRAM fabrication process;
FIG. 2 is a schematic diagram illustrating a structure of a metal line layer, a barrier layer and a dielectric layer on a substrate according to an embodiment of the present application;
FIG. 3 shows a schematic view of the structure after providing vias in the dielectric layer and the barrier layer;
FIG. 4 shows a partial structural schematic of FIG. 3;
FIG. 5 is a schematic diagram showing the structure after filling the via hole with a bottom electrode material; and
fig. 6 shows a schematic diagram of the structure formed after removing the bottom electrode material outside the via hole.
Wherein the figures include the following reference numerals:
2', a metal wire layer; 3', a barrier layer; 4', a dielectric layer; 5', a through hole; 6', a bottom electrode;
1. a substrate; 2. a metal wire layer; 3. a barrier layer; 4. a dielectric layer; 5. a through hole; 6. a bottom electrode; 51. a first portion; 52. a second portion; 06. a bottom electrode material.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
As described in the background of the invention, in the prior art, due to the presence of the filling metal such as copper in the via hole, the MRAM cannot obtain a sufficiently flat surface, and thus the performance of the MRAM is affected.
In an exemplary embodiment of the present application, a method for fabricating an MRAM is provided, the method comprising: step S1, as shown in fig. 2, providing a metal wire layer 2 on the surface of the substrate 1, wherein the metal wire layer 2 comprises a plurality of spaced metal wire portions; step S3, disposing a dielectric layer 4 on a surface of the metal wire layer 2 away from the substrate 1, as shown in fig. 2; step S4, as shown in fig. 3, forming a plurality of spaced vias 5 by using a dual damascene process, wherein the vias 5 are opened in the dielectric layer 4, the vias 5 are connected to the metal wire portions in a one-to-one correspondence manner, as shown in fig. 4, the vias 5 include a first portion 51 and a second portion 52, the first portion 51 is close to the substrate 1, the second portion 52 is communicated with the first portion 51, a depth of the second portion 52 is smaller than a depth of the first portion 51, and a width of the second portion 52 is larger than a width of the first portion 51; in step S5, a bottom electrode material 06 is filled in each of the through holes 5 to form a bottom electrode 6 shown in fig. 6, a surface of the bottom electrode 6 away from the substrate 1 and a surface of the dielectric layer 4 away from the substrate 1 are on the same plane, and the bottom electrode material 06 is a non-copper conductive material.
The dual damascene process is a dual damascene process in a common semiconductor process, also called a dual damascene process, and does not include a process of depositing a bottom electrode material, and the process includes forming a through hole 5 in one or more material layers, where the through hole 5 includes two portions with different apertures and the two portions have different depths and different widths, that is, the dual damascene process includes forming a through hole 5 in one or more material layers, where the through hole includes two portions communicating with each other and having different depths and different widths.
In the manufacturing method of the application, a plurality of spaced through holes 5 are directly formed in the dielectric layer 4 by adopting a dual damascene process, then the bottom electrode material 06 is filled in each through hole 5, and further a plurality of spaced bottom electrodes 6 are formed, so that the two-step process that copper is filled in the through holes 5 firstly and then the bottom electrodes 6 are arranged on the copper in the prior art is avoided, and the problem that a relatively flat surface cannot be formed due to the fact that the hardness of the Cu is low is avoided due to the fact that the Cu is not arranged.
In order to further enable the bottom electrode material 06 to be filled in the first portion 51 more efficiently and quickly, so as to ensure that the first portion 51 is filled with the bottom electrode material 06, thereby ensuring good conductivity of the MRAM, in an embodiment of the present application, as shown in fig. 4, the depth of the first portion 51 is H, the width of the first portion 51 is W, H: w < 1.
In another embodiment of the present application, between the step S1 and the step S3, the manufacturing method further includes: in step S2, a barrier layer 3 is formed on the surface of the metal wiring layer 2 away from the substrate 1, and the via hole 5 is opened in the dielectric layer 4 and the barrier layer 3. The barrier layer 3 prevents the conductive material in the via 5 from diffusing into the dielectric layer 4, further ensuring good performance of the MRAM.
The metal wire layer 2 in the present application is formed by using a damascene process, and the metal wire layer 2, the barrier layer 3, the dielectric layer 4 and the bottom electrode material 06 in the present application may be formed by using any suitable method in the prior art, for example, the dielectric layer 4 may be formed by using a chemical vapor deposition method or the like.
The barrier layer 3 may be formed of any material of the barrier layer 3 in the prior art, such as N-BLOK/ndc (sinc), and a person skilled in the art can select a suitable material to form the barrier layer 3 according to practical situations. This layer may be deposited by CVD or the like.
In order to form the flatter bottom electrode 6, in an embodiment of the present application, the step S5 includes: step S51, as shown in fig. 5, providing the bottom electrode material 06 in each of the through holes 5; in step S52, the bottom electrode material 06 outside the through hole 5 is removed by chemical mechanical polishing, and the bottom electrode material 06 in the through hole 5 is formed into the bottom electrode 6 as shown in fig. 6.
In another embodiment of the present application, the step S52 is performed by using a polishing liquid, the polishing rate of the polishing liquid to the bottom electrode material 06 is V1, the polishing rate of the polishing liquid to the dielectric layer 4 is V2, V1: v2> 50. This enables a better control of the grinding process so that it stops exactly on the dielectric layer 4, and a more even surface is obtained.
In order to select a polishing slurry with a higher selectivity ratio, better control the polishing process of the bottom electrode material 06, and accurately stop the polishing endpoint on the dielectric layer 4, thereby ensuring the uniformity of the MRAM and simultaneously ensuring the conductivity of the bottom electrode 6, in an embodiment of the present application, the bottom electrode material 06 is TaN, and in the prior art, the ratio of the polishing rate of the polishing slurry to TaN to the polishing rate of the polishing slurry to the dielectric layer 4 may reach more than 100.
The material of the dielectric layer 4 in the present application may be any material with good insulating property and without affecting the operation of MRAM in the prior art, and those skilled in the art can select a suitable material to form the dielectric layer 4 according to practical situations.
In order to further reduce the resistance of the MRAM and thus the power consumption of the MRAM, in an embodiment of the present application, the material of the dielectric layer 4 is selected from a low K material and/or an ultra low K material. Such as a silicon nitride compound or a silicon oxynitride compound.
In another embodiment of the present application, the material of the metal wire layer 2 is Cu. The resistance of Cu is low, which can significantly reduce the RC delay effect.
Of course, the material of the metal wire layer 2 of the present application is not limited to Cu, and those skilled in the art can select other suitable conductive materials to form the brief wire layer according to practical situations.
In another embodiment of the present application, the manufacturing method further includes: and a step of providing a structure layer other than the bottom electrode 6 in the MTJ device on the surface of the bottom electrode 6. Specifically, other structural layers include a free layer, a reference layer, an insulating barrier layer, a top electrode, and the like.
The substrate 1 in this application comprises a base and all necessary structures and devices of the previous process on the base, including for example CMOS and the like.
In another exemplary embodiment of the present application, an MRAM is provided, as shown in fig. 6, the MRAM includes a substrate 1, a metal line layer 2, a dielectric layer 4, and a bottom electrode 6, the metal line layer 2 is disposed on a surface of the substrate 1, and the metal line layer 2 includes a plurality of spaced metal line portions; a dielectric layer 4 disposed on a surface of the metal wiring layer 2 away from the substrate 1, the dielectric layer 4 having a plurality of spaced through holes 5 formed therein, the through holes 5 being connected to the metal wiring portions in a one-to-one correspondence, the through holes 5 including a first portion 51 and a second portion 52, the first portion 51 being adjacent to the substrate 1, the second portion 52 being in communication with the first portion 51, the second portion 52 having a depth smaller than that of the first portion 51, and the second portion 52 having a width larger than that of the first portion 51; a bottom electrode 6 is provided in each of the through holes 5, the bottom electrode is formed of a bottom electrode material 06, a surface of the bottom electrode 6 remote from the substrate 1 and a surface of the dielectric layer 4 remote from the substrate 1 are on the same plane, and the bottom electrode material 06 is a conductive material other than copper.
In the MRAM, the through hole 5 is filled with a non-Cu conductive material to form the bottom electrode 6, where the bottom electrode 6 is actually equivalent to the Cu portion connecting the metal wire layer 2 and the bottom electrode 6 in the prior art, the MRAM has a simple manufacturing process, and avoids a complex process of forming the Cu portion and then forming the bottom electrode 6 in the prior art, and because the through hole 5 is not filled with Cu, the problem that a relatively flat surface cannot be formed due to relatively low hardness of Cu is avoided, so that the MRAM is relatively flat, has relatively good uniformity, and has relatively good performance.
In order to further enable the bottom electrode material 06 to be filled in the first portion 51 more efficiently and quickly, so as to ensure that the first portion 51 is filled with the bottom electrode material 06, thereby ensuring good conductivity of the MRAM, in an embodiment of the present application, as shown in fig. 4, the depth of the first portion 51 is H, the width of the first portion 51 is W, H: w < 1.
In another embodiment of the present invention, as shown in fig. 2 and 6, the MRAM further includes a barrier layer 3, the barrier layer 3 is disposed between the metal line layer 2 and the dielectric layer 4, and the via 5 is opened in the barrier layer 3 and the dielectric layer 4. The barrier layer 3 prevents the conductive material in the via 5 from diffusing into the dielectric layer 4, further ensuring good performance of the MRAM.
In order to select a polishing slurry with a higher selection ratio, better control the polishing process of the bottom electrode material, and accurately stop the polishing endpoint on the dielectric layer, thereby ensuring the uniformity of the MRAM and simultaneously ensuring the conductivity of the bottom electrode, in an embodiment of the present application, the bottom electrode material is TaN, and in the prior art, the ratio of the polishing rate of the polishing slurry to TaN to the polishing rate of the polishing slurry to the dielectric layer can reach more than 100.
The material of the bottom electrode in the present application is not limited to TaN as described above, and may be any other non-copper conductive material in the prior art, for example, TiN, Ta, Ti, or a combination thereof. One skilled in the art can select suitable materials to form the bottom electrode according to practical situations.
The material of the dielectric layer in the present application may be any material in the prior art that has good insulating properties and does not affect the operation of the MRAM, and those skilled in the art can select a suitable material to form the dielectric layer 4 according to practical situations.
In order to further reduce the resistance of the MRAM and thus the power consumption of the MRAM, in one embodiment of the present application, the material of the dielectric layer is selected from a low K material and/or an ultra low K material. Such as fluorine-doped oxide (SiOF), carbon-doped (hydro) oxide (SiOC/SiOCH), and low-K dielectric organic polymers.
In another embodiment of the present application, the material of the metal wire layer is Cu. The lower resistance of Cu can significantly reduce the RC delay effect.
Of course, the material of the metal wire layer of the present application is not limited to Cu, and those skilled in the art can select other suitable conductive materials to form the brief wire layer according to practical situations.
In order to make the technical solutions of the present application more clearly understood by those skilled in the art, the technical solutions of the present application will be described below with reference to specific embodiments.
Examples
The manufacturing method of the MRAM comprises the following steps:
preparing a substrate 1 comprising a base and a structure prepared by the previous process on the base;
forming a metal wire layer 2 on the surface of the substrate 1 by adopting a damascene process, wherein the metal wire layer 2 comprises a plurality of spaced metal wire parts as shown in fig. 2;
NDC is deposited on the surface of each metal wire part far away from the substrate 1 to form a barrier layer 3;
forming SiO on the barrier layer 3 by PECVD using TEOS2A layer forming the dielectric layer 4 shown in fig. 3;
forming via hole 5 including first portion 51 and second portion 52 by using dual damascene process, as shown in fig. 4, the first portion 51 is close to the substrate 1, the second portion 52 is communicated with the first portion 51, and the depth of the first portion 51 is 
The depth of the second portion 52 is
And the width of the first portion 51 is
The width of the second portion 52 is
As shown in fig. 5, the via hole 5 is filled with metal TaN, and the surface of the structure is planarized by chemical mechanical polishing, so as to form a bottom electrode 6 shown in fig. 6, wherein the surface of the bottom electrode 6 away from the substrate 1 and the surface of the dielectric layer 4 away from the substrate 1 are on the same plane. The polishing rate of the bottom electrode material 06 by the polishing liquid used in the chemical mechanical polishing method was V1, and the polishing rate of the dielectric layer 4 by the polishing liquid was V2, V1: v2 is 100.
The manufacturing method can avoid the problem of uneven surface caused by filling copper, and the grinding of the final bottom electrode material can be accurately stopped on the dielectric layer through the selection of the bottom electrode material and the selection of the grinding liquid, so that the formed MRAM not only has a flat surface, but also has better uniformity, and the MRAM is ensured to have better performance.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) in the manufacturing method, a plurality of spaced through holes are directly formed in the dielectric layer by adopting a dual damascene process, then the through holes are filled with the bottom electrode material, and further a plurality of spaced bottom electrodes are formed, so that the problem that a smoother surface cannot be formed due to the fact that the hardness of Cu is lower due to the fact that the copper is not arranged in the two-step process that the through holes are filled with the copper first and then the bottom electrodes are arranged on the copper in the prior art is solved. The polishing method ingeniously changes 'the polishing endpoint is controlled on the bottom electrode material such as TaN by grinding off the dielectric layer in the chemical mechanical polishing process of the existing bottom electrode' into 'the polishing endpoint is controlled on the dielectric layer by grinding off the bottom electrode material' so as to realize the polishing by utilizing the existing grinding fluid with the large selection ratio of TaN to TEOS on the market.
2) In the MRAM of the application, fill non-Cu conducting material in the through-hole, form the bottom electrode, bottom electrode here is actually equivalent to the Cu part and the bottom electrode of connecting metal wire layer 2 and bottom electrode among the prior art, the preparation simple process of this MRAM, the earlier Cu part that forms among the prior art has been avoided, then form the complicated technology of bottom electrode, and because not filling Cu in the through-hole, avoided leading to the problem that can not form more smooth surface because Cu's hardness is lower, and then make this MRAM more level and smooth, the homogeneity is better, and the performance is better.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A method for fabricating an MRAM, the method comprising:
step S1, arranging a metal wire layer on the surface of the substrate, wherein the metal wire layer comprises a plurality of spaced metal wire parts;
step S3, a dielectric layer is arranged on the surface of the metal wire layer far away from the substrate;
Step S4, forming a plurality of spaced through holes by using a dual damascene process, wherein the through holes are opened in the dielectric layer, the through holes are connected with the metal wire portions in a one-to-one correspondence manner, each through hole comprises a first portion and a second portion, the first portion is close to the substrate, the second portion is communicated with the first portion, the depth of the second portion is smaller than that of the first portion, and the width of the second portion is larger than that of the first portion; and
step S5, filling a bottom electrode material in each through hole to form a bottom electrode, wherein a surface of the bottom electrode away from the substrate and a surface of the dielectric layer away from the substrate are on the same plane, the bottom electrode material is a non-copper conductive material,
the depth of the first portion is H, the width of the first portion is W, H: w < 1.
2. The method of manufacturing of claim 1, wherein between the step S1 and the step S3, the method of manufacturing further comprises:
step S2, a barrier layer is disposed on the surface of the metal wire layer away from the substrate, and the via hole is opened in the dielectric layer and the barrier layer.
3. The method of manufacturing according to claim 1, wherein the step S5 includes:
step S51, disposing the bottom electrode material in each of the through holes; and
and step S52, removing the bottom electrode material outside the through hole by adopting a chemical mechanical polishing method, wherein the bottom electrode material in the through hole forms the bottom electrode.
4. The method according to claim 3, wherein the step S52 is performed by using a polishing slurry, the polishing rate of the polishing slurry on the bottom electrode material is V1, the polishing rate of the polishing slurry on the dielectric layer is V2, V1: v2> 50.
5. The method of claim 1, wherein the bottom electrode material is TaN.
6. The method of claim 1, wherein the dielectric layer is made of a material selected from a low-K material and an ultra-low-K material.
7. The method according to claim 1, wherein the metal wire layer is made of Cu.
8. An MRAM, comprising:
a substrate (1);
a metal wire layer (2) arranged on the surface of the substrate (1), wherein the metal wire layer (2) comprises a plurality of spaced metal wire parts;
A dielectric layer (4) disposed on a surface of the metal wire layer (2) far away from the substrate (1), wherein a plurality of spaced through holes (5) are formed in the dielectric layer (4), the through holes (5) are connected with the metal wire portions in a one-to-one correspondence manner, each through hole (5) comprises a first portion (51) and a second portion (52), the first portion (51) is close to the substrate (1), the second portion (52) is communicated with the first portion (51), the depth of the second portion (52) is smaller than that of the first portion (51), and the width of the second portion (52) is larger than that of the first portion (51); and
a bottom electrode (6) comprising a bottom electrode material (06) disposed in each of the through holes (5), wherein a surface of the bottom electrode (6) away from the substrate (1) and a surface of the dielectric layer (4) away from the substrate (1) are on the same plane, the bottom electrode material (06) is a non-copper conductive material,
the depth of the first portion (51) is H, the width of the first portion (51) is W, H: w < 1.
9. The MRAM of claim 8, further comprising:
And the barrier layer (3) is arranged between the metal wire layer (2) and the dielectric layer (4), and the through hole (5) is formed in the barrier layer (3) and the dielectric layer (4).
10. The MRAM of claim 8, wherein the bottom electrode material (06) is TaN.
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| CN106298831A (en) * | 2015-06-25 | 2017-01-04 | 台湾积体电路制造股份有限公司 | The technology connected for MRAM MTJ top electrodes |
| CN106409814A (en) * | 2015-07-28 | 2017-02-15 | 台湾积体电路制造股份有限公司 | Dummy bottom electrode in interconnect to reduce cmp dishing |
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| CN111081872A (en) * | 2019-12-30 | 2020-04-28 | 浙江省北大信息技术高等研究院 | Resistive random access memory and manufacturing method thereof |
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| US9614143B2 (en) * | 2015-06-09 | 2017-04-04 | Qualcomm Incorporated | De-integrated trench formation for advanced MRAM integration |
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| CN102376875A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Forming method of magnetoresistive memory |
| CN106298831A (en) * | 2015-06-25 | 2017-01-04 | 台湾积体电路制造股份有限公司 | The technology connected for MRAM MTJ top electrodes |
| CN106409814A (en) * | 2015-07-28 | 2017-02-15 | 台湾积体电路制造股份有限公司 | Dummy bottom electrode in interconnect to reduce cmp dishing |
| CN108735895A (en) * | 2017-04-14 | 2018-11-02 | 上海磁宇信息科技有限公司 | Magnetic RAM hearth electrode contact and forming method thereof |
| CN111081872A (en) * | 2019-12-30 | 2020-04-28 | 浙江省北大信息技术高等研究院 | Resistive random access memory and manufacturing method thereof |
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