CN109216285B - Display panel - Google Patents
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- CN109216285B CN109216285B CN201710541668.0A CN201710541668A CN109216285B CN 109216285 B CN109216285 B CN 109216285B CN 201710541668 A CN201710541668 A CN 201710541668A CN 109216285 B CN109216285 B CN 109216285B
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- 239000000758 substrate Substances 0.000 claims abstract description 89
- 230000002093 peripheral effect Effects 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims description 47
- 239000011368 organic material Substances 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 3
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 3
- 239000010408 film Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
- Led Device Packages (AREA)
Abstract
The invention provides a display panel, which comprises a substrate, a buffer insulating layer, a plurality of connecting pads and a plurality of light emitting diodes. The substrate is provided with a display area and a peripheral area adjacent to the display area. The buffer insulating layer is disposed on the substrate. The Young's modulus of the buffer insulating layer is less than 10 GPa. The pad is located on the buffer insulating layer and is configured in the display area of the substrate. The light emitting diode is electrically connected to the pad and is bonded to the display region of the substrate through the pad. The buffer insulating layer is positioned between the light emitting diode and the substrate. The orthographic projection of the light-emitting diode on the substrate at least partially overlaps the orthographic projection of the buffer insulating layer on the substrate.
Description
Technical Field
The present invention relates to a display device, and more particularly, to a display panel.
Background
Generally, a light emitting chip is composed of an epitaxial structure, an N-type electrode and a P-type electrode, wherein the N-type electrode and the P-type electrode are respectively in contact with an N-type semiconductor layer and a P-type semiconductor layer. In order to increase the applications of the light emitting chip, the manufactured light emitting chip is usually subjected to metal bonding by heating, so that the light emitting chip is fixed on a circuit substrate to form a light emitting module or a display module. Since the thermal expansion coefficient of the materials between the light emitting chip and the circuit substrate are mismatched (mismatch), and only the inorganic material (such as SiO2 or SiN) is used as the insulating layer between the light emitting chip and the circuit substrate, it is unable to provide buffer during bonding, and the bonding yield is low, thereby reducing the structural reliability of the product.
Disclosure of Invention
The invention provides a display panel with better structural reliability.
The display panel of the invention comprises a substrate, a buffer insulating layer, a plurality of connecting pads and a plurality of light emitting diodes. The substrate is provided with a display area and a peripheral area adjacent to the display area. The buffer insulating layer is disposed on the substrate. The Young's modulus of the buffer insulating layer is less than 10 GPa. The pad is located on the buffer insulating layer and is configured in the display area of the substrate. The light emitting diode is electrically connected to the pad and is bonded to the display region of the substrate through the pad. The buffer insulating layer is positioned between the light emitting diode and the substrate. The orthographic projection superposition of the light-emitting diode on the substrate is at least partially overlapped with the orthographic projection of the buffer insulating layer on the substrate.
In an embodiment of the invention, an overlapping area of an orthographic projection of each of the light emitting diodes and the buffer insulating layer on the substrate is between 50% and 100% of an area of the orthographic projection of the light emitting diode on the substrate.
In an embodiment of the invention, each of the light emitting diodes is a horizontal light emitting diode.
In an embodiment of the invention, each of the light emitting diodes includes a first type semiconductor layer, a second type semiconductor layer, an active layer, an insulating layer, a first type electrode and a second type electrode. The active layer is located between the first type semiconductor layer and the second type semiconductor layer. The first type semiconductor layer is positioned between the active layer and the buffer insulating layer. The insulating layer is located between the first type semiconductor and the substrate and has a first contact opening and a second contact opening. The first type electrode extends from one surface of the insulating layer to the first contact opening and is electrically connected with the first type semiconductor layer. The second type electrode extends from the surface of the insulating layer to the second contact opening and is electrically connected with the second type semiconductor layer.
In an embodiment of the invention, each of the light emitting diodes further includes a blind via sequentially passing through the first type semiconductor layer, the active layer and the second type semiconductor layer. The second contact opening of the insulating layer is also arranged in the blind hole.
In an embodiment of the invention, the display panel further includes: a first electrode layer and a second electrode layer. The first electrode layer is disposed on an upper surface of the substrate. The second electrode layer is disposed on the first electrode layer and the buffer insulating layer, wherein the buffer insulating layer has a plurality of first openings. Part of the second electrode layer extends into the first opening and is electrically connected with the first electrode layer. The light emitting diode is electrically connected with the second electrode layer through the connecting pad.
In an embodiment of the invention, the first electrode layer includes a plurality of first-type electrode lines separated from each other. The second electrode layer comprises a plurality of connecting parts and a plurality of second type electrode wires which are separated from each other. The connecting parts are electrically connected with the first type electrodes of the light-emitting diodes, the second type electrode wires are electrically connected with the second type electrodes of the light-emitting diodes, and the connecting parts extend into the first openings of the buffer insulating layer and are electrically connected with the first electrode layers.
In an embodiment of the invention, the display panel further includes: an inorganic insulating layer disposed on the upper surface of the substrate and between the buffer insulating layer and the substrate. The inorganic insulating layer covers the upper surface and the first electrode layer and is provided with a plurality of second openings. The second opening communicates with the first opening of the buffer insulating layer. Part of the second electrode layer extends and is arranged in the first opening and the second opening and is electrically connected with the first electrode layer.
In an embodiment of the invention, the buffer insulating layer is a patterned film layer. The pattern of the buffer insulating layer is substantially the same as the pattern of the second electrode layer.
In an embodiment of the invention, the display panel further includes: an inorganic insulating layer disposed between the second electrode layer and the buffer insulating layer. The inorganic insulating layer has a plurality of second openings communicating with the first openings of the buffer insulating layer. Part of the second electrode layer extends and is arranged in the second opening and is electrically connected with the first electrode layer.
In an embodiment of the invention, each of the light emitting diodes is a vertical light emitting diode.
In an embodiment of the invention, the display panel further includes: the plurality of first electrode lines are arranged on the buffer insulating layer and are separated from each other. The first electrode wires are respectively positioned between the connecting pads and the buffer insulating layer, and the light emitting diodes are respectively connected to the first electrode wires through the connecting pads.
In an embodiment of the invention, the display panel further includes: the plurality of second electrode wires are respectively configured on the light emitting diodes. The light emitting diodes are respectively positioned between the second electrodes and the first electrodes.
In an embodiment of the invention, a thickness of the buffer insulating layer is between 3 micrometers and 5 micrometers.
In an embodiment of the invention, a material of the buffer insulating layer is an organic material.
In an embodiment of the invention, the young's modulus of the buffer insulating layer is between 2.9GPa and 3.6 GPa.
In an embodiment of the invention, a residual stress (residual stress) of the buffer insulating layer is 25MPa to 45 MPa.
In an embodiment of the invention, an elongation at break (elongation at break) of the buffer insulating layer is between 5% and 10%.
In an embodiment of the invention, the substrate includes a sapphire substrate, a glass substrate, a Thin Film Transistor (TFT) substrate, a Submount, a Complementary Metal-Oxide-Semiconductor (CMOS) circuit substrate, or a Liquid Crystal On Silicon (LCOS) substrate.
In an embodiment of the invention, a thickness of each of the light emitting diodes is between 5 micrometers and 6 micrometers, and a thickness of each of the pads is between 0.1 micrometer and 10 micrometers.
Based on the above, since the display panel of the invention has the buffer insulating layer, and the young modulus of the buffer insulating layer is less than 10GPa, when the light emitting diode is electrically connected to the pad and is bonded to the substrate through the pad, the buffer insulating layer can absorb the stress generated during bonding, so as to improve the bonding yield, and further increase the structural reliability of the display panel of the invention.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A is a schematic top view of a display panel according to an embodiment of the invention.
FIG. 1B is a schematic cross-sectional view taken along line A-A' of FIG. 1A.
Fig. 1C is a schematic partial cross-sectional view of a display panel according to another embodiment of the invention.
Fig. 1D is a partial cross-sectional view of a display panel according to another embodiment of the invention.
Fig. 2A to 2E are schematic cross-sectional views illustrating a manufacturing method of the display panel of fig. 1A.
Fig. 3 is a schematic partial cross-sectional view of a display panel according to another embodiment of the invention.
Fig. 4 is a schematic partial cross-sectional view of a display panel according to another embodiment of the invention.
Fig. 5 is a partial cross-sectional view of a display panel according to another embodiment of the invention.
Description of the symbols
100 a: display panel
110: substrate
116: upper surface of
120 a: buffer insulating layer
122 a: first opening
130a1, 130a 2: connecting pad
140 a: light emitting diode
141 a: first type electrode
142 a: first type semiconductor layer
143 a: second type electrode
144 a: active layer
146 a: second type semiconductor layer
148 a: insulating layer
148a 1: first contact opening
148a 2: second contact opening
148a 3: surface of
150 a: first type electrode wire
160 a: second electrode wire
160a 1: connecting part
160a 2: second type electrode wire
T1, T2, T3: thickness of
Detailed Description
Fig. 1A is a schematic top view of a display panel according to an embodiment of the invention. FIG. 1B is a schematic cross-sectional view taken along line A-A' of FIG. 1A. Referring to fig. 1A and fig. 1B, in the present embodiment, the display panel 100a includes a substrate 110, a buffer insulating layer 120a, a plurality of pads 130a1, 130a2, and a plurality of light emitting diodes 140 a. The substrate 110 has a display area 112 and a peripheral area 114 adjacent to the display area 112. The pads 130a1, 130a2 and the led 140a are disposed in the display region 112, and the led 140a is electrically connected to the substrate 110 through the pads 130a1 and 130a 2. In the present embodiment, the leds 140a have a plurality of colors, and are arranged in a pixel array in the display area 112, and then control light emission and display images via a driving circuit (not shown) or an external IC (not shown). The buffer insulating layer 120a is located between the light emitting diode 140a and the substrate 110 and Young's modulus (Young's modulus) of the buffer insulating layer 120a is less than 10 GPa. The orthographic projection of the light emitting diode 140a on the substrate 110 is at least partially overlapped with the orthographic projection of the buffer insulating layer 120a on the substrate 110.
In detail, the substrate 110 of the present embodiment may be, for example, a substrate with a wireless design, such as a sapphire substrate or a glass substrate, and the passive driving external IC circuit is used to control the light emitting diodes 140 a; alternatively, the light emitting diode 140a may be controlled by an active driving IC circuit, such as a Thin Film Transistor (TFT) substrate, a Submount (Submount), a Complementary Metal-Oxide-Semiconductor (CMOS) circuit substrate, a Liquid Crystal On Silicon (LCOS) substrate, or other suitable driving circuit substrate; of course, in various embodiments, only a fixed display image with a single color light emission, an illumination device, and the like may be used, and the invention is not limited thereto.
In particular, the material of the buffer insulating layer 120a of the present embodiment is an organic material, such as photoresist, Benzocyclobutene (BCB), Polyimide (PI), an organic glue, and the like, wherein the thickness T1 of the buffer insulating layer 120a is between 3 micrometers and 5 micrometers, the residual stress (residual stress) of the buffer insulating layer 120a is between 25MPa and 45MPa, such as 34MPa, and the elongation at break (elongation at break) of the buffer insulating layer 120a is between 5% and 10%. Preferably, the Young's modulus of the buffer insulating layer 120a is between 2.9GPa and 3.6 GPa. In this way, the buffer insulating layer 120a can provide a stress buffering effect between two components with different thermal expansion degrees, such as the light emitting diode 140a and the substrate 110.
Referring to fig. 1B, in the present embodiment, the light emitting diodes 140a are implemented as horizontal light emitting diodes, wherein each light emitting diode 140a includes a first type semiconductor layer 142a, an active layer 144a, a second type semiconductor layer 146a, an insulating layer 148a, a first type electrode 141a and a second type electrode 143 a. The active layer 144a is disposed between the first type semiconductor layer 142a and the second type semiconductor layer 146 a. The first type semiconductor layer 142a is located between the active layer 144a and the buffer insulating layer 120 a. The insulating layer 148a is disposed on the first type semiconductor 142a and has a first contact opening 148a1 and a second contact opening 148a 2. The first-type electrode 141a extends from a surface 148a3 of the insulating layer 148a into the first contact opening 148a1 and is electrically connected to the first-type semiconductor layer 142 a. The second-type electrode 143a extends from the surface 148a3 of the insulating layer 148a into the second contact opening 148a2 to electrically connect to the second-type semiconductor layer 146a, and the insulating layer 148a electrically insulates the second-type electrode 143a from the first-type semiconductor layer 142a and the active layer 144 a.
Furthermore, the pads 130a1 and 130a2 of the present embodiment are separated from each other, wherein the first type electrode 141a of the led 140a is electrically connected to the pad 130a1, and the second type electrode 143a of the led 140a is electrically connected to the pad 130a2, so that the led 140a is bonded to the substrate 110. In other words, the led 140a is flip-chip bonded to the substrate 110. Here, the thickness T2 of each led 140a is, for example, between 5 microns and 6 microns, and the thickness T3 of each pad 130a1 (or pad 130a2) is, for example, between 0.1 microns and 10 microns.
In addition, referring to fig. 1A and fig. 1B, the display panel 100a of the present embodiment further includes a first electrode layer 150 and a second electrode layer 160, wherein the first electrode layer 150 is disposed on an upper surface 116 of the substrate 110, the buffer insulating layer 120a is disposed on the first electrode layer 150, and the second electrode layer 160 is disposed on the buffer insulating layer 120 a. The first electrode layer 150 includes a plurality of first-type electrode lines 150a separated from each other, and the second electrode layer 160 includes a plurality of second-type electrode lines 160a2 separated from each other and a connection portion 160a 1. The buffer insulating layer 120a has a plurality of first openings 122a between the first-type electrode lines 150a and the connection portions 160a1 of the second electrode layer 160. The connecting portion 160a1 of the second electrode layer 160 extends into the first opening 122a and is electrically connected to a corresponding first-type electrode line 150 a. The light emitting diode 140a electrically connects the first type electrode 141a to a first type electrode line 150a through the pads 130a1, 130a2, and the second type electrode 143a is electrically connected to a second type electrode line 160a2, and then provides the first type electric carriers through the components such as the external power circuit, etc. to enter the first type semiconductor layer 142a from the first type electrode line 150a, the connecting portion 160a1 and the pad 131a1, and provides the second type electric carriers to enter the second type semiconductor layer 146a from the second type electrode line 160a2 and the pad 131a2, so as to form an electric path to make the light emitting diode 140a emit light.
In short, since the display panel 100a of the present embodiment has the buffer insulating layer 120a, and the young's modulus of the buffer insulating layer 120a is less than 10GPa, when the light emitting diode 140a is bonded to the substrate 110, the buffer insulating layer 120a can absorb the stress generated during bonding, thereby increasing the bonding yield, and further increasing the process yield and the structural reliability of the display panel 100a of the present embodiment.
It should be noted that the following embodiments follow the reference numerals and parts of the contents of the foregoing embodiments, wherein the same reference numerals are used to indicate the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.
Fig. 1C is a schematic partial cross-sectional view of a display panel according to another embodiment of the invention. Referring to fig. 1B and fig. 1C, the display panel 100B of the present embodiment is similar to the display panel 100a of fig. 1B, and the difference between the two is: the light emitting diode 140B of the present embodiment is different from the light emitting diode 140a of fig. 1B. In detail, the led 140b of the present embodiment further includes a blind via 145b, wherein the blind via 145b sequentially passes through the first type semiconductor layer 142b, the active layer 144b and the second type semiconductor layer 146 b. The insulating layer 148b is further extended to be disposed on the inner wall of the blind via 145b, the second type electrode 143b is extended from the surface 148b3 of the insulating layer 148b to the blind via 145b, and the second contact opening 148a2 is also located in the blind via 145b to expose the second type semiconductor layer 146b so that the second type electrode 143b electrically contacts the second type semiconductor layer 146 b.
Fig. 1D is a partial cross-sectional view of a display panel according to another embodiment of the invention. The display panel 100c of the present embodiment includes a substrate 110, a buffer insulating layer 120c, a plurality of pads 130c, a plurality of light emitting diodes 140c, a first electrode layer 150, and a second electrode layer 160.
In detail, the light emitting diode 140c of the present embodiment is embodied as a vertical light emitting diode. The light emitting diode 140c includes a first type semiconductor layer 142c, an active layer 144c, a second type semiconductor layer 146c, a first type electrode 141c, and a second type electrode 143 c. The active layer 144c is disposed between the first type semiconductor layer 142c and the second type semiconductor layer 146c, the first type electrode 141c is disposed between the first type semiconductor layer 142c and the pad 130b, and the second type electrode 143c is disposed on the second type semiconductor layer 146 c. That is, the first-type electrode 141c and the second-type electrode 143c are respectively disposed on two sides of the active layer 144 c. Furthermore, the buffer insulating layer 120c of the present embodiment is disposed on the substrate 110, and the first electrode layer 150 is disposed on the buffer insulating layer 120c and includes a plurality of first-type electrode lines 150c separated from each other. The light emitting diodes 140c are respectively bonded to the corresponding first type electrode lines 150c through the pads 130 c. Similarly, the orthographic projection of the light emitting diode 140c on the substrate 110 is overlapped with the orthographic projection of the buffer insulating layer 120c on the substrate 110, so that the stress generated by the bonding can be reduced through the buffer insulating layer 120c during the bonding, and the bonding yield is improved.
As can be seen from fig. 1B, fig. 1C and fig. 1D, the present invention is not limited to the light emitting diodes 140a, 140B and 140C, and the buffer insulating layers 120a and 120C made of organic materials are disposed between the light emitting diodes 140a, 140B and 140C and the substrate 110, which is within the protection scope of the present invention.
Fig. 2A to 2E are schematic cross-sectional views illustrating a manufacturing method of the display panel of fig. 1A. It should be noted that fig. 2A to 2D are cross-sectional views taken along line B-B 'of fig. 1A, and fig. 2E is a cross-sectional view taken along line C-C' of fig. 1A. In the manufacturing process, referring to fig. 1A and fig. 2A, according to the manufacturing method of the display panel of the present embodiment, first, a substrate 110 is provided; next, first-type electrode lines 150a separated from each other are formed on the upper surface 116 of the substrate 110. Next, referring to fig. 1A and fig. 2B, a buffer insulating material layer 120 is formed on the upper surface 116 of the substrate 110, and covers the upper surface 116 and the first-type electrode lines 150 a. The first electrode line 150a may be formed by depositing a whole first electrode layer and then performing photolithography and etching; or by vapor deposition after defining the pattern by using a mask. In the present embodiment, the plurality of first-type electrode lines 150a are separated from each other and extend from the display region 112 to the peripheral region 114 to be electrically connected to an external circuit (not shown).
Next, referring to fig. 1A and fig. 2C, a first opening 122a is formed in the buffer insulating material layer 120 to expose a portion of the upper surface 152a of the first-type electrode line 150a, thereby completing the fabrication of the buffer insulating layer 120 a. Then, referring to fig. 2D and fig. 2E, a patterned second electrode layer 160 is formed on the buffer insulating layer 120a, and a connection portion 160a1 and a second type electrode line 160a2 are formed independently from each other, wherein the connection portion 160a1 extends from the surface 124a of the buffer insulating layer 120a into the first opening 122a to be electrically connected to the first type electrode line 150a, and the second type electrode line 160a2 is disposed on the surface 124a of the buffer insulating layer 120a and separated from the connection portion 160a1 and arranged alternately, in the present embodiment, the second type electrode line 160a2 extends from the display area 112 to the peripheral area 114 to be electrically connected to an external circuit (not shown), and the external circuit provides current carriers to illuminate the light emitting diode 140a through the first type electrode line 150a and the second type electrode line 160a 2. However, the present invention is not limited to the circuit design of the first-type electrode line 150a and the second-type electrode line 160a2, and the first-type electrode line 150a and the second-type electrode line 160a2 may also be formed in the display area 112 and connected to the circuit in the substrate 110 to provide the current for the light emitting diode 140 a.
Finally, as shown in fig. 1A, the pads 130a1, 130a2 are formed on the connecting portion 160a1 and the second type electrode line 160a2, and the led 140a is bonded on the substrate 110 corresponding to the pads 130a1, 130a2, wherein the led 140a is bonded to the substrate 110 by electrically connecting the pads 130a1, 130a 2. Thus, the display panel 100a is completed.
Fig. 3 is a schematic partial cross-sectional view of a display panel according to another embodiment of the invention. Referring to fig. 1B and fig. 3, the display panel 100d of the present embodiment is similar to the display panel 100a of fig. 1B, and the difference between the two is: the display panel 100d of the present embodiment further includes an inorganic insulating layer 170d, wherein the inorganic insulating layer 170d is disposed on the upper surface 116 of the substrate 110 and between the buffer insulating layer 120d and the substrate 110. The inorganic insulating layer 170d covers the upper surface 116 and the first-type electrode lines 150a and has a plurality of second openings 172 d. The second opening 172d is disposed corresponding to the first opening 122d of the buffer insulating layer 120d and is communicated with the first opening 122d, wherein a diameter of the second opening 172d is substantially the same as a diameter of the first opening 122 d. The connection portion 160a1 of the second electrode layer 160 extends into the first opening 122d and the second opening 172d and is electrically connected to the first type electrode line 150 a. Here, the thickness of the inorganic insulating layer 170d is much smaller than that of the buffer insulating layer 120d, and the material of the inorganic insulating layer 170d is, for example, silicon dioxide (SiO2) or silicon nitride (SiN), which is provided for the purpose of improving the reliability of the structure and increasing the process yield. In addition, the led 140 shown here can be the led 140a or the led 140b, which is not limited herein.
Fig. 4 is a schematic partial cross-sectional view of a display panel according to another embodiment of the invention. Referring to fig. 3 and fig. 4, the display panel 100e of the present embodiment is similar to the display panel 100d of fig. 3, and the difference between the two is: the buffer insulating layer 120e of the present embodiment is a patterned design and is formed under the second electrode layer 160. Preferably, the area ratio of the light emitting diode 140 overlapping the orthographic projection of the buffer insulating layer 120e on the substrate 110 is between 50% and 100% of the orthographic projection area of the light emitting diode 140 on the substrate 110. That is, the orthographic projection of the light emitting diode 140 on the substrate 110 may partially overlap or completely overlap the orthographic projection of the buffer insulating layer 120e on the substrate 110. Here, the pattern of the buffer insulating layer 120e is similar to that of the second electrode layer 160. More specifically, the second electrode layer 160 and the buffer insulating layer 120e may be patterned by the same etching process, such that the edge of the pattern of the buffer insulating layer 120e is aligned with the edge of the connection portion 160a1, and the edge of the second type electrode line 160a2 is also aligned. Here, the thickness of the inorganic insulating layer 170e is much smaller than that of the buffer insulating layer 120 e. In addition, the led 140 shown here can be the led 140a or the led 140b, which is not limited herein.
Fig. 5 is a partial cross-sectional view of a display panel according to another embodiment of the invention. Referring to fig. 3 and fig. 5, the display panel 100f of the present embodiment is similar to the display panel 100d of fig. 3, and the differences include: the display panel 100f of the present embodiment further includes an inorganic insulating layer 170f and a patterned buffer insulating layer 120f, wherein the inorganic insulating layer 170f is disposed between the second electrode layer 160 and the buffer insulating layer 120f, and extends to be disposed on the upper surface 116 of the substrate 110 and the inner wall of the first opening 122 f. The buffer insulating layer 120f is patterned corresponding to the second electrode layer 160 and the light emitting diode 140, so that the stress generated by the buffer bonding of the buffer insulating layer 120f is also present under the second electrode layer 160 when the light emitting diode 140 is bonded. The inorganic insulating layer 170f has a plurality of second openings 172f, and the second openings 172f are disposed corresponding to the first openings 122f of the buffer insulating layer 120 f. The aperture of each second opening 172f is smaller than the aperture of each first opening 122 f. The connection portion 160a1 of the second electrode layer 160 extends into the second opening 172f and is electrically connected to the first electrode layer 150. Here, the thickness of the inorganic insulating layer 170f is much smaller than that of the buffer insulating layer 120 f. In addition, the led 140 shown here can be the led 140a or the led 140b, which is not limited herein.
In summary, since the display panel of the invention has the buffer insulating layer, and the young modulus of the buffer insulating layer is less than 10GPa, when the light emitting diode is electrically connected to the pad and bonded to the substrate through the pad, the buffer insulating layer can absorb the stress generated during bonding, so as to improve the bonding yield and further increase the structural reliability of the display panel of the invention.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (19)
1. A display panel, comprising:
the display device comprises a substrate, a display panel and a display panel, wherein the substrate is provided with a display area and a peripheral area adjacent to the display area;
a buffer insulating layer disposed on the substrate, wherein the Young's modulus of the buffer insulating layer is less than 10 GPa;
a plurality of pads disposed on the buffer insulating layer and disposed in the display region of the substrate; and
and the light-emitting diodes are electrically connected to the pads and are bonded to the display area of the substrate through the pads, wherein the buffer insulating layer is positioned between the light-emitting diodes and the substrate, and the orthographic projections of the light-emitting diodes on the substrate completely overlap the orthographic projections of the buffer insulating layer on the substrate.
2. The display panel of claim 1, wherein each of the light emitting diodes is a horizontal light emitting diode.
3. The display panel of claim 2, wherein each of the light emitting diodes comprises a first type semiconductor layer, a second type semiconductor layer, an active layer, an insulating layer, a first type electrode, and a second type electrode, the active layer is disposed between the first type semiconductor layer and the second type semiconductor layer, the first type semiconductor layer is located between the active layer and the buffer insulating layer, the insulating layer is located between the first type semiconductor layer and the substrate and has a first contact opening and a second contact opening, the first type electrode extends from one surface of the insulating layer to the first contact opening and is electrically connected with the first type semiconductor layer, the second type electrode extends into the second contact opening from the surface of the insulating layer and is electrically connected with the second type semiconductor layer.
4. The display panel of claim 3, wherein each of the light emitting diodes further comprises a blind via sequentially passing through the first type semiconductor layer, the active layer and the second type semiconductor layer, and the second contact opening of the insulating layer is further disposed in the blind via.
5. The display panel according to claim 3, further comprising:
a first electrode layer disposed on an upper surface of the substrate; and
a second electrode layer disposed on the first electrode layer and the buffer insulating layer, wherein the buffer insulating layer has a plurality of first openings, a portion of the second electrode layer extends into the first openings and is electrically connected to the first electrode layers, and the light emitting diodes are electrically connected to the second electrode layers through the pads.
6. The display panel of claim 5, wherein the first electrode layer comprises a plurality of first type electrode lines separated from each other, the second electrode layer comprises a plurality of connecting portions separated from each other and a plurality of second type electrode lines, the plurality of connecting portions are electrically connected to the plurality of first type electrodes of the plurality of light emitting diodes, the plurality of second type electrode lines are electrically connected to the plurality of second type electrodes of the plurality of light emitting diodes, and the plurality of connecting portions extend into the plurality of first openings of the buffer insulating layer to be electrically connected to the first electrode layer.
7. The display panel according to claim 5, further comprising:
an inorganic insulating layer disposed on the upper surface of the substrate and between the buffer insulating layer and the substrate, wherein the inorganic insulating layer covers the upper surface and the first electrode layer and has a plurality of second openings, the second openings are communicated with the first openings of the buffer insulating layer, and a portion of the second electrode layer extends into the first openings and the second openings and is electrically connected to the first electrode layer.
8. The display panel of claim 5, wherein the buffer insulating layer is a patterned film layer, and the pattern of the buffer insulating layer is substantially the same as the pattern of the second electrode layer.
9. The display panel according to claim 5, further comprising:
and an inorganic insulating layer disposed between the second electrode layers and the buffer insulating layer, wherein the inorganic insulating layer has a plurality of second openings communicated with the first openings of the buffer insulating layer, and a portion of the second electrode layer extends to the second openings to be electrically connected to the first electrode layer.
10. The display panel of claim 1, wherein each of the light emitting diodes is a vertical light emitting diode.
11. The display panel according to claim 10, further comprising:
and a plurality of first electrode lines disposed on the buffer insulating layer and separated from each other, wherein the plurality of first electrode lines are respectively located between the plurality of pads and the buffer insulating layer, and the plurality of light emitting diodes are respectively bonded to the plurality of first electrode lines through the plurality of pads.
12. The display panel according to claim 11, further comprising:
and a plurality of second electrode lines respectively disposed on the plurality of light emitting diodes, wherein the plurality of light emitting diodes are respectively located between the plurality of second electrodes and the plurality of first electrodes.
13. The display panel of claim 1, wherein the buffer insulating layer has a thickness of 3 to 5 μm.
14. The display panel of claim 1, wherein the buffer insulating layer is made of an organic material.
15. The display panel according to claim 1, wherein the young's modulus of the buffer insulating layer is between 2.9GPa and 3.6 GPa.
16. The display panel according to claim 1, wherein the buffer insulating layer has a residual stress of 25 to 45 MPa.
17. The display panel according to claim 1, wherein the buffer insulating layer has an elongation at break of 5% to 10%.
18. The display panel of claim 1, wherein the substrate comprises a sapphire substrate, a glass substrate, a thin film transistor substrate, a submount, a cmos circuit substrate, or a lcos substrate.
19. The display panel of claim 1, wherein the thickness of each of the light emitting diodes is between 5 microns and 6 microns, and the thickness of each of the pads is between 0.1 microns and 10 microns.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TW201216474A (en) * | 2010-10-12 | 2012-04-16 | Au Optronics Corp | Thin film transistor and display panel |
| TW201711227A (en) * | 2015-09-04 | 2017-03-16 | 錼創科技股份有限公司 | Light emitting device |
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| US9640729B2 (en) * | 2013-07-03 | 2017-05-02 | Koninklijke Philips N.V. | LED with stress-buffer layer under metallization layer |
| US10910350B2 (en) * | 2014-05-24 | 2021-02-02 | Hiphoton Co., Ltd. | Structure of a semiconductor array |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201216474A (en) * | 2010-10-12 | 2012-04-16 | Au Optronics Corp | Thin film transistor and display panel |
| TW201711227A (en) * | 2015-09-04 | 2017-03-16 | 錼創科技股份有限公司 | Light emitting device |
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Effective date of registration: 20240509 Address after: 8th Floor, No.13 Kezhong Road, Zhunan Town, Miaoli County, Hsinchu Science Park, Taiwan, China, China Patentee after: PlayNitride Inc. Country or region after: TaiWan, China Address before: Grand Cayman Island, Grand Exhibition Hall Commercial Center, Olander Road, 802 West Bay Road, PO Box 32052, KY1-1208, Cayman Islands Patentee before: PlayNitride Inc. Country or region before: Cayman Islands |